1. Shared Memory Consistency Models: A Tutorial
Authors: Sarita V. Adve
Kourosh Gharachorloo
Sourced from Adve's Presentation

2. Sourced from Adve's Presentation
Overview
Memory Consistency Model
Implicit Memory Model -- Sequential Consistency
Relaxed Memory Model (system-centric)
Relaxed models (program-centric)
Sourced from Adve's Presentation

3. Memory Consistency Model
Definition: Order in which memory operations will appear to execute
-- what value can a read return
-- a read should return the value of the “last” write to the same memory location
Affecting 3P
-- Programmability (easy-of-programming)
-- Performance (optimization)
-- Portability (moving software across different systems)
Sourced from Adve's Presentation

4. Sourced from Adve's Presentation
Implicit Memory Model
Sequential consistency (SC) [Lamport]
Result of an execution appears as if
All operations executed in some sequential order
Memory operations of each process in program order
MEMORY P1 P3 P2 Pn
Sourced from Adve's Presentation

5. Sourced from Adve's Presentation
Implicit Memory Model
Sequential consistency (SC) [Lamport]
Result of an execution appears as if
All operations executed in some sequential order
Memory operations of each process in program order
MEMORY P1 P3 P2 Pn
Two aspects:
Program order
Atomicity
Sourced from Adve's Presentation

6. Architectures without Caches: example 1
Initially Flag1 = Flag2 = 0
P P2
Flag1 = Flag2 = 1
if (Flag2 == 0) if (Flag1 == 0)
critical section critical section
Execution:
(Operation, Location, Value) (Operation, Location, Value)
Write, Flag1, Write, Flag2, 1
Read, Flag2, Read, Flag1, ____
Sourced from Adve's Presentation

7. Architectures without Caches: example 1
Initially Flag1 = Flag2 = 0
P P2
Flag1 = Flag2 = 1
if (Flag2 == 0) if (Flag1 == 0)
critical section critical section
Execution:
(Operation, Location, Value) (Operation, Location, Value)
Write, Flag1, Write, Flag2, 1
Read, Flag2, Read, Flag1, 0?
Sourced from Adve's Presentation

8. Architectures without Caches: example 1
P P2
(Operation, Location, Value) (Operation, Location, Value)
Write, Flag1, Write, Flag2, 1
Read, Flag2, Read, Flag1, 0
Can happen if
Write buffers with read bypassing
Overlap, reorder write followed by read in h/w or compiler
Allocate Flag1 or Flag2 in registers
Optimization by use of writer buffer is safe on convention uniprocessor, but it can violate SC in multiprocessor system.
Sourced from Adve's Presentation

9. Architectures without Caches: example 1
Write buffer
Sourced from Adve's Presentation

10. Architectures without Caches: example 2
Initially Head = Data = 0
P P2
Data = 2000; while (Head != 1) {;}
Head = 1; = Data;
Write, Data, Read, Head, 0
Write, Head, 1
Read, Head, 1
Read, Data, 0?
Can happen if
Overlap or reorder writes or non-blocking reads in hardware or compiler
Sourced from Adve's Presentation

11. Architectures without Caches: example 2
Overlapped writes
Sourced from Adve's Presentation

12. Architectures without Caches: example 3
Non-blocking reads
Sourced from Adve's Presentation

13. Architectures With Caches
Cache Coherence and SC
Cache Coherence
A write is visible to all processors
Serialization of writes to the same location SC
Serialization of writes to all locations
Operations appear to execute in program order
SC implies Cache Coherence:
A memory consistency model as the policy that places an early and late bound on when a new value can be propagated by invalidating or updating
Atomicity for writes
Propagating changes to cache copies in a non-atomic operation
Serialize write can avoid the violation of SC
Ordering of updates/invalidates between source and destination is preserved by network
Or delay an update/invalidate from being sent out until any updates or invalidates from previous write are acknowledged
Sourced from Adve's Presentation

14. Sourced from Adve's Presentation
SC Summary
SC constrains all memory operations:
Write  Read
Write  Write
Read  Read, Write
Simple model for reasoning about parallel programs
But, intuitively reasonable reordering of memory operations in a uniprocessor may violate sequential consistency model in multiprocessor
Modern microprocessors reorder operations all the time to obtain performance (write buffers, overlapped writes,non-blocking reads…).
How do we reconcile sequential consistency model with the demands of performance?
Sourced from Adve's Presentation

15. Sourced from Adve's Presentation
Relaxed Memory Model
Optimizations
Program order relaxation:
Write  Read
Write  Write
Read  Read, Write
Read others’ write early
Read own write early
Sourced from Adve's Presentation

16. Relaxed Memory Model (system-centric)
Models provide safety net
Models maintain uniprocessor data and control dependences, write serialization
Sourced from Adve's Presentation

17. System-Centric model assessment
System-centric models provide higher performance than SC
BUT how about 3P criteria
Programmability?
Programmer need to consider the correctness with the optimization the specific model provides
Portability?
Many different models
Performance?
Can we do better?
Programmer-Centric Model
Sourced from Adve's Presentation

18. Programmer-Centric Models
Data operation executed more aggressively
Programmer provide information about memory operations
System based on the model exploit the optimization without violating consistency
Sourced from Adve's Presentation

19. Programmer-Centric Model
Sourced from Adve's Presentation

20. Programmer-Centric Model Assessment
3P criteria
Programmability
System ensure correctness instead of safety nets used by programmer
Performance
Optimization enabled by the WO can be applied
Information enables more aggressive optimization
Portability
Not based on specific model
Sourced from Adve's Presentation