1. ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2016 Microprogramming (Appendix D)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
Spring 2016, Mar
ELEC / Lecture 8

2. Alternatives for Control Unit (CU)
Hard-wired (hardware)
Random logic, programmable logic array (PLA), or ROM
Fast
Inflexible
Firmware
Microprogrammed or microcoded CU
Control implemented like a computer (microcomputer)
Microinstructions
Microprogram
Flexible
Software-like changes to instruction set possible
Completely different instruction sets can be emulated
Speed limited by microcomputer memory
Spring 2016, Mar
ELEC / Lecture 8

3. Multicycle Datapath Memory ALU Instr. reg. (IR) A Reg. PC
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
11-15
Register file
ALU
ALUSrcA
ALUSrcB
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
RegDst
IRWrite 4
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALU
control
ALUOp
0-5
Spring 2016, Mar
ELEC / Lecture 8

4. Multicycle Control FSM
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0 1
Instr.
fetch/
adv. PC
Instr.
decode/reg.
fetch/branch
addr.
lw or sw J R B 3 2
Read
memory
data
Compute
memory
addr.
ALU
operation
Write
jump addr.
to PC
Write PC
on branch
condition lw 6 8 9 sw 4 5
Write
register
Write
memory
data 7
Write
register
Spring 2016, Mar
ELEC / Lecture 8

5. States and Outputs Suppose 10 states are encoded 0000 through 1001.
State code completely determines 16 control signals (Moore machine).
States 0 (0000), 3 (0011) and 6 (0110)
Next state ← present state + 1
State 1 (0001) – opcode determines next state
State 2 (0010) for lw or sw
State 6 (0110) for R-type of instruction
State 8 (1000) for branch instruction
State 9 (1001) for jump instruction
State 2 (0010) – opcode determines next state
State 3 (0011) for lw
State 5 (0101) for sw
States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) – next state is unconditionally 0 (0000)
Spring 2016, Mar
ELEC / Lecture 8

6. A Program-Like Implementation
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0000
0001
Instr.
fetch/
adv. PC
Instr.
decode/reg.
fetch/branch
addr.
lw or sw J R
0011 B
0010
Read
memory
data
ALU
operation lw
Compute
memory
addr.
Write PC
on branch
condition
Write
jump addr.
to PC
0110 sw
1000
1001
0100
0101
0111
Write
memory
data
Write
register
Write
register
Spring 2016, Mar
ELEC / Lecture 8

7. Implementing with ROM Control PLA or ROM 16 words 16 16 control
signals 2
PLA input or
ROM address
Select
one of
4 ways 4
Four flip-flops
State sequencer
6-bit
opcode 6
Spring 2016, Mar
ELEC / Lecture 8

8. ROM and State Sequencer
Control ROM
Sixteen
18-bit words
4-bit address 16
Control
signals to
datapath 2
0001
AddrCtl go to
st. 0
st. + 1
st. 2,6,8,9
st. 3,5
Address 4 4
4-bit state flip-flops
MUX
Adder
Advance state
0000 4
Dispatch ROM 2
Dispatch ROM 1
6-bit
Opcode
from IR
sw or lw
ROM Address
sw, lw, R,
B or J 6
Spring 2016, Mar
ELEC / Lecture 8

9. Dispatch ROM Contents Each dispatch ROM has sixty-four 4-bit words
Address is 6-bit opcode
Content is next state (4-bits)
Dispatch ROM 1
Instruction
Address
(Opcode)
Content lw
100011
0010 sw
101011 R
000000
0110 B
000100
1000 J
000010
1001
Dispatch ROM 2
Instruction
Address
(Opcode)
Content lw
100011
0011 sw
101011
0101
Spring 2016, Mar
ELEC / Lecture 8

10. Control ROM Contents Control ROM has sixteen 18-bit words:
bits 0-1, AddrCtl to control mux
bits 2-17, sixteen control signals for datapath
Address is 4-bit state of control machine
Addr.
bits 17-2
bits 1-0
0000 11
0001 01
0010 10
0011
0100 00
0101
0110
0111
1000
1001
Spring 2016, Mar
ELEC / Lecture 8

11. Microprogram: Basic Idea
The control unit in a computer generates an output (sequence of control signals) for each instruction.
Suppose we break down each instruction into a series of smaller operations (microinstructions), such as, fetch, decode, etc.
Then, implement the control unit as a small computer (within the computer) that executes a sequence of microinstructions (microprogram) for each instruction.
M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Report of Manchester University Computer Inaugural Conference, pp , 1951.
Reprinted in E. E. Swartzlander (editor), Computer Design Development: Principal Papers, pp , Rochelle Park, NJ: Hayden, 1976.
Spring 2016, Mar
ELEC / Lecture 8

12. Maurice V. Wilkes
Born June 26, 1913, Staffordshire, UK, died November 29, 2010
1967 Turing Award citation:
Professor Wilkes Is best known as the builder and designer of the EDSAC, the first computer with an internally stored program. Built in 1949, the EDSAC used a mercury delay line memory. He is also known as the author, with Wheeler and Gill, of a volume on “Preparation of Programs for Electronic Digital Computers” in 1951, in which program libraries were effectively introduced.
Spring 2016, Mar
ELEC / Lecture 8

13. Microcoded Control Unit
Microcode word
Sixteen
18-bit words
4-bit address
Microcode
memory 16
Control
signals to
datapath
0001
AddrCtl
Address
Sequencing
field 2 4 4
μPC
4-bit state flip-flops
MUX
Adder
0000
Dispatch ROM 2
Dispatch ROM 1
Opcode
from IR
Address
select
logic
lw or sw
sw, lw, R,
B or J
ROM address 6
Spring 2016, Mar
ELEC / Lecture 8

14. Implementing the Idea
Use a memory type implementation for control unit.
Create a software infrastructure to automatically translate instructions into memory data (microcode):
Microinstructions – define a machine language in which instructions can be described
Microprogram – an instruction described as a sequence of microinstructions
Microassembler – converts microprogram to (binary) microcode
Is there a micro-compiler?
Spring 2016, Mar
ELEC / Lecture 8

15. Microprogramming A microinstruction set is defined.
To program the control of a computer for an instruction set, a programmer writes a microprogram for each machine instruction.
Each micrprogram is converted into microcode, specific to the datapath hardware, by a microassembler and the entire microcode is loaded in the microcode memory of the control unit (CU).
Spring 2016, Mar
ELEC / Lecture 8

16. Breaking Up MIPS Instructions
R-type instruction:
Fetch
Decode
ALU operation
Write register
lw:
Memory address computation
Read memory
Spring 2016, Mar
ELEC / Lecture 8

17. Microinstructions for MIPS ISA
Fetch fetch instruction
Decode decode instruction, read registers, calculate branch address
RegWr write register
LWSW1 compute memory address
LW2 memory read
SW2 memory write
R1 register type execution
BEQ1 branch execution
JUMP1 jump execution
Spring 2016, Mar
ELEC / Lecture 8

18. Let’s Construct MIPS Instructions
sw:
Fetch
Decode
LWSW1
SW2
Branch:
BEQ1
Jump:
JUMP1
R-type instruction:
Fetch
Decode R1
RegWr
lw:
LWSW1
LW2
Spring 2016, Mar
ELEC / Lecture 8

19. Microinstruction Format
Just one instruction with seven arguments
A label or name for control state(s), e.g., Fetch, MEM1, etc.
Seven arguments and their possible values:
ALU control add, subtract or funct. code # result to ALUOut
SRC1 PC or A
SRC2 B, 4, extend or extend-shift
Reg. control Read # read two reg. specified by IR into A and B
Write ALU # write ALUOut to register file
Write MDR # register file ← MDR
Memory Read PC # IR ← M[ PC ]
Read ALU # MDR ← M[ ALUOut ]
Write ALU # M[ ALUOut ] ← B
PCWrite ALU # write PC from ALU
ALU cond. # If zero = 1, PC ← ALUOut
Jump addr. # PC ← jump address
Sequencing Seq # choose next μInst. Sequentially
fetch # go to first μInst. to begin new instr.
Dispatch i # use Dispatch ROM i, i = 1 or 2
Spring 2016, Mar
ELEC / Lecture 8

20. Sequencing Illustrated
Fetch 1
Instr.
fetch/
adv. PC
Sequencing
= seq
Instr.
decode/reg.
fetch/branch
addr.
State 0
Fetch
Dispatch 1
JUMP1 3 2
LWSW1 R1
BEQ1
LW2
Read
memory
data
Compute
memory
addr.
ALU
operation
Write
jump addr.
to PC
Write PC
on branch
condition lw 6
Dispatch 2 8
seq 9
seq
SW2 4 5
Write
register
Write
memory
data 7
Write
register
Fetch
Spring 2016, Mar
ELEC / Lecture 8

21. Microinstruction Arguments
Value
μCode value
Action
ALU Ctrl
Add
ALUOp = 00
ALU adds
Subt
ALUOp = 01
ALU subtracts for beq
Funct code
ALUOp = 10
ALU executes R-type instruction
SRC1 PC
ALUSrcA = 0
PC is first ALU input A
ALUSrcA = 1
Reg A is first ALU input
SRC2 B
ALUSrcB = 00
Reg B is second ALU input 4
ALUSrcB = 01
Constant 4 is second ALU input
Extend
ALUSrcB = 10
Sign extension unit is second ALU input
Extshft
ALUSrcB = 11
2-bit shift unit is second ALU input
Spring 2016, Mar
ELEC / Lecture 8

22. Microinstruction Arguments (Cont.)
Value
μCode value
Action
Reg. Ctrl
Read
Load A and B from Register file
Write ALU
RegWrite = 1
RegDst = 1
MemtoReg = 0
An IR-specified register in Register file is written from ALUOut
Write MDR
RegDst = 0
MemtoReg = 1
An IR-specified register in Register file is written from MDR
Memory
Read PC
MemRead = 1
IorD = 0
IRWrite = 1
IR ← M[ PC ]
MDR ← M[ PC ]
Read ALU
IorD = 1
MDR ← M[ ALUOut ]
MemWrite = 1
M[ ALUOut ] ← B
Spring 2016, Mar
ELEC / Lecture 8

23. Microinstruction Arguments (Cont.)
Field
μInstr. value
μCode value
Action
PC Write Ctrl
ALU
PCSource = 00
PCWrite = 1
Register file loads A and B
ALUOut-cond
PCSource = 01
PCWriteCond = 1
An IR-specified register in Register file is written from ALUOut
Jump address
PCSource = 10
An IR-specified register in Register file is written from MDR
Sequencing
Seq
AddrCtl = 11
Choose next μInstr. sequentially
Fetch
AddrCtl = 00
Go to first μInstr. to begin new instruction
Dispatch 1
AddrCtl = 01
Use Dispatch ROM 1
Dispatch 2
AddrCtl = 10
Use Dispatch ROM 2
Spring 2016, Mar
ELEC / Lecture 8

24. Microinstruction Fetch
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
Fetch Add PC 4 Read PC ALU Seq
Decode Add PC ExtShft Read Dispatch 1
Microassembler produces the following microcode:
MemRead
IorD
IRWrite
MemWrite
RegWrite
RegDst
MemtoReg
ALUOp
PCSource
PCWrite
PCWriteCond
Addrctl
ALUSrcA
ALUSrcB
Spring 2016, Mar
ELEC / Lecture 8

25. Microprogram for lw and sw
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
LWSW1 Add A Extend Dispatch 2
LW Read ALU Seq
RegWr Write MDR Fetch
SW Write ALU Fetch
Microprogram consists of four microinstructions.
Spring 2016, Mar
ELEC / Lecture 8

26. Microprogram for R-Type Instruction
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
R1 Funct code A B Seq
RegWr Write ALU Fetch
Go to next μInstr.
Go to μInstr. Fetch
Microprogram consists of two microinstructions.
Spring 2016, Mar
ELEC / Lecture 8

27. Microprogram for beq Instruction
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
BEQ1 Subt A B ALUOut-cond Fetch
If (zero) then PC ← ALUOut Go to μInstr. Fetch
Microprogram consists of one microinstruction.
Spring 2016, Mar
ELEC / Lecture 8

28. Microprogram for jump Instruction
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
JUMP Jump address Fetch
Microprogram consists of one microinstruction.
Spring 2016, Mar
ELEC / Lecture 8

29. μProgram for Multi-Cycle CU
Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.
ctrl. ctrl. ctrl.
Fetch Add PC Read PC ALU Seq
Decode1 Add PC ExtShft Read Disp. 1
LWSW1 Add A Extend Disp. 2
LW Read ALU Seq
RegWr Write MDR Fetch
SW Write ALU Fetch
R1 FntCd. A B Seq
RegWr Write ALU Fetch
BEQ1 Subt A B ALUOut-cond Fetch
JUMP Jump address Fetch
Spring 2016, Mar
ELEC / Lecture 8

30. Multicycle Datapath Memory ALU Instr. reg. (IR) A Reg. PC
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
MicrocodedControl
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
11-15
Register file
ALU
ALUSrcA
ALUSrcB
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
RegDst
IRWrite 4
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALU
control
ALUOp
0-5
Spring 2016, Mar
ELEC / Lecture 8

31. Microcode Operation μPC is always initialized to 0000
Load starting instruction address in PC
Clock control and datapath
Spring 2016, Mar
ELEC / Lecture 8

32. How Microcode Works Sixteen 18-bit words 4-bit address Microcode
memory 16
clk 1: Set
Datapath
for Fetch
0001 in clk 2
0001
AddrCtl
μPC
Address
Sequencing
field 4
0000 11 4
MUX
Adder
0000
Opcode
from IR
In clk 2
Dispatch ROM 2
Dispatch ROM 1
Address
select
logic
lw or sw
sw, lw, R,
B or J
ROM address 6
Spring 2016, Mar
ELEC / Lecture 8

33. Multicycle Control FSM
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0 1
Instr.
fetch/
adv. PC
Instr.
decode/reg.
fetch/branch
addr.
lw or sw J R B 3 2
Read
memory
data
Compute
memory
addr.
ALU
operation
Write
jump addr.
to PC
Write PC
on branch
condition lw 6 8 9 sw 4 5
Write
register
Write
memory
data 7
Write
register
Spring 2016, Mar
ELEC / Lecture 8

34. Summary
Hard-wired control: A finite state machine implemented typically using programmable logic array (PLA) or random logic.
Microinstruction: A one-clock instruction that asserts a set of control signals to the datapath and specifies what microinstruction to execute next.
Microprogram: A sequence of microinstructions that implements a multicycle (or single cycle) instruction.
Microcode: Machine code of a microprogram, generally produced by a microassembler.
Microprogrammed or microcoded control: A method of specifying control that uses microcode rather than a finite state machine.
Spring 2016, Mar
ELEC / Lecture 8

35. Further on Microprogramming
Preceding discussion is based on:
D. A. Patterson and J. L. Hennessey, Computer Organization and Design, Second Edition, San Francisco: Morgan-Kaufman, 1998, Chapter 5, pp
Terms “microcomputer”, “microarchitecture” and “micropipeline” are not related to microprogramming.
Nanoprogramming: Two levels of microprogramming – a “recursive” control:
Nanodata Corp., QM-1 Hardware Level Users Manual, 2nd Ed., Williamsville, NY, 1972.
J. P. Hayes, Computer Architecture and Organization, Section 4.4.3, NY: McGraw-Hill, 1978.
Virtual machines: Any program can be run on any instruction set using an interpreter. Example, Java.
Spring 2016, Mar
ELEC / Lecture 8