Presentation is loading. Please wait.

Presentation is loading. Please wait.

Another Performance Evaluation of Memory Hierarchy in Embedded Systems

Published byΚαλλιγένεια Ζυγομαλάς Modified over 5 years ago

Similar presentations

Presentation on theme: "Another Performance Evaluation of Memory Hierarchy in Embedded Systems"— Presentation transcript:

1 Another Performance Evaluation of Memory Hierarchy in Embedded Systems
Nelson Barnes CPE 631 04/14/03

2 Outline Introduction Related Work Problem Statement Proposed Solutions
Experimental Setup Experimental Results Conclusions Here is the Outline of today’s lecture. First, we shall give a short overview of major trends and breakthroughs in Computer Technology for last 50 years. Then, we will give an answer to the question “What is Computer Architecture”. After these two introductory topics we will consider Measuring and Reporting Performance and major Quantitative Principles of Computer Design. 11/24/2018 UAH, ECE

3 Why is cache design so important in embedded systems?
Introduction Why is cache design so important in embedded systems? 11/24/2018 UAH, ECE

4 Cache Design Parameters
Cache organization Unified vs. Split (Instruction + Data) caches Cache size Cache block (line) size Block placement policy Direct-mapped, fully-associative, set-associative Block replacement policy Random, Least-Recently Used (LRU), Round-robin, Pseudo-LRU, OPT (Optimal) 11/24/2018 UAH, ECE

5 Related Work Mibench vs. NetBench 11/24/2018 UAH, ECE

6 Problem Statement Comprehensive performance evaluation of cache design issues in embedded systems Split versus unified cache Cache placement and size Cache block size Block replacement policy Performance metrics Static measure: the number of cache misses per 1K instructions executed - measured at the end of application execution Dynamic measure: The number of cache misses per 1K instructions executed - measured on every 100K instructions executed 11/24/2018 UAH, ECE

7 Proposed Solution Why use NetBench? 11/24/2018 UAH, ECE

8 Experimental Setup ARM version of the SimpleScalar toolset
Sim-cache Sim-cheetah NetBench Applications include: Micro-Level Programs CRC – Checksum calculation TL – Table lookup IP-Level Programs Route – IPv4 routing DRR – Deficit round robin Application-Level Programs DH – Public key encryption/decryption MD5 – Message digest algorithm (secure signature) 11/24/2018 UAH, ECE

9 Experimental Setup Cache memory setup Cache parameters
Split first level instruction and data Unified first level cache Cache parameters Cache size  ranging from 0.5KB to 32KB Cache associativity  direct mapped, 2-way, 4-way, and 8-way set associative Cache replacement policies  FIFO, Random, LRU, pLRUt, pLRUm, and Optimal Cache block size  32B, 64B 11/24/2018 UAH, ECE

10 Experimental Setup (cont’d)
Instructions ARM Core L1I $ Data L1D $ ARM Core L1U $ Instructions & Data 11/24/2018 UAH, ECE

11 MiBench Experimental Results

12 Data Cache Misses 11/24/2018 UAH, ECE

13 Instruction Cache Misses
11/24/2018 UAH, ECE

14 Unified Cache Misses 11/24/2018 UAH, ECE

15 Dynamic Behavior 11/24/2018 UAH, ECE

16 Dynamic Behavior 11/24/2018 UAH, ECE

17 Replacement Policies 11/24/2018 UAH, ECE

18 Experimental Results NetBench Discussion 11/24/2018 UAH, ECE

19 Conclusions Split caches outperform the equivalent unified cache for relatively small direct mapped caches Unified cache almost always outperforms the split caches for set-associative caches 11/24/2018 UAH, ECE

20 Conclusions Increasing cache associativity reduces the number of cache misses (up to 8-way associative caches) more beneficial for data and unified caches than for instruction caches Pseudo-LRU techniques perform as well as LRU for data caches Random performs the best for instruction caches Relatively significant difference between optimal replacement policy and the best non-optimal policy 11/24/2018 UAH, ECE

Download ppt "Another Performance Evaluation of Memory Hierarchy in Embedded Systems"

Similar presentations

Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suite Hussein Al-Zoubi.

Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suite Hussein Al-Zoubi.
361 Computer Architecture Lecture 15: Cache Memory

361 Computer Architecture Lecture 15: Cache Memory
ITEC 352 Lecture 25 Memory(2). Review RAM –Why it isnt on the CPU –What it is made of –Building blocks to black boxes –How it is accessed –Problems with.

ITEC 352 Lecture 25 Memory(2). Review RAM –Why it isnt on the CPU –What it is made of –Building blocks to black boxes –How it is accessed –Problems with.
Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures Pree Thiengburanathum Advanced computer architecture Oct 24, 2007 1.

Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures Pree Thiengburanathum Advanced computer architecture Oct 24,
Using Instruction Block Signatures to Counter Code Injection Attacks Milena Milenković, Aleksandar Milenković, Emil Jovanov The University of Alabama in.

Using Instruction Block Signatures to Counter Code Injection Attacks Milena Milenković, Aleksandar Milenković, Emil Jovanov The University of Alabama in.
1 Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers By Sreemukha Kandlakunta Phani Shashank.

1 Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers By Sreemukha Kandlakunta Phani Shashank.
Lecture 8: Memory Hierarchy Cache Performance Kai Bu

Lecture 8: Memory Hierarchy Cache Performance Kai Bu
On-Chip Cache Analysis A Parameterized Cache Implementation for a System-on-Chip RISC CPU.

On-Chip Cache Analysis A Parameterized Cache Implementation for a System-on-Chip RISC CPU.
1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 2 (and Appendix B) Memory Hierarchy Design Computer Architecture A Quantitative Approach,

1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 2 (and Appendix B) Memory Hierarchy Design Computer Architecture A Quantitative Approach,
Beneficial Caching in Mobile Ad Hoc Networks Bin Tang, Samir Das, Himanshu Gupta Computer Science Department Stony Brook University.

Beneficial Caching in Mobile Ad Hoc Networks Bin Tang, Samir Das, Himanshu Gupta Computer Science Department Stony Brook University.
Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures Aviral Shrivastava, Ilya Issenin, Nikil Dutt Center For Embedded.

Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures Aviral Shrivastava, Ilya Issenin, Nikil Dutt Center For Embedded.
A Novel Cache Architecture with Enhanced Performance and Security Zhenghong Wang and Ruby B. Lee.

A Novel Cache Architecture with Enhanced Performance and Security Zhenghong Wang and Ruby B. Lee.
Memory Hierarchy and Cache Memory Jennifer Tsay CS 147 Section 3 October 8, 2009.

Memory Hierarchy and Cache Memory Jennifer Tsay CS 147 Section 3 October 8, 2009.
Computer Architecture Memory organization. Types of Memory Cache Memory Serves as a buffer for frequently accessed data Small  High Cost RAM (Main Memory)

Computer Architecture Memory organization. Types of Memory Cache Memory Serves as a buffer for frequently accessed data Small  High Cost RAM (Main Memory)
Computer Architecture Lecture 26 Fasih ur Rehman.

Computer Architecture Lecture 26 Fasih ur Rehman.
Abdullah Aldahami (11074595) March 23, 2010 1. 1. Introduction 2. Background 3. Simulation Techniques a.Experimental Settings b.Model Description c.Methodology.

Abdullah Aldahami ( ) March 23, Introduction 2. Background 3. Simulation Techniques a.Experimental Settings b.Model Description c.Methodology.
CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.

CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.
Efficient Cache Structures of IP Routers to Provide Policy-Based Services Graduate School of Engineering Osaka City University

Efficient Cache Structures of IP Routers to Provide Policy-Based Services Graduate School of Engineering Osaka City University
Lecture 08: Memory Hierarchy Cache Performance Kai Bu

Lecture 08: Memory Hierarchy Cache Performance Kai Bu
Introduction: Memory Management 2 Ideally programmers want memory that is large fast non volatile Memory hierarchy small amount of fast, expensive memory.

Introduction: Memory Management 2 Ideally programmers want memory that is large fast non volatile Memory hierarchy small amount of fast, expensive memory.

Similar presentations

Ads by Google