1. Introduction of Platform LAB-8902

2. 5.2 Multi-Serial Ports Optical Isolated Board Based on LPC
Catalog
Platform Layout
1.1.External Appearance
1.2.Internal Layout
Board Specification
2.1.Specification
Interfaces
3.1.Interfaces in form of socket
3.2.Interfaces in form of pins
3.3.JTAG(XDP)
Timing
4.1.Power sequence
4.2.Signal sequence
Application Examples
5.1.LED light based on GPIO
5.2 Multi-Serial Ports Optical Isolated Board Based on LPC

3. 1.Platform Layout 1.1. External Appearance A B PWR LED HDD LED Power
Reset A B

4. 1.Platform Layout 1.2. Internal Layout Display Power Supply
MotherBoard
Material Box

5. 2.Board Specification and Quality Guarantee
CPU：
—— Atom D510 processor
—— 667MHz front side bus(FSB) support
Chipset：
—— CPU+ICH8M
—— Intel Atom D510 with Intel ICH8M
Super I/O：
—— Winbond W83627DHG
System memory：
—— DIMM socket max support 2G
LVDS:
——Support 18Bits LVDS
VGA:
—— DB15接口
LAN：
—— 1 Gagibit LAN with RTL8111D

6. 2.Board Specification and Quality Guarantee
USB： (8USB)
—— 2 in form of socket
—— 6 in form of pins
AUDIO：
—— Contain Mic In、Line In、Line Out functions with chip ALC888
COM1、2：
—— COM1 supports RS232
—— COM2 supports RS232/422/485, in form of pins
LPT：
—— LPT with standard DB25 interface
PS/2:
—— Standard PS/2 socket
SATA：
—— 2 SATA interfaces，1 in form of 7pin＋15pin(data and power)，1 in form of 7pins with a white socket
CF:
—— Standard CF card socket

7. 2.Board Specification and Quality Guarantee
PC104：
—— Standard PC104 interface based on ISA bus through chip IT8888
PCI：
——Standard PCI interface
PCI-E：
—— 1 4x standard socket
—— 1 1x MINI-PCIE
LPC（IIC bus included）：
——In form of pins
JTAG（XDP）：
—— Standard JTAG socket
GPIO: (From ICH8M)
—— 8 bits GPIO，4IN、4OUT with buffer
BIOS：
—— 8M BIOS

8. 2.Board Specification and Quality Guarantee
BLOCK

9. Note:The square pad or white arrow means the first pin
3.Interfaces
Note:The square pad or white arrow means the first pin

10. 3.Interfaces

11. 3.Interfaces 3.1.Interfaces in form of socket Power Supply VGA +12V_IN
VGA(DB15)

12. 3.Interfaces
COM1
COM1(DB9)

13. 3.Interfaces
LPT
LPT(DB25)

14. 3.Interfaces
PS2
Mouse
Keyboard
Line in
Line out
Audio
Mic

15. 3.Interfaces
USB1/2 & LAN
LAN
USB1/2

16. DDRII Memory(Max support 2G) LVDS(18bits single channel)
3.Interfaces
DDRII Memory(Max support 2G) J8 J9
LVDS
Memory
LVDS Power
LVDS(18bits single channel)
LVDS BKLTPower

17. -12V、-5V are not supported
3.Interfaces
SATA1
SATA2
SATA1
Pwr-out(J7)
PC104
SATA2 & Pwr-out(J7)
PC104(ISA)
-12V、-5V are not supported

18. 3.Interfaces CF(Compact Flash) Default Master PCI (33MHz,32bit)
CF Slot
PCI (33MHz,32bit)
-12V is not supported
PCI

19. 3.Interfaces
PCIE 4x
PCIE

20. MINIPCIE 1X （Support WIFI card、USB device and SSD）
3.Interfaces
MINIPCIE 1X （Support WIFI card、USB device and SSD）
pole1
pole2
MINIPCIE

21. COM2(Support RS232/RS422/RS485)
3.Interfaces
3.2.Interfaces in form of pins
USB3/4/5/6/7/8
USB7/8
USB5/6
USB3/4
COM2 J1 J2 J3
COM2(Support RS232/RS422/RS485)

22. LPC(Low Pin Count,Needs the help of BIOS Engineer)
3.Interfaces
GPIO(JGP)
LPC
GPIO(JGP)
PWR-BTN
LPC(Low Pin Count,Needs the help of BIOS Engineer)
PWR-BTN

23. 3.Interfaces
3.3.JTAG(XDP)
JTAG(XDP)

24. 3.Interfaces Feature of JTAG Emulator i. Based on GUI
ii. Control the registers of chipset
iii. Trace the operation status of the system
iv. If power exists, we can do the debugging
Emulator

25. StandBy Power: Power before we push the button
4.Timing
4.1. Power Sequence
StandBy Power: Power before we push the button
+12V_IN
5VSB
3.3VSB
+12V_IN
5VSB
3.3VSB
Ctrl sig.A
＋12V
Ctrl
Ctrl
VCC
VCC3
Part 1
Part 2

26. 4.Timing Part 3 +12V_IN ＋12V VCC_DDR +12V_IN VCC Ctrl sig.C Ctrl sig.D
Ctrl sig.B
VCC_1P5
VCC_1P05
VCC_GFX
VCC_DDR
3.3VSB
+12V_IN
VCC
VCC3
＋12V
VCC3
VCC_DDR_VTT
Ctrl sig.E
Ctrl sig.E
VCC_1P8
Vcore
Part 3

27. 4.Timing
a. When the adapter is plugged, the +12V_IN、5VSB、3.3VSB will be generated.
b. When the power button is pushed,+12V、5V、3.3V will be generated.
c. When the Ctrl sig.B(SLP_S4#) is received, VCC_DDR、VCC_DDR_VTT will be generated.
d. When the Ctrl sig.C(SLP_S3#) is received, VCC_1P5 will be generated.
e. When the Ctrl sig.D(VCC1P5_PG) is received, VCC_1P05、VCC_GFX will be generated.
f. When the Ctrl sig.E(VCC1P05_PG) is received, VCC_1P8、Vcore will be generated.

28. 4.Timing 4.2.Signal sequence ICH8M W83627DHG-P XDP CK505 CPU 2ms Dly
PLT_RST
XDP
CK505
ICH8M
CPU
SYS_RST
CPU_PWRGD
PCI_RST
2ms Dly
PLT_RST
CPU_PG
CPU_PG
VRM_PWRGD
PLT_RST
PWROK
RSM_RST
CF_RST
PWR_BTN
SLP_S3
VCORE
100ms Dly
LPC_RST
CPU_PG
3.3VSB
PCIE_RST
VCC_1P05PG
CPU
PSOUT
W83627DHG-P
SLP_S3
+12V、＋5V、＋3.3V、VCC_DDR
VCC_DDR_VTT、VCC_1P8、
VCC_1P5、VCC_GFX、VCC_1P05
RSM_RST
PSON
PLT_RST
PSIN
PWR_BTN

29. 4.Timing
a. RSM_RST de-asserted (High) after the 3.3VSB stables for at least 30ms.
b. PWR_BTN is pressed (Low), signal sent to SuperIO.
c. SuperIO sent a signal to ICH8 PWR_BTN to wake the system.
d. SLP_S3 de-asserted (High) by ICH8 and sent to SuperIO.
e. PSON asserted (Low) from SuperIO to turn on power supply.
f. PWRGD signals (VCC_1P5、VCC_GFX、VCC_1P05) asserted (High) by each Voltage Regulator. The Vcore is generated when VCC_1P05PG asserted.
g. VRM_PWRGD asserted (High) by CPU_PG signal.
h. Enable CK505 after 2ms delay from CPU_PG.
i. PWROK asserted (High) by CPU_PG signal after 100ms delay.
j. CPU_PWRGD asserted (High).
k. PLT_RST de-asserted (High).

30. 4.Timing

31. 5.Application Examples 5.1.LED Light Based On GPIO Purpose:
I. Learn the feature of GPIO programming based on X86 structure
II. Master the technique of GPIO programming
Feature
AS:
There are many chips which contain gpio interface in one system
There are many registers need to configure
Different gpio chip has its own programming method
SO:
Make sure which gpio chip you are based on
Make sure which registers need to configure
Make sure you have the datasheet of the chip

32. 5.Application Examples Device GPIO Input: gp1、gp6、gp7、gp17
Output: gp20、gp24、gp27、gp28
Output: 5V
Input: 5V
Provided by ICH8
LED
Max Voltage: 5V
Max Current: 15mA

33. 5.Application Examples
Registers

34. 5.Application Examples
GPIO_USE_SEL[31:0]－R/W. Each bit in this register enables the corresponding GPIO (if exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
GP_IO_SEL[31:0]－R/W. When configured in native mode (GPIO_USE_SEL[n] is 0),writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
GP_LVL[31:0]－R/W:
If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. 1=high,0=low.
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1=high,0=low）and writes will have no effect. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode.

35. unsigned int GPIOBase = 0x500;
5.Application Examples
Key function analysis
unsigned int GPIOBase = 0x500;
Memory Map
Variable Map
GPIO(Anywhere in 64 KB)
Registers Map
I/O Map
Fixed Map
PCI Config Map
#define GPIO_USE_SEL (GPIOBase + 0x0)
#define GP_IO_SEL (GPIOBase + 0x4)
#define GP_LVL (GPIOBase + 0xC)
int GPIOInit_5872(unsigned char DirPinGPIO);
int GPIORead_5872( unsigned char PinNum );
int GPIOWrite_5872(unsigned char PinNum, unsigned char Data);

36. Initiate the GPIO register
5.Application Examples
Initiate the GPIO register

37. 5.Application Examples
GPIO Read Function

38. 5.Application Examples
GPIO Write Function

39. 5.Application Examples
GUI

40. 5.Application Examples
5.2 Multi-Serial Ports Optical Isolated Board Based on LPC
Purpose:
Learn the concept of LPC
Learn the concept of Optical isolate
Learn how to extend the LPC interface
Device and Part :
LPC interface of EMB-5872
F81216DG
PC410L
SP213ECA
F0505S-1W(DC/DC)

41. 5.Application Examples LPC Definition Signal Definition based on ICH8M
LPC=Low Pin Count
Based on intel LPC protocol
33MHz, 4bits Data/Address bus
Signal Definition based on ICH8M
LPC_AD[3:0]: Multiplexed Address/Data
LPC_FRAME#: Indicate the start of an LPC cycle
LPC_SERIRQ: Conveys the serial interrupt protocol
LPC_CLKOUT[2:0]: Clock driven by the SCH
LPC_CLKRUN#: Enable the LPC_CLKRUN# to operate

42. 5.Application Examples Board && Block Diagram
AFC-391C16 Multi-Serial Ports Optical Isolated board
LPC to 4 UART
LPC Interface
COM18
COM17
DC/DC
photocoupler
COM15
COM16
RS232 Transceiver
COM3
COM4

43. 5.Application Examples
Design Structure

44. 5.Application Examples Choose the right LPC to UART Chip F81216DG:
Supports LPC interface
Provides 4 UART ports
Frequency input 24/48MHz
Powered by 3Vcc

45. 5.Application Examples
Typical Sample

46. 5.Application Examples

47. 5.Application Examples

48. 5.Application Examples Optical photocoupler circuit
PC410L:10Mb/s、isolation voltage is 3.75KV
F0505S-1W

49. 5.Application Examples SP213ECA (Transfer Voltage±10V)
+5V High Performance RS232 Transceivers
230kbps Transmission rates
Tri-State Receiver Outputs
Meets All EIA-232 Specifications
RS232(1: -3V----15V 0: 3V---15V)
Phase1
Phase2
Phase3
Phase4

50. Note: This example needs the support of BIOS engineer
5.Application Examples
GUI
Note: This example needs the support of BIOS engineer

51. More resources of support

52. Thank you for your attention!