1. 3D interconnection in the DevDET FP7 proposal
3D Integration workshop
Ringberg Castle
April 6-9, 2009

2. 3D Integration workshop
Scope of Proposal
3D Integration workshop
Ringberg Castle
April 6-9, 2009

3. 3D Integration workshop
Scope of the Proposal
3D Integration workshop
Ringberg Castle
April 6-9, 2009

4. 3D Integration workshop
Workpackages
3D Integration workshop
Ringberg Castle
April 6-9, 2009

5. 3D Integration workshop
WP3 objectives
3D Integration workshop
Ringberg Castle
April 6-9, 2009

6. 3D Integration workshop
Task Description
3D Integration workshop
Ringberg Castle
April 6-9, 2009

7. 3D Integration workshop
Budget
Total Budget: 1.25 MEuro
EU contribution: 450 kEuro
(request!)
Probably not sufficient for the ambitious program
Partners have to increase their contribution
However: It’s a coordination project
Main emphasis on creation of common activities:
- shared design of test ASIC
- common MPW
- common processing of test/prototype interconnection
3D Integration workshop
Ringberg Castle
April 6-9, 2009

8. 3D Integration workshop
Timeline
Proposal filed: 29. February 2008
Expect Decision: Early July 2008
Negotiation Phase,
Consortium Agreement
Official Start: January 2009
However: get started now:
N. Hessey:
Recfa will back a start on the common project aspects of DevDet,
until DevDet starts
-> get organized
3D Integration workshop
Ringberg Castle
April 6-9, 2009

9. 3D Integration workshop
Scope of the workshop
One of the goals of this workshop is the formation of a common platform for the R&D on vertically integrated pixel detector systems which then would give the opportunity to share the experience and open new possibilities for the organization
of common projects
How to form a common platform?
ASIC/sensor design
ASIC/sensor production
3D interconnection processing
IZM
IMEC
MIT
Tazzaron
………
Ideal: MPW projects
3D Integration workshop
Ringberg Castle
April 6-9, 2009

10. 3D Integration workshop
MPW with wafer access
Main obstacle: many process steps need complete wafers
postprocessing of ASICs
barrier layers, metal layers
even chip-to-wafer needs such processing
single chips form MPW cannot be used!
Proposal:
Organize common MPW runs of 3D-community with agreed access to
Complete wafers
Possible if organized by CERN (has happened before)
Costs of an extra wafer: ~3000 $
Costs of an MPW: ~300 k$ (130nm, IBM)
Need some kind of NDA (don’t use chips on the wafer not belonging to you)
This is possible if the entire wafer is for the community
What is needed:
Sufficient participants to fill a wafer (however, not all needs to be for 3D!)
Agree on a common technology
3D Integration workshop
Ringberg Castle
April 6-9, 2009