1. SmartOpt An Industrial Strength Framework for Logic Synthesis
Stephen Jang, Xilinx Inc.
Dennis Wu, Xilinx Inc.
Mark Jarvin, Xilinx Inc.
Billy Chan, Xilinx Inc.
Kevin Chung, Xilinx Inc.
Alan Mishchenko, UC Berkeley
Robert Brayton, UC Berkeley

2. Example Industrial Circuit
Toy synthesized netlist created for Xilinx FPGA with Xilinx MUXFx
Xilinx Confidential

3. Example Industrial Circuit
MUXFx is dedicated hardware that multiplexes the outputs of two adjacent LUTs
Xilinx Confidential

4. Example Industrial Circuit
MUXFx is dedicated hardware that multiplexes the outputs of two adjacent LUTs
Xilinx Confidential

5. Modeling the Example
Xilinx Confidential

6. Modeling the Example
Xilinx Confidential

7. Modeling the Example .model MUXFx .inputs I0 I1 S .outputs O
.attrib comb black box
.end
Xilinx Confidential

8. Modeling the Example
.model MUXFx
.inputs I0 I1 S
.outputs O
.attrib comb black box
.end
No information flow between inputs and outputs of MUXFx
Xilinx Confidential

9. Modeling the Example
.model MUXFx
.inputs I0 I1 S
.outputs O
.attrib comb black box
.end
No information flow between inputs and outputs of MUXFx
Box I/Os equivalent to PIs/POs
Xilinx Confidential

10. Modeling the Example
Xilinx Confidential

11. Modeling the Example Pin delays added to model .model MUXFx
.inputs I0 I1 S
.outputs O
.attrib comb black box
.delay I0 O 0.5
.delay I1 O 0.5
.delay S O 0.1
.end
Pin delays added to model
Xilinx Confidential

12. Modeling the Example Pin delays added to model Better timing analysis
.model MUXFx
.inputs I0 I1 S
.outputs O
.attrib comb black box
.delay I0 O 0.5
.delay I1 O 0.5
.delay S O 0.1
.end
Pin delays added to model
Better timing analysis
Still can’t exploit constant
Xilinx Confidential

13. Modeling the Example
Xilinx Confidential

14. Modeling the Example Model MUXFx functionality .model MUXFx
.inputs I0 I1 S
.outputs O
.attrib comb white box
.delay I0 O 0.5
.delay I1 O 0.5
.delay S O 0.1
.names IO I1 S O
1-0 1
-11 1
.end
Model MUXFx functionality
Xilinx Confidential

15. Modeling the Example Model MUXFx functionality Trim unused logic
.inputs I0 I1 S
.outputs O
.attrib comb white box
.delay I0 O 0.5
.delay I1 O 0.5
.delay S O 0.1
.names IO I1 S O
1-0 1
-11 1
.end
Model MUXFx functionality
Trim unused logic
IP designer’s intent preserved by white box
Xilinx Confidential

16. Results with different models
Quality of results obtained by ABC scale with information carried in the integeration model
Compared to the reference flow without ABC, using ABC on the fractured netlist, results in 2.5% LUT count reduction and 0.7% design performance improvement. This improvement is due to ABC’s combinational optimization and mapping.
Allowing timing information to flow for the entire netlist, ABC’s combinational synthesis is able to improve Fmax an additional 1% and to further reduce LUTs by 0.6% by applying area recovery to the non-critical paths.
Allowing timing and functional information to flow for the entire netlist, ABC is able to greatly reduce the # of LUTs and FFs through it sequential optimizations.
Xilinx Confidential

17. Conclusion
Introduced BLIF extensions to allowing timing and logical information for the entire circuit to be visible to ABC
Industrial design quality of results scale with modeling detail presented to ABC
Black Box models: reduce LUTs by 2.5% and improve speed by 0.7% vs. non-ABC flow
Box with timing info: reduce LUTs by 3.1% and improve speed by 1.7%
SmartOpt (boxes with timing and function information): reduce LUTs by 8.3% and FFs by 7.8% plus improve speed by 2.1%
Xilinx Confidential