1. Survey of Crypto CoProcessor Design
Shah Zafrani
CS 6021 – Fall ’17

2. Cryptography Basics
There are two main types of commonly Cryptographic Algorithms :
Symmetric Key
AES is the most commonly used form of this because of it’s speed
Better for encrypting messages
Asymmetric Key
RSA is used because of it’s ability to securely exchange keys
Used for key exchange primarily
Not ideal for message encryption because it’s computationally heavy
We’re going to be focusing on Symmetric Key

3. Hash Algorithms are crucial too!
Hashing algorithms are used to authenticate data.
MD5 Checksums, SHA-1, and SHA-256 are just a few.
Some Crypto CoProcessors also speed up these algorithms

4. FPGA vs ASIC ASIC (Application Specific Integrated Chip)
More Power Efficient
Takes longer to design
Relatively difficult to modify
FPGA (Field Programmable Gate Array)
Short design cycle enables quick time-to-market
Low cost
Easy to update and modify

5. FPGA based CoProcessor
This is an implementation that is coupled with a MIPS Processor but can be extended to others
All instructions fetched by the main processor that are not designed for it are sent to the FPGA.
CoProcessor is Parameterized so that only as many rounds as needed are processed
Designed specifically for AES

6. AES implementation
Completes rounds
iteratively

7. Pipelined AES Implementation
Takes advantage of parallelization to allow multiple rounds to run concurrently

8. MIPS Datapath

9. MIPS with AES CoProcessor

10. AFPC Implementation Application Flexible coProcessor for Crypto
CMOS 0.18um fabrication
Uses VLIW (Very Long Instruction Word) 160 bits wide
32 bits for op code, and 128/4 bits for up to four functional units
Allows for AES, DES, MD5, SHA, and others
Application Flexible coProcessor for Crypto information

11. Overview of AFPC

12. Functional Unit Details

13. SRCP Implementation ASIC CMOS produced solution
Resistant to Side Channel Attacks
Simple Power Analysis
Differential Power Analysis
Electromagnetic Analysis
Supports AES, DES, IDEA, RC6
Reconfigurable using PE Arrays
Secure Reconfigurable Crypto CoProcessor
Complementary metal–oxide–semiconductor
PE: Processing Element

14. SRCP Overview

15. Scan Channel Analysis Visualized

16. References (APA Style)
Parameterized AES-Based Crypto Processor for FPGAs. (2014) th Euromicro Conference on Digital System Design, Digital System Design (DSD), th Euromicro Conference on, Digital System Design (DSD), 2013 Euromicro Conference on, 465. doi: /DSD Yang, X., Yu, X., Dai, Z., & Zhang, Y. (2008). Accelerated flexible co-processor architecture for crypto information. *2008 4Th IEEE International Conference On Circuits And Systems For Communications, ICCSC*, (2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC), doi: /ICCSC Shan, W., Fu, X., & Xu, Z. (2015). A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA. IEEE Transactions On Computer-Aided Design Of Integrated Circuits & Systems, 34(7),