1. Clock Domain Crossing
Keon Amini

2. What is Clock Domain Crossing (CDC)?
If we have two sequential circuits, each running with different clocks, and signals are being transmitted from one to the other, the signals are said to be crossing clock domains.
Examples of CDC usage include buttons, switches, UART receivers, incoming SPI clocks, asynchronous resets, USB-FPGA interfacing, etc.

3. Some CDC Techniques Crossing into Higher Frequency Domain
Multi-Flip Flop Synchronizers
Crossing into Similar or Lower Frequency Domain
Asynchronous FIFOs

4. Multi-Flip Flop Synchronizers
Cascading Flip Flops introduces a delay in the output which reduces the chances of any propagated metastability
Signal A must not transition any faster than the time required for signal C to stabilize, otherwise there will be data loss
MTBF > 1/(fA*fC2)
To discard the excess samples in C, additional follow-up logic is required.

5. Asynchronous FIFOs
Since the receiver is slower, the data must be written into a memory
Domain A writes data into the FIFO using clock A (fast), Domain B reads data from the FIFO using clock B (slow)
Once the FIFO is full, Domain A must stop writing, and Domain B will continue reading until FIFO is empty
Uses n+1 bit registers: n for data, 1 for full/not full flag

6. Asynchronous FIFOs
Read and write pointers must cross domains in order to be checked for fullness, as a result 2-FF synchronizers are used
Must use a clever numbering scheme for address pointers so that there are minimum bit transitions -> maximum reliability of the 2FF synchronizers
Best Scheme: Gray Code

7. Other Considerations Data Incoherency
Multiple Bits crossing over domains – some may have longer metastable durations -> incoherent output
Solution: MUX Recirculation Synchronizers
More CDC use-cases to be considered in the near future

8. References
design.com/papers/CummingsSNUG2008Boston_CDC.pdf