1. 3D IC EMC

2. Contents 3D-IC Benefits 3D-IC Technology 3D-IC EMC Challenges
3D-IC Signal Integrity
3D-IC PDN & Power Integrity
3D-IC Measurement methods
3D-IC EMC guidelines
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3. References http://www.itrs2.net/itrs-reports.html
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4. 3D-IC BENEFITS
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5. 3D-IC Benefits
“Evolutionary and revolutionary interconnect technologies are needed to enable migration to 3D”
ITRS - The next Step in Assembly and Packaging
3DIC & 2.5D TSV Interconnect for Advanced Packaging
2014 Business Update Report, Yole Developpement
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6. 3D-IC Benefits Georgia-Tech vision of SoC
From Georgia Tech 3D system packaging research
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7. 3D-IC Benefits
3D-Ics used to improve the processor/memory link efficiency
High-Bandwidth Memory (HBM)
High Bandwidth Memory (HBM)
Target
Servers
Smartphones
HD real-time cameras
Automatic drive
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8. 3D-IC Benefits High Performance Computing
Tesla platform for Artificial Intelligence (AI) and deep learning systems.
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9. 3D-IC Benefits High Bandwidth Memory (HBM): stacked dies DDR3 HBM
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10. From ITRS 2011 Executive Summary, and Yole Dev.
3D-IC Benefits
3D Packaging contributes to “More than Moore” at a reasonable price
2008 : “Why 3D?”
2010 “”How 3D?
2012 : “When 3D?” …
20xx : “Why 2D?”
From ITRS 2011 Executive Summary, and Yole Dev.
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11. 3D-IC Benefits
3D technology enables the integration of ICs fabricated in different technologies
CMOS, CCD, SOI, Sensor
4µm vias
Bosch process
B. Aull, et. al., “Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes” IEEE SSCC 2006.
C. Bower, et. al., “High Density Vertical Interconnects for 3D Integration of Silicon ICs,” 56th ECTC, San Diego, 2006.
0.18μm SOI
0.35 μm SOI
Sensor
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12. 3D-IC Benefits Increase of pixel area in imagers
3DIC & 2.5D TSV Interconnect for Advanced Packaging
2014 Business Update Report, Yole Developpement
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13. 3D-IC Benefits Improve electronic efficiency
3D minimizes interconnect parasitic effects
3D simplifies multiple supply voltage distribution
3D reduces package pin count
More uniform, high density power delivery
J. Lu, “Monolithic 3D Power Delivery Using Dc-Dc Converter”, 3D Architecture Conference, October, 2006, Burlingame, CA.
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14. Voltage translation and level shifers
3D-IC Benefits
A significant reduction in I/O complexity
Solder ball
ESD protection
Voltage translation and level shifers
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15. 3D-IC Benefits A better power efficiency
Smaller wire-length distribution
Shorter wires decrease the average load capacitance and resistance and decrease the number of repeaters needed for long wires.
The reduced average interconnect length in 3D IC, vs 2D IC, improves the wire efficiency by %
Active power may be reduced by 25-50%
"Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in 3D-Ics « , Lili Zhou, ICCD 2007
T. Topol « Three-dimensional integrated circuits », Ibm Journal Research, 2006
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16. 3D-IC Benefits PCB PCB 2.5D ICS - Package on package Upper MEM
Connection SoC- Memory through PCB
2 separate Ics on each side of the PCB
Stacked packages
Connection SoC- Memory through molded vias
2D configuration
3D configuration
Upper MEM
MEM to SoC (TMV)
PCB
PCB
MEM to PCB (TMV)
Bottom SoC
New Gen SoC

17. 3D-IC Benefits 2.5D ICS - Package on package
Lower die: NG SoC
Upper die: 512 Mb SDRAM
E. Sicard "EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package", EMC Compo 2015, Nov , 2015, Edinburgh

18. 3D-IC Benefits
2.5D ICs
The yield of a single 7-Billion CMOS die is too low
4 dies (1.7 B-device each) connected by transposer
The 4-die Virtex-7 reaches 7 Billion devices
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19. 3D-IC TECHNOLOGY
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20. 3D-IC Technology Higher complexity at lower cost Stacking of memories
12 chips, 840 µm thickness
8 chips, 560 µm thickness
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21. 3D-IC Technology Through silicon via technologies
3DIC & 2.5D TSV Interconnect for Advanced Packaging, 2014 Business Update Report, Yole Developpement
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22. 3D-IC Technology Direct bond interconnect (DBI) using magic metal
R around 50 mΩ
Review of 3D Related Technologies for HEP R. Yarema, 2007
Ziptronix, 3D Conference, Oct, 2007
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23. 3D-IC Technology Wire-Bond vs. Through-Silicon-Via (TSV)
LOH, « 3D Stacked Microprocessor: Are We There Yet? », IEEE Micro, 2010
A. Chambers, “Through-Wafer Via Etching”, Advanced Packaging, April 2005
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24. Process offered by CMC, CMP and MOSIS
3D-IC Technology
Process offered by CMC, CMP and MOSIS
Terrazon with 2 flip chips
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25. MIT Lincoln Labs 3D case study
3D-IC Technology
MIT Lincoln Labs 3D case study
R. Yarema, “Development of 3D Integrated Circuits for HEP”, 12th LHC Electronics Workshop, Valencia, Spain, September 25-29, 2006
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26. 3D-IC Technology http://www.eejournal.com/article/20170102-hbm-hmc/
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27. 3D-IC EMC CHALLENGES
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28. EMI of System-on-Package Sudo, IEEE Trans EMC 2004
3D-IC EMC Challenges
EMI, SI, PI…
EMI of System-on-Package Sudo, IEEE Trans EMC 2004
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29. 3D-IC EMC Challenges
J. Kim; IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC
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30. 3D-EMC Challenges No mature standard applicable to 3D-Ics
Various processes, TSV sizes…
SEMI Inspection and Metrology Task Force
“cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed”
Identify and create new standards in 3D-ICs.
TSV depth
BWP thickness
Microbump co-planarity
Defect, and Overlay
… but no EMC
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31. From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev.
3D-IC EMC Challenges
No I/O standardization between interfaces
3D integration of memory + logic ICs together is perceived as the big wave for 3D volume adoption
3D stack of CPU, GPU, DSP, FPGA, ASICs and Basebands ICs
Ued in future cell phones, super-computers, network / storage systems, notebooks, automotive and medical processing units …
IBIS could play an important role for standard interfacing
From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev.
From ITRS Roadmap
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32. 3D-IC EMC Challenges Effects of heterogenous temperature
Core + MEM stack
Investigation of temperature variation amoung dies
Upto 35° variation
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
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33. HTOL : High temperature operating lifetime (eq. 10 years):
3D-IC EMC Challenges
High Temperature accelerates ageing and reduces immunity
HTOL : High temperature operating lifetime (eq. 10 years):
150⁰C
+10% Vdd
408 hours
B. Li, “Ageing effect on electromagnetic susceptibility of a phase locked loop”, Microelectronic Reliability, Vol. 50, Issues 9-11, pp September 2010.
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34. 3D-IC SIGNAL INTEGRITY
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35. EMC-3D Consortium Overview and CoO Model, Paul Siblerud, www.emc3d.org
3D-IC Signal Integrity
3D stacking vs TSV
EMC-3D Consortium Overview and CoO Model, Paul Siblerud,
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36. 3D-IC Signal Integrity PoP signal integrity simulation
IBIS available for both chips
DDR buffer
DQ0
R,L,C
NG - SoC
Memory (7)
SoC silicon Die L
Micro ball from die to BGA (2)
BGA track (3)
Through Mold Via to Mem (4)
Memory package track (5)
Package bonding (6)
Radiating inductances 1 2 3 4 5 6 7
500mV overshoot
2.5ns symbol
450mV undershoot

37. 3D-IC Signal Integrity TSV Model
Resistance and Capacitance values in mΩ and fF
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
Above 1 GHz: skin effect, dielectric losses
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38. 3D-IC Signal Integrity TSV Model
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
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39. 3D-IC Signal Integrity Inter-die model F2F F2B
J. Roulard, Electrical Characterization and Impact on Signal Integrity of New Basic Interconnection Elements inside 3D Integrated Circuits, 2011 Electronic Components and Technology Conference
F2F
F2B
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40. 3D-IC PDN & POWER INTEGRITY
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41. 3D-IC PDN & Power Integrity
Passive Distribution Network
Effect of on-die capacitors
EMI of System-on-Package Sudo, IEEE Trans EMC 2004
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42. 3D-IC PDN & Power Integrity
Maximum power noise (mV) with varied settings
Power TSV
Young-Joon Lee, Co-design of Reliable Signal and Power Interconnects in 3D Stacked Ics, 2009
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43. 3D-IC PDN & Power Integrity
Dynamic noise
Voltage drop as a function of time.
The dynamic noise as a function of TSV dimension in μm (40 x 40 TSV)
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
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44. 3D-IC PDN & Power Integrity
IR-Drop (current-passing-resistance voltage)
Larger TSVs provide lower resistance and inductance values
The IR drop are highly influenced by the pitch of the TSVs
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45. 3D-IC PDN & Power Integrity
Strategies for supply arrays in TSVs
Ideas for supply standardization
J. S. Pak “PDN Impedance Modeling and Analysis of 3D TSV IC », IEEE Transactions on components, packaging, and manuf. Tech. vol. 1, no. 2, Feb. 2011
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46. 3D-IC PDN & Power Integrity
DDR port handling
1. Split in geographical domains
North
East
West
2. Switch all synchronously
3. Apply a duty-cycle
4. Apply a randomizing factor
5. Apply a screening factor
mDDR top level: radiation via bonding wires
Radiate
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47. 3D-IC PDN & Power Integrity
DDR port handling
10ns
10 synchronous ADDR lines
32 synchronous data lines
No activity in the DQ port
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48. 3D-IC MEASUREMENT METHODS
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49. 3D-IC Measurement Methods
IEC – 4 “1/150 Ω method”
Each die would have a built-in 1 Ω probing for IC emission characterization
1 Ω die 1
1 Ω die 2
1 Ω die 3
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50. 3D-IC Measurement Methods
IEC – 4 “DPI method”
Each die would have built-in injection probes for IC immunity characterization
to die 1
to die 2
to die 3
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51. 3D-IC Measurement Methods
IEC – 2 “TEM/GTEM method”, -8 “Mini-strip line”
Mini strip-line efficient for injection (3%)
Canonical field
EMC test board
Strip line cross-section
6.7 mm
F. Klotz, « IC-Stripline, new method for emission and immunity », EMC Compo 2009
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52. 3D-IC GUIDELINES
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53. 3D-IC EMC guidelines Filter design Technique Expected EMI reduction
Reference
Shielding in 3D stacking
Graphene shielding between embedded inductor aggressor and LNA victim
10-17 dB
[Kim2012]
Shielding in 3D ICs
Guard rings and ground TSVs
Patterned Ground Shield
30 dB
5-10 dB
[Lim2015]
[Alimadadi2015]
Active filtering
Active output compensation with reverse phase to reduced output noise
10-20 dB
[Hamza2013]
[Kose2012]
Spread Spectrum
Modulation of the HS/LS power switch
10-15 dB
[Liou2014]
Multi-phase
Multi-phase converter
10 dB (HF)
[Dang2015]
[Abouda2015]
Coupled coils
Design of on-chip inductor to cancel radiated fields
10 dB
[Dang2014]
MIM capacitance
Decoupling at very high frequencies
[Kurd2014]
Damping
Serial resistance close to LC resonant structure
10 dB above 50 MHz
[Park2015]
Choice of components
Selection of diodes
15 dB (HF)
[Li2005]
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54. 3D-IC EMC guidelines Shielding in 3D stacking
K. Kim, “Graphene-based EMI Shielding for Vertical Noise Coupling Reduction in 3D Mixed-Signal System”, 2012
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55. 3D-IC EMC guidelines Shielding in 3D stacking
J. Lim, “Shielding Structures for Through Silicon Via (TSV) to Active Circuit Noise Coupling in 3D IC”, EMC Compo 2015 Edinburgh
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56. 3D-IC EMC guidelines Shielding in 3D stacking
Thin magnetic-nonmagnetic multi-layered structure
Trench-via array and multi-layered conductor structures (5G, GHz)
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57. 3D-IC EMC guidelines Active filtering Spread spectrum
D. Hamza and M. Qiu, "Digital Active EMI Control Technique for Switch Mode Power Converters," 2013
Spread spectrum
W. R. Liou “Monolithic Low-EMI CMOS DC–DC Boost Converter for Portable Applications, “, IEEE Trans. VLSI, Vol. 22, No. 2, February 201
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58. 3D-IC EMC guidelines Multi-phase
K. ABOUDA,, “Analytical Approach to study Electromagnetic Emission EME Contributors on DC/DC applications - Introducing of multiphase Buck converters in automotive analog designs to reduce EME”, EMC Compo 2015, Edinburgh
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59. 3D-IC EMC guidelines
Coupled coils
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60. N. Kurd “Haswell: A Family of IA 22nm Processors” ISSCC 2014
3D-IC EMC guidelines
N. Kurd “Haswell: A Family of IA 22nm Processors” ISSCC 2014
On-chip decoupling
Eunseok Song; "Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs," Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.3, no.9, pp.1467,1480, Sept. 2013
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61. 3D-IC EMC guidelines Damping
S. Park, Analysis of EMI Reduction Methods of DC-DC Buck Converter, EMC Compo 2015
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62. Z. Li, “EMI Specifics of Synchronous DC-DC Buck Converters”, 2005
3D-IC EMC guidelines
Choice of components
K. ABOUDA,, “Analytical Approach to study Electromagnetic Emission EME Contributors on DC/DC applications”, EMC Compo 2015, Edinburgh
Z. Li, “EMI Specifics of Synchronous DC-DC Buck Converters”, 2005
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63. Conclusion
Interconnect delay, power consumption, yield and reliability limit 2D-ICs
3D speed up signal propagation, consumes less power, improves yield, on the path to Tera-Hz computing
Many 3D-IC technologies co-exist, no standard
New EMC Challenges in 3D due to die-die proximity, protection simplification
Signal Integrity closely linked to via technologies
PDN & Power Integrity linked to 3D choices
Standard and new measurement methods available
EMC guidelines applicable to 3D ICs
3D-EMC still in infancy stage, a huge room for innovation
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64. Thank you for your attention
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