1. CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 13
March 2
W’05
Yutao He
4532B Boelter Hall

2. Outline Administrative Matters Basic sequential devices - Recap
Design of sequential systems w/ FFs
Analysis of sequential systems
Timing Analysis
Functional analysis

3. Administrative Matters
Quiz #3
Given on Friday
Closed-book/Closed-note
You’ll be given FF Excitation Tables if they’re used
Project #3
Is posted and due at 2pm March 11 (Friday), 2005
Midterm Solution
Is posted

4. Latch and FF Loop feedback introduces “memory” capability D D Q CLK
positive edge-triggered flip-flop D
CLK
QFF
Qlatch
D Q G
CLK
Level-sensitive gated latch
behavior is the same unless input changes
while the clock is high

5. Edged-Trigged Flip-Flops
Development of D-FF
Level-sensitive used in custom integrated circuits
Edge-triggered used in programmable logic devices
Good choice for data storage register
Historically J-K FF was popular but now never used
Similar to R-S but with 1-1 being used to toggle output
Good in days of TTL/SSI (more complex input function): D = JQ' + K'Q
Not a good choice for PALs/PLAs as it requires 2 inputs
Can always be implemented using D-FF
Asynchronous preset and clear inputs are highly desirable on FFs
Used at start-up or to reset system to a known clean state

6. Excitation Functions of Flip-Flops
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop

7. Write up Switching Expressions
Roadmap of Implementation w/ FFs
Start with
State Table
Select FF Types
Fill in Truth Table
of FF inputs
Simplify with K-Map
Write up Switching Expressions
Draw Networks
(FFs+Gates)

8. Ex Modulo-5 Counter
Use T flip-flops to design a modulo-5 counter

9. Ex. 8.8 - Modulo-5 Counter (Cont’d)
State Assignment
5, 6, and 7 are don’t cares!
State Transition Table

10. Ex. 8.8 - Modulo-5 Counter (Cont’d)Q
CLK x y2 y1 y0
To Be
Designed
Truth Tables for T0,T1,T2

11. Ex. 8.8 - Modulo-5 Counter (Cont’d)
K-Maps
Switching Expressions

12. Ex. 8.8 - Modulo-5 Counter (Cont’d)

13. Example 8.9

14. Example 8.9 (Cont’d)

15. Example 8.9 (Cont’d)

16. Example 8.9 (Cont’d) 00 01 10 11

17. Example 8.9 (Cont’d)

18. State Assignment Revisit
Basic goal:
Encode each “symbolic” state with a binary number
Basic fact:
With n state bits for m states, there are 2n! / (2n – m)!
Basic approaches of state assignment:
One-FF-per-bit
Binary code: just number states as they appear in the state table
Other codes, etc. Gray Code
Random: pick random codes
One-FF-per-state (One-hot)
State encoding with fewer bits has fewer equations
However, each may be more complex
State encoding with more bits has simpler equations

19. One-FF-Per-State(One-Hot) Approach
Each flip-flop implements each state
There is only single 1 in state encoding
State functions are simple
Design directly from the state diagram
Determined
by inputs

20. Example: Modulo-5 CounterQ Q’ S0 S1 S2 S3 S4
CLK

21. Compare M-5 Counter Implementations

22. Analysis of Sequential Systems
Goal:
Decide the timing and functional behavior from the implementation of a sequential system composed of FFs and logic gates
Types:
Timing analysis
Functional analysis

23. Clock Revisit A regular periodic signal Period T Frequency f
Time between two consecutive ticks
Frequency f
f = 1/T
Duty-cycle d
Time clock is high between ticks
Usually expressed as % of period
duty cycle (in this case, 50%)
CLK
period

24. Clock Signal Questions to ask: When inputs are sampled?
Ideal
Reality
Level-sensitive
Edge-triggered
Questions to ask:
When inputs are sampled?
When the next state is computed?
When outputs are asserted? (i.e. the value is 1)

25. Timing Parameters of A Basic Cell
Setup time (tsu): minimum time before the clock triggering edge by which the input must be stable
Hold time (th): minimum time after the clock triggering edge until which the input must remain stable
Propagation delay (tp): time interval between input transition and output transition it causes
CLK
tsu th
CLK D Q
Input D
Don’t care
Don’t care tp
Output Q
Unknown

26. Timing Behavior of Sequential Network
CLK
Output
input
CLK
All storage cells are controlled by the same clock edge
The Com. Logic blocks:
Inputs are updated at each clock tick
All outputs MUST be stable before the next clock tick
Network setup time, hold time, propagation delay
Minimal clock cycle (maximal clock frequency)
is a function of the critical path

27. Clock Skew

28. Dealing with Asyn. Inputs
Clocked synchronous circuits
Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock)
E.g., master/slave, edge-triggered
Asynchronous circuits
Inputs, state, and outputs sampled or changed independently of a common reference signal (hazards a major concern)
E.g., gated latch
Asynchronous inputs to synchronous circuits
Inputs can change at any time, will not meet setup/hold times
Dangerous, synchronous inputs are greatly preferred
Cannot be avoided (e.g., reset signal, memory wait, user input)

29. Dealing with Asyn. Inputs
Never allow asynchronous inputs to fan-out to more than one flip-flop
Synchronize as soon as possible and then treat as synchronous signal D Q Q0
Clock Q1
Async
Input
Clocked
Synchronous
System D Q Q0
Clock Q1
Async
Input
Synchronizer

30. Functional Analysis Major goal: Basic approach: Basic steps:
Obtain specification (high-level or binary level) of a sequential system from its implementation
Basic approach:
Break the loop at inputs of FFs
Use characteristic equations of FFs
Basic steps:
Step 1. Obtain switching expressions of output and next state functions
Step 2. Remove inputs of FFs from the expressions
Step 3. Write transition table or draw state diagram
Step 4. Select suitable encoding scheme and figure out high-level function

31. Characteristic Equation of FFs

32. Example 8.4
State Transition:
Output:

33. State Transition Table
Example 8.4 (Cont’d)
State Transition Table
Encoding Scheme
Input
Output
State

34. High-Level Specification
Example 8.4 (Cont’d)
High-Level Specification

35. Time-behavior Specification
Example 8.4 (Cont’d)
State Diagram
Time-behavior Specification

36. Example 8.7

37. Example 8.7 (Cont’d)
JAKA, JBKB
10,01
01,01
10,10
01,10
00,00
01,00
11,10

38. Example 8.7 (Cont’d)

39. Example 8.7 (Cont’d)

40. About Design
Bad designs
Mediocre designs
Good designs
Creativity

41. Design Requirements
Dependability
Performance
Cost

42. Performance Concern Criteria Goal How well it can perform? Short delay
Low power dissipation
Rich Functionalities
Goal
High-Performance

43. Cost Which part of cost you can control?
List price
Average Discount
Average selling price
Gross Margin
Direct Cost
Component Cost
Which part of cost you can control?
How to obtain a good design in a cost-effective way?
Chip area
number of gates
number of inputs
design time

44. Dependability Concern: What if Techniques:
design is not perfect, or
operational environments cause a fault in the system, or
a malicious fault committed by human being?
High Confidence
Techniques:
Fault -Avoidance: Testing, Verification
Zero-defect is impossible for complex systems
Fault-Tolerance:
Design the system such that it will perform well as expected in spite of presence of faults
Error detection/correction Codes
One area of my research interests

45. Rules-of-thumb of a Good Design
Divide-and-conquer Principle
Partition a complex problem into a set of simple problems
Start from a simple problem step-by-step
Formulate a final solution by combining the solutions to all simple problems
KISS Principle
Keep It Simple, Stupid!
The simplest solution is the correct one
Keep it simple and make it work first

46. Rules-of-thumb of a Good Design (Cont’d)
Murphy’s Law
Things DO break at the last minute!
Plan ahead, start earlier, and make continuous progress.
Forrest Gump’s Law
Never give up!
It does not fail until you give up
Working hard is never an excuse for failure

47. Summary Design of sequential systems with FFs
State assignment
one-FF-per-bit
one-FF-per-state
Implementation
Use excitation function of FFs
Analysis of sequential systems with FFs
Timing analysis
Functional analysis
Use characteristic equations of FFs

48. Next Lecture
Chapter 9