1. 1. Illustration of the Technology Scale down
Etienne Sicard

2. E. Sicard - Technology scale down
Summary
1. Who’s who
2. Road map
3. The MOS device
4. The inverter
5. Conclusion
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E. Sicard - Technology scale down

3. E. Sicard - Technology scale down
1. Who’s who in France
Philips
Philips Ibm
ST rennes
Atmel
Atmel
ST Grenoble
ST Tours
Texas, VLSI
Cadence
ST, Atmel
Motorola
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E. Sicard - Technology scale down

4. E. Sicard - Technology scale down
2. Roadmap
Bits 4G
10 GIGA
DRAM 1G
256M
1 GIGA
64M
100 MEG
16M 4M
10 MEG 1M
1 MEG
256K
100K
Year 83 86 89 92 95 98 01 04
Année
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E. Sicard - Technology scale down

5. E. Sicard - Technology scale down
2. Roadmap
Technology
(µm)
2.0
80286
Production
80386
1.0
486
pentium
0.3
pentium II
0.2
Pentium IV
Research
0.1
0.05
0.03 83 86 89 92 95 98 01 04
Year
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E. Sicard - Technology scale down

6. E. Sicard - Technology scale down
2. Roadmap
Leti
1 MOS
0.02µm
Dec. 2000
IBM
106 MOS
0.015µm
Nov. 2001
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E. Sicard - Technology scale down

7. E. Sicard - Technology scale down
2. Roadmap
0.5 µm
0.18 µm
0.12µm l
Devices
1995
2000
2002
3 layers
Interconnects
7 layers
8 layers
Frequency
1500 MHz
120MHz
500MHz
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8. E. Sicard - Technology scale down
2. Roadmap
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9. E. Sicard - Technology scale down
2. Roadmap
Supply (V)
Chip I/Os
5.0
I/O trend
Core trend
3.3
Chip Core
2.5
1.5
Technology (µm)
0.5
0.35
0.18
0.10
0.07
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10. E. Sicard - Technology scale down
2. Roadmap
Radiation
Typical wire load (fF)
100 75 50
Charge 25
Charges (C.V)
Technology (µm)
0.5
0.35
0.18
0.10
0.07
“Soft error” due to radiation becomes probable
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E. Sicard - Technology scale down

11. E. Sicard - Technology scale down
3. The MOS device 1 3 2 I V 3
demo 2 1
Little quiz V
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12. E. Sicard - Technology scale down
3. The MOS device 1 1
demo
Ron close from 1000
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E. Sicard - Technology scale down

13. E. Sicard - Technology scale down
3. The MOS device 1
Good 0
Bad 1
Bad 0
Good 1
Technology scale down keeps those drawbacks
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14. E. Sicard - Technology scale down
3. The MOS device
R off
Static Current (A) 1
0.1
0.01
0.001
100 M
1 MT block
10 M
1 M
Low leakage MOS
100K
Technology (µm)
0.5
0.35
0.18
0.10
0.07
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15. E. Sicard - Technology scale down
3. The MOS device
Low power
High Speed
High Voltage
3.3V
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16. E. Sicard - Technology scale down
4. The inverter In
Out
Time
In 0.25µm typical delay 50ps
Depends on conditions (10,90%)
Depends on charge (capacitance)
demo
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E. Sicard - Technology scale down

17. E. Sicard - Technology scale down
4. The inverter
Idd (mA)
In, Out
(V)
Time
Current peaks 0.2mA
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E. Sicard - Technology scale down

18. E. Sicard - Technology scale down
4. The inverter
Delay (ns)
Interconnection (µm)
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19. E. Sicard - Technology scale down
4. The inverter
Ring oscillator
0.7µm
0.25µm
Frequencies x 5 although VDD divided by 2
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E. Sicard - Technology scale down

20. E. Sicard - Technology scale down
Conclusion
Illustration of technology scale down
Continuous gain in frequency
Power supply reduction
The MOS keeps the same, but many versions
Increased interconnects improve density
In 2002, ST will produce the 0.12µm technology
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E. Sicard - Technology scale down