1. Computer Architecture
Introduction

2. Syllabus ECE 4551 Computer Architecture
Contact Info: Këpuska, Veton Olin Engineering Building, Office # 344 Tel. (321)
CRN   Subj   Crse   Sec   Credits   Title       ECE  4551  E1  3.00   Computer Arch.   Start Date  End Date Days & Times   Bldg Room Aug 25, 03 Dec 13, 03  TR 06:30pm-07:45pm  501ENG 118EC  
Instructor(s): Veton Këpuska
Textbook(s):
Computer Systems Design & Architecture, by Vincent P. Heuring & Harry F.Jordan, Addison Wesley Longman, Inc.,1997, ISBN X.
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3. Syllabus
Course Goals: To provide a clear understanding of the structure and function of the digital computer at all levels from digital logic, or gate level, to the machine language programming level, to the overall system, or architectural level.
Subject Area: Computer Architecture
Prerequisites: ece3551 or cse3101
Topics Covered:
COMPUTER HARDWARE DESIGN/BIT-SLICE ARCHITECTURE. A study of the design of large computer systems and special-purpose controllers. The theory behind bit-slice concepts, microcode, pipelines, cache memory, instruction execution overlapping is also covered. Systems are designed using bit-slice technology and microcode.
Recommended Grading
Homework: 30%
Exams: 70% (20%+20%+30%)
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4. Blackboard Enroll in the class using Blackboard:
->
Course Catalog ->
Traditional Courses ->
Computer Archit. ->
Login ->
Create an Account
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5. Backup Course Information
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6. The General Purpose Machine
Topics
1.1 The General Purpose Machine
1.2 The User’s View
1.3 The Machine/Assembly Language Programmer’s View
1.4 The Computer Architect’s View
1.5 The Computer System Logic Designer’s View
1.6 Historical Perspective
1.7 Trends and Research
1.8 Approach of this course
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7. The General Purpose Machine—A Perspective
Alan Turing showed that an abstract computer, a Turing machine, can compute any function that is computable by any means.
A general purpose computer with enough memory is equivalent to a Turing machine.
Over 50 years, computers have evolved
from memory size of 1 kiloword (1024 words) clock periods of 1 millisecond (0.001 s)
to memory size of a terabyte (240 bytes) and clock periods of 1 ns (10-9 s)
More speed and capacity is needed for many applications, such as:
Real-time 3D animation
Image rendering
Weather forecasting
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8. Scales, Units, and Conventions
Term
K (kilo-)
M (mega-)
G (giga-)
T (tera-)
103
106
109
1012
210
= 1,024
220
= 1,048,576
230
= 1,073,741,824
240
= 1,099,511,627,776
Normal Usage
As a power of 2
Term
Usage
m (milli-) m
(micro-)
n (nano-)
p (pico-)
10-3
10-6
10-9
10-12
Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word,
Second (s), Hertz (Hz)
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9. Scales, Units, and Conventions
Left-most bit => most significant bit (msb)
Right-most bit => least significant bit (lsb)
Seconds => s
Bits => b
Bytes => B
Words => w
Examples:
Gb/s (Giga bits per second)
MB (MegaBytes)
100 ns (NanoSeconds)  10 MHz
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10. Fig 1.1 The User’s View of a Computer
The user sees software, speed, storage capacity,
and peripheral device functionality.
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11. Machine/Assembly Language Programmer’s View
Machine language:
Set of fundamental instructions the machine can execute
Expressed as a pattern of 1’s and 0’s
Assembly language:
Alphanumeric equivalent of machine language
Mnemonics more human-oriented than 1’s and 0’s
Assembler:
Computer program that transliterates (one-to-one mapping) assembly to machine language
Computer’s native language is machine/assembly language
“Programmer,” as used in this course, means machine/assembly language programmer
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12. Machine and Assembly Language
The assembler converts assembly language to machine language. Student must also know how to do this.
Op code
Data reg. #5
Data reg. #4
MC68000 Assembly Language
Machine Language
MOVE.W D4, D5
ADDI.W #9, D2
Tbl 1.2 Two Motorola MC68000 Instructions
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13. The Stored Program Concept
The stored program concept says that the program
is stored with data in the computer’s memory. The
computer is able to manipulate it as data—for
example, to load it from disk, move it in memory,
and store it back on disk.
It is the basic operating principle for every computer.
It is so common that it is taken for granted.
Without it, every instruction would have to be initiated manually.
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14. The Stored Program Concept
The stored program concept originated with Eckerd and Mauchley’s group in the mid-1940s. (ENIAC)
Machine language program that is stored in the machine’s memory is executed instruction by instruction.
One by one, machine language instructions are fetched out of the computer’s memory,
Temporarily stored in the instruction register (IR), and
Executed by the central processing unit (CPU).
The information where the next instruction is to be fetched is stored in a register known as program counter (PC)
This is referred to as fetch-execute cycle.
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15. Basic Organization of Digital Computers
Memory
Input
Output
Control
Processing
(ALU)
CPU
Data and Instructions
Instructions
Decision Results
Results/Data
Control Signals
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16. Fig 1.2 The Fetch-Execute Process
Byte addressable memory M C 6 8 P U a i n m e o r y 4 3 1 2 – 5 I R V u s g t T h c l
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17. Programmer’s Model: Instruction Set Architecture (ISA)
Instruction set: the collection of all machine operations.
Programmer sees set of instructions, along with the machine resources manipulated by them.
ISA includes
Instruction set,
Memory, and
Programmer-accessible registers of the system.
There may be temporary or scratch-pad memory used to implement some function- hence is not considered to be part of ISA.
Not Programmer Accessible.
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18. Fig 1.3 Programmer’s Models of 4 Commercial Machines( i n t r o d u c e d 1 9 7 5 ) ( i n t r o d u c e d 1 9 7 9 ) ( i n t r o d u c e d 1 9 8 1 ) ( i n t r o d u c e d 1 9 9 3 ) 7 1 5 8 7 3 1 6 3 A A X R 3 2 1 5 B D a t a B X 1 2 g e n e r a l 6 4 - b i t r e g i s t e r s p u r p o s e f l o a t i n g p o i n t 6 s p e c i a l I X C X R 1 1 p u r p o s e r e g i s t e r s r e g i s t e r s S P D X A P 3 1 r e g i s t e r s P C F P 3 1 S P S t a t u s A d d r e s s S P a n d B P 3 2 3 2 - b i t P C c o u n t S I g e n e r a l r e g i s t e r s p u r p o s e D I P S W r e g i s t e r s 3 1 C S M e m o r y D S 3 1 2 1 6 b y t e s s e g m e n t 2 3 2 b y t e s r e g i s t e r s S S o f m a i n o f m a i n M o r e t h a n 5 m e m o r y E S m e m o r y 3 2 - b i t s p e c i a l c a p a c i t y c a p a c i t y p u r p o s e 2 1 6 – 1 2 3 2 – 1 r e g i s t e r s I P S t a t u s M o r e t h a n 3 F e w e r i n s t r u c t i o n s t h a n 1 i n s t r u c t i o n s 2 2 b y t e s 2 5 2 b y t e s o f m a i n o f m a i n m e m o r y m e m o r y c a p a c i t y c a p a c i t y 2 2 – 1 2 5 2 – 1 M o r e t h a n 1 2 M o r e t h a n 2 5 i n s t r u c t i o n s i n s t r u c t i o n s
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19. Programmer’s Model RISC – Reduced Instruction Set Computer
CISC – Complex Instruction Set Computer
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20. Machine, Processor, and Memory State
The Machine State: contents of all registers in system, accessible to programmer or not
The Processor State: registers internal to the CPU
The Memory State: contents of registers in the memory system
“State” is used in the formal finite state machine sense
Maintaining or restoring the machine and processor state is important to many operations, especially for procedure calls and interrupts
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21. Data Type: HLL Versus Machine Language
HLLs provide type checking
Verifies proper use of variables at compile time
Allows compiler to determine memory requirements
Helps detect bad programming practices
Most machines have no type checking
The machine sees only strings of bits
Instructions interpret the strings as a type: usually limited to signed or unsigned integers and FP numbers
A given 32-bit word might be an instruction, an integer, a FP number, or 4 ASCII characters
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22. Tbl 1.3 Instruction Classes
This compiler:
Maps C integers to 32-bit VAX integers
Maps C assign, *, and + to VAX MOV, MPY, and ADD
Maps C goto to VAX BR instruction
The compiler writer must develop this mapping for each language-machine pair
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23. Tools of the Assembly Language Programmer’s Trade
The assembler
The linker
The debugger or monitor
The development system
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24. Who Uses Assembly Language
The machine designer
Must implement and trade off instruction functionality
The compiler writer
Must generate machine language from a HLL
The writer of time or space critical code
Performance goals may force program-specific optimizations of the assembly language
Special purpose or embedded processor programmers
Special functions and heavy dependence on unique I/O devices can make HLLs useless
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25. The Computer Architect’s View
Architect is concerned with design & performance
Designs the ISA for optimum programming utility and optimum performance of implementation
Designs the hardware for best implementation of the instructions
Uses performance measurement tools, such as benchmark programs, to see that goals are met
Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections
Meets performance and functional goals at lowest cost
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26. Buses as Multiplexers Interconnections are very important to computer
Most connections are shared
A bus is a time-shared connection or multiplexer
A bus provides a data path and control
Buses may be serial, parallel, or a combination of both
Serial buses transmit one bit at a time
Parallel buses transmit many bits simultaneously on many wires
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27. Fig 1.4 Simple One- and Two-Bus Architecturesy M e m o r y M e m o r y b u s C P U C P U I / O b u s I n p u t / I n p u t / o u t p u t o u t p u t s u b s y s t e m s u b s y s t e m n n - b i t s y s t e m b u s I n p u t / o u t p u t I n p u t / o u t p u t d e v i c e s d e v i c e s ( a ) O n e b u s ( b ) T w o b u s e s
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28. Fig 1.5 The Apple Quadra 950 Bus System (Simplified)o c a l T a l k b u s P r i n t e r s , o t h e r L o c a l T a l k c o m p u t e r s i n t e r f a c e A D B A D B b u s K e y b o a r d , m o u s e , b i t p a d s t r a n s c e i v e r S y s t e m S C S I S C S I b u s D i s k d r i v e s , b u s i n t e r f a c e C D R O M d r i v e s N u B u s V i d e o a n d s p e c i a l N u B u s p u r p o s e c a r d s i n t e r f a c e C P U E t h e r n e t E t h e r n e t O t h e r c o m p u t e r s t r a n s c e i v e r M e m o r y
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29. Fig 1.6 The Memory Hierarchy
Modern computers have a hierarchy of memories
Allows tradeoffs of speed/cost/volatility/size, etc.
CPU sees common view of levels of the hierarchy. C P U C a c h e M a i n D i s k T a p e m e m o r y m e m o r y m e m o r y m e m o r y
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30. Tools of the Trade Software models, simulators and emulators
Performance benchmark programs
Specialized measurement programs
Data flow and bottleneck analysis
Subsystem balance analysis
Parts, manufacturing, and testing cost analysis
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31. Logic Designer’s View Designs the machine at the logic gate level
The design determines whether the architect meets cost and performance goals
Architect and logic designer may be a single person or team
Programmable Solutions: CPLD’s & FPGA’s
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32. Implementation Domains
An implementation domain is the collection of
devices, gate & logic levels, etc. which the designer uses.
Possible implementation domains:
VLSI on silicon
TTL or ECL chips
Gallium arsenide chips
PLAs or sea-of-gates arrays
Programmable Solutions: CPLD’s & FPGA’s
Fluidic logic or optical switches
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33. Fig 1.7 Three Implementation Domains for the 2-1 Multiplexer
2-1 multiplexer in three different implementation domains
Generic logic gates (abstract domain)
National Semiconductor FAST Advanced Schottky TTL (VLSI on Si)
Fiber optic directional coupler switch (optical signals in LiNbO3) U 6 1 5 / G 1 S / A / B 2 1 A 4 1 Y 3 1 B 5 2 A 7 6 2 Y S 2 B I O 1 1 3 A 9 I 1 I 1 3 Y 3 B O 1 4 I 4 A 1 2 S I 1 1 3 4 Y O I 1 4 B 7 4 F 2 5 7 N ( a ) A b s t r c v i e w o f B l n g ( b ) T T L i m p l e m e n t a t i o n ( c ) O p t i c a l s w i t c h d o m a i n i m p l e m e n t a t i o n
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34. The Distinction Between Classical Logic Design and Computer Logic Design
The entire computer is too complex for traditional Finite State Machine (FSM) design techniques
FSM techniques can be used “in the small”
There is a natural separation between data and control
Data path: storage cells, arithmetic, and their connections
Control path: logic that manages data path information flow
Well defined logic blocks are used repeatedly
Multiplexers, decoders, adders, etc.
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35. Two Views of the CPU’s PC Register31 PC
Programmer:
Logic Designer
(Fig 1.8):
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36. Tools of the Logic Designer’s Trade
Computer-aided design tools
Logic design and simulation packages
Printed circuit layout tools
IC (integrated circuit) design and layout tools
Logic analyzers and oscilloscopes
Hardware development system
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37. Brief Overview of Computer Evolution
From Abacus to Mechanical Calculators Designed in17th Century by Pascal and Leibniz.
First Device that is considered a computer in modern sense was proposed by Charles Babbage in 1830 (Analytical Engine).
Howard Aiken of Harvard University in 1937 proposed Automatic Sequence Controlled Calculator -> Mark I sponsored by Harvard and IBM. Completed in August 7, Mark I was electromechanical machine.
ENIAC first Digital Computer based on Vacuum Tubes: J.P. Eckert and J.W. Mauchly, and John von Neumann mathematical consultant.
Great Speed of Electronic Devices => Unnecessary to have many parallel calculating elements.
Storing the Program in Memory much the same manner as data => made possible to branch to alternate sequences of instructions.
New Developments in electronics => EDVAC
Von Neumann’s 5 basic principles that defines a computer:
It must have an input medium, by means of which an essentially unlimited number of operands or instructions may be entered.
It must have store, from which operands or instructions may be obtained and into which results may be entered, in any desired order.
It must have a calculating section, capable of carrying out arithmetic or logical operations on any operands taken from the store.
It must have an output medium, my means of which an essentially unlimited number of results may be delivered to the user.
It must have a control unit, capable of interpreting instructions obtained from memory, and capable of choosing between alternative courses of action on the bases of computed results.
Eckert and Mauchly developed first commercially produced computer – UNIVAC I (1951).
Von Neumann at Princeton led development of IAS (1951)
Indexing and indirect addressing.
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38. Historical Generations
1st Generation: 1946–59, vacuum tubes, relays, mercury delay lines
2nd generation: 1959–64, discrete transistors and magnetic cores
3rd generation: 1964–75, small- and medium-scale integrated circuits
4th generation: 1975–present, single-chip microcomputer
Integration scale: components per chip
Small: 10–100
Medium: 100–1,000
Large: 1000–10,000
Very large: greater than 10,000
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39. Chapter 1 Summary
Three different views of machine structure and function
Machine/assembly language view: registers, memory cells, instructions
PC, IR
Fetch-execute cycle
Programs can be manipulated as data
No, or almost no, data typing at machine level
Architect views the entire system
Concerned with price/performance, system balance
Logic designer sees system as collection of functional logic blocks
Must consider implementation domain
Tradeoffs: speed, power, gate fan-in, fan-out
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