EC6504 Microprocessor and Microcontrollers

EC6504 Microprocessor and Microcontrollers
(Regulation 2013)

Objectives Study the Architecture of 8086Microprocessor
Learn the design aspects of I/O and Memory Interfacing circuits Study about communication and bus interfacing. Study the Architecture of 8051 microcontroller. 21-Sep-18

Syllabus UNIT I - THE 8086 MICROPROCESSOR (9)
Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and assembler directives – Assembly language programming – Modular Programming - Linking and Relocation - Stacks - Procedures – Macros – Interrupts and interrupt service routines – Byte and String Manipulation. UNIT II SYSTEM BUS STRUCTURE (9) 8086 signals – Basic configurations – System bus timing –System design using 8086 – IO programming – Introduction to Multiprogramming – System Bus Structure - Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to advanced processors. 21-Sep-18

Syllabus UNIT III - I/O INTERFACING (9)
Memory Interfacing and I/O interfacing - Parallel communication interface – Serial communication interface – D/A and A/D Interface - Timer – Keyboard /display controller – Interrupt controller – DMA controller – Programming and applications Case studies: Traffic Light control, LED display , LCD display, Keyboard display interface and Alarm Controller. UNIT IV - MICROCONTROLLER (9) Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and Circuits - Instruction set - Addressing modes - Assembly language programming. 44 UNIT V - INTERFACING MICROCONTROLLER (9) Programming 8051 Timers - Serial Port Programming - Interrupts Programming – LCD & Keyboard Interfacing - ADC, DAC & Sensor Interfacing - External Memory Interface- Stepper Motor and Waveform generation TOTAL: 45 PERIODS 21-Sep-18

Text Books [1] Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088 Family - Architecture, Programming and Design”, Second Edition, Prentice Hall of India, [2] Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, “The 8051 Microcontroller and Embedded Systems: Using Assembly and C”, Second Edition, Pearson Education, [3] Doughlas V.Hall, “Microprocessors and Interfacing, Programming and Hardware”, TMH,2012 21-Sep-18

Unit-I The 8086 Microprocessor
Objective Study the Architecture of 8086 Microprocessor Write 8086 Assembly Language Programs 21-Sep-18

Overview Introduction to 8086 8086 Architecture Addressing Modes
8086 Instruction Set Assembler Directives Assembly Language Programming Modular Programming Stacks Procedures Macros Interrupts and Interrupt Service Routines Byte and String Programming 21-Sep-18

Introduction to 8086 Overview of Microcomputer Systems
Two principal components 1. Hardware CPU, Timing circuits Memory Units Input / Output Subsystems Bus control Logic System Bus 2. Software System Software User Software 21-Sep-18

List of Intel Microprocessors
Introduction to 8086 (continued.....) 21-Sep-18

Microprocessors by other Companies

Architecture of a typical Microcomputer System

Software Hierarchy Introduction to 8086 (continued.....) 21-Sep-18

Three Levels of Programming
used to write a program for a microcomputer Machine Language Binary form of program (Instructions / data in1’ and 0’s form) Difficult for programmer to memorize Error occurs easily Assembly Language More readable form of machine language Uses mnemonic codes Assembler needed to translate to machine code High Level Language Uses English-like program statements Programs can usually be written faster & easily Compiler needed to translate high-level language statement to machine code Executed slowly ; Require more memory Introduction to 8086 (continued.....) 21-Sep-18

Assembler An assembler translates the assembly language program into machine language program Assembly language program à source codes Machine language program à object codes Introduction to 8086 (continued.....) 21-Sep-18

Data Representation Number Formats Binary (or Integer)
[+ve, -ve Integers; Base 2, 8, 10, 16] Floating Point (or Real) Binary Coded Decimal (BCD) (or Decimal) Alphanumeric Codes EBCDIC-Extended Binary Coded Decimal Interchange Code ASCII – American Standard Code for Information Interchange Introduction to 8086 (continued.....) 21-Sep-18

General Operation of a Computer

Operation of µP 1. Fetch 2. Decode 3. Execute

8086 Architecture 21-Sep-18

8086 Chipset 8086 Architecture 21-Sep-18

8086 Architecture (continued…)
Features 16-bit microprocessor , most of instructions are designed to work with 16 bit binary words Data bus : 16 bit (read data from or write data to memory and ports either 16 bits or 8 bits at a time Address bus : 20 bit (can address upto 220= = 1MB memory locations). [Address range : 00000H to FFFFFH] It provides 14, 16-bit registers. It has multiplexed Address and Data bus AD0- AD15 and A16 – A19. 8086 Architecture (continued…) 21-Sep-18

8086 Features Has ‘Look ahead’ feature to increase the throughput. (i.e) It can prefetch upto 6 bytes from memory and queues them in order to speed up instruction execution. 40 pin dual in line package Supply Voltage: +5V ; Clock Speed: 5MHz, 8MHz, 10MHz 8086 is designed to operate in two modes, Minimum and Maximum. 8086 Architecture (continued…) 21-Sep-18

CPU-Memory interface CPU 8086 Memory 20 16 Addess Bus Data Bus Control Bus 8086 Architecture (continued…) 21-Sep-18

21-Sep-18

The 8086 has two parts: the Bus Interface Unit (BIU) Fetches instructions, Reads and Writes data, and computes the 20-bit address for memory operands Transfers instruction bytes into the 6 byte FIFO queue the Execution Unit (EU) Decodes and Executes the instructions using the 16-bit ALU. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. 8086 Architecture (continued…) 21-Sep-18

8086 Internal registers 16 bits (2 bytes each)
BIU Registers CS DS ES SS IP Code Segment Data Segment Extra Segment Stack Segment Instruction Pointer AX AH AL BH BL CH CL DH DL SP BP SI DI Flags EU Registers Accumulator BX Base Register CX Count Register DX Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register Flag Register 8086 Architecture (continued…) 21-Sep-18

The 8086 Microprocessor: Registers
In total there are Fourteen 16-bit registers in an 8086 8086 Architecture (continued…) 21-Sep-18

The 8086 Microprocessor: Registers
Registers are in the CPU and are referred to by specific names Data registers Hold data for an operation to be performed There are 4 data registers (AX, BX, CX, DX) Address registers Hold the address of an instruction or data element Segment registers (CS, DS, ES, SS) Pointer registers (SP, BP, IP) Index registers (SI, DI) Status register Keeps the current status of the processor The status register is called the FLAG register 8086 Architecture (continued…) 21-Sep-18

Data Registers: AX, BX, CX, DX
Instructions execute faster if the data is in a register Data Registers are general purpose registers but they also perform special functions AX, BX, CX, DX are the data registers Low and High bytes of the data registers can be accessed separately AH, BH, CH, DH are the high bytes AL, BL, CL, DL are the low bytes 8086 Architecture (continued…) 21-Sep-18

AX Accumulator Register Used in Arithmetic, Logic and Data Transfer instructions Used in Multiplication and Division operations Used in I/O operations BX Base Register Also serves as an address register Used in array operations Used in Table Lookup operations (XLAT) CX Count register Used as a Loop Counter Used in shift and rotate operations DX Data register Used in Multiplication and Division Also used in I/O operations 8086 Architecture (continued…) 21-Sep-18

Pointer and Index Registers
Contains the offset addresses of memory locations Can also be used in Arithmetic and other operations SP: Stack pointer Used with SS to access the stack segment BP: Base Pointer Primarily used to access data on the stack Can be used to access data in other segments 8086 Architecture (continued…) 21-Sep-18

Pointer and Index Registers
SI: Source Index register is required for some string operations SI is associated with the DS in string operations. DI: Destination Index register is also required for some string operations. DI is associated with the ES in string operations. The SI and the DI registers may also be used to access data stored in arrays 8086 Architecture (continued…) 21-Sep-18

Segment Registers - CS, DS, SS and ES
Are Address registers Stores the memory addresses of instructions and data Memory Organization 20 bit address line addresses 1 MB of memory Each byte in memory has a 20 bit address Addresses are expressed as 5 hex digits from FFFFF Problem: 20 bit addresses are TOO BIG to fit in 16 bit registers! Solution: Memory Segment A segment number is a 16 bit number Segment numbers range from 0000 to FFFF Block of 64K (65,536) (i.e 216)consecutive memory bytes Within a segment, a particular memory location is specified with an offset An offset also ranges from 0000 to FFFF 8086 Architecture (continued…) 21-Sep-18

Segmented Memory Architecture
Memory space is divided into overlapping segments Each segment is of 64 Kbytes Segment address begins at an address that is divisible by or 1016 Segment register contains the starting address of a segment. 16 bit words will be stored in two consecutive memory locations. If first byte of the data is stored at an even address, reads the entire word in one operation. Example if the 16 bit data 2607H is stored at even address 00520H, then for instruction MOV BX, [00520], 8086 reads the first byte and stores the data in BL and reads the second byte and stores the data in BH. BL ß (00520) BH ß(00521) 8086 Architecture (continued…) 21-Sep-18

If the first byte of data is stored at an odd address, needs two operation to read the 16 bit data. Example if the 16 bit data F520H is stored at odd address 00521H, then for instruction MOV BX, [00521], In first operation, 8086 reads the 16 bit data from the location and stores the data of location in register BL and discards the data of location. In second operation, 8086 reads the 16 bit data from the location and stores the data of location in register BH and discards the data of location. 8086 Architecture (continued…) 21-Sep-18

1MB Memory Space divided into non-overlapping segments
            Seg-1 Seg-2 Seg-3 Seg-4 Seg-5 Seg-6 Seg-7 Seg-8 Seg-15 Seg-16 64 KB 00000 0FFFF 10000 1FFFF 20000 2FFFF EFFFF FFFFF 8086 Architecture (continued…) 21-Sep-18

Segmented memory addressing: Absolute Address = Four bit left shifted16-bit segment value added to a 16-bit offset 1 MB Memory Space Starting Address of each segment 00000 10000 20000 30000 40000 50000 60000 70000 80000 90000 A0000 B0000 C0000 D0000 E0000 F0000 5000:0000 5000:FFFF 5000:0250 SegAddr:Offset 8086 Architecture (continued…) 21-Sep-18

Physical Memory Address Generation
The BIU has a dedicated adder for determining Physical memory addresses Physical Address (20 Bits) Adder Offset Value or Effective address (16 bits) Segment Register (16 bits) 8086 Architecture (continued…) 21-Sep-18

Physical Memory Address Generation
Logical Address is specified as Segment:Offset Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address Thus the physical address of the logical address A4FB:4872 is A4FB0   A9822 1010 0100 1111 1011 0000 0100 1000 0111 0010 1001 1001 1000 0010 0010 8086 Architecture (continued…) 21-Sep-18

Overlapping segments 8086 Architecture (continued…) 21-Sep-18

Advantages of using Segment Registers
Even though addresses associated with the instructions are 16 bits only, allows the memory capacity to be 1MB More than one Code, Data or Stack segment can be used for programs more than 64KB long. Facilitates, use of separate memory areas for a program, its data and the stack. Permit a program and/or its data to be put into different areas of memory each time the program is executed. 8086 Architecture (continued…) 21-Sep-18

Separation of a program’s Code, Data and Stack segment & Program relocation using the CS register 8086 Architecture (continued…) 21-Sep-18

Flags Carry flag Overflow flag Parity flag Direction flag Auxiliary flag Interrupt enable Trap flag Zero flag 6 - status flags 3 - control flags Sign flag 8086 Architecture (continued…) 21-Sep-18

Flags Status or Conditional flags: These are set according to the results of the arithmetic or logic operations. Need not be altered by the user. Control flags: Used to control some operations of the MPU. These flags are to be set by the user, in order to achieve some specific purposes. 8086 Architecture (continued…) 21-Sep-18

Status or Conditional or Condition Code Flags
CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation. PF (parity) Indicates the number of 1 bits that result from an operation.(1=even) AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic (BCD). ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) OF (overflow) Indicates overflow of the leftmost bit during arithmetic. 8086 Architecture (continued…) 21-Sep-18

Control flags: DF (direction) Indicates left or right for moving or comparing string data. IF (interrupt) Indicates whether external interrupts are being processed or ignored. TF (trap) Permits operation of the processor in single step mode. 8086 Architecture (continued…) 21-Sep-18

Example Assume that the previous instruction performed the following addition, SF= ZF= PF= CF= AF= OF= 0101 0011 0010 0100 1001 0001 1110 0101 1001 0100 0101 0011 1010 0110 SF= ZF= PF= CF= AF= OF= 1 1 0011 1001 0101 1 8086 Architecture (continued…) 21-Sep-18

Addressing Modes 21-Sep-18

Addressing Modes Various methods used to access instruction operands is called as Addressing Mode General Instruction Format Operands may be contained in Registers, Memory I/O ports. Three basic modes of addressing are Immediate Register OPCODE Operand       Addressing Modes 21-Sep-18

Addressing Modes (continued...)
Example: If CS=24F6h & IP=634Ah, show the; 1- The logical address 2- The offset address 3- The physical address 4- The lower range of the segment 5- The upper range of the segment Solution: 1- The logical address is the CS: IP content which is: 24F6:634A 2- The offset address is the content of the IP register which is: 634A 3- The physical address: Addressing Modes (continued...) 21-Sep-18

8086 Addressing modes - classified according to flow of instruction execution Sequential flow instructions Arithmetic Logical Data transfer Processor control Control transfer instructions INT CALL RET JUMP Addressing Modes (continued...) 21-Sep-18

Sequential flow instructions Implied Addressing mode Immediate addressing mode Direct addressing mode Register addressing mode Register Indirect addressing mode Indexed addressing mode Register Relative addressing mode Based Indexed addressing mode Relative Based Indexed addressing mode Control transfer instructions Intersegment Direct addressing mode Intersegment Indirect addressing mode Intra segment Direct addressing mode Intra segment Indirect addressing mode Addressing Modes (continued...) 21-Sep-18

Sequential Flow Instructions Implied Addressing - The data value/data address is implicitly associated with the instruction. AAA AAS AAM AAD DAA DAS XLAT Addressing Modes (continued...) 21-Sep-18

Sequential Flow Instructions
Immediate Addressing – Data / operand is part of the instruction MOV AX, 25BF ; MOV AL, 8EH ; Direct Addressing – Data is pointed by 16 bit offset value specified in the instruction MOV AX, [5000H] ; Destination Source [ AX25BF H ] 16 Bit Data [ AL8E ] 8 Bit Data Effective Addr = 5000 PhyAddr = 10H*DS H Addressing Modes (continued...) 21-Sep-18

Register Addressing – Data is in the register specified in the instruction MOV BX, AX No PhyAddr, since data is in regr 16 BIT Operand Registers - AX, BX, CX,DX, SI, DI, SP, BP 8 BIT Operand Registers - AL, AH, BL, BH, CL, CH, DL, DH Addressing Modes (continued...) 21-Sep-18

Register Indirect Addressing – Data is pointed by the offset value in the register, specified in the instruction MOV AX, [BX] Default Segment - DS or ES Offset – BX or SI or DI PhyAddr = DS ES BX SI DI + 10H * If DS=5000H; BX=10FF; Then EffectiveAddr = 10FF and PhyAddr = 10H*5000H + 10FFH = 510FFH Addressing Modes (continued...) 21-Sep-18

Indexed Addressing Data is pointed by the offset in the index register specified in the instruction DS is the default segment register for SI and DI MOV AX, [SI] Data is available in the logical address [DS:SI] Effective Addr = [SI] PhyAddr = DS SI DI + 10H * Addressing Modes (continued...) 21-Sep-18

Register Relative Addressing Data is pointed by the sum of 8 bit or 16 bit displacement specified in the instruction plus Offset specified in the registers –BX, BP, SI, DI Default segment registers – DS, ES MOV AX, 50H [BX] EffectiveAddr = 50H+[BX] PhyAddr = DS ES BX BP SI DI + 10H * Addressing Modes (continued...) 21-Sep-18

Based Indexed Addressing Data is pointed by content of base register specified in the instruction plus Content of index register specified in the instruction Default segment registers – DS, ES MOV AX, [BX] [SI] BX BP SI DI + EffectiveAddr = BX BP SI DI + 10H * DS ES + PhyAddr = Addressing Modes (continued...) 21-Sep-18

Register Relative Addressing Data is pointed by the sum of 8 bit or 16 bit displacement specified in the instruction plus Offset specified in the base registers –BX, BP plus Offset specified in the index registers – SI, DI Default segment registers – DS, ES 8 bit 16 bit + BX BP SI DI + EffectiveAddr = BX BP SI DI + 10H * DS ES + 8 bit 16 bit + PhyAddr = Addressing Modes (continued...) 21-Sep-18

Control Transfer Instructions
Intrasegment Direct Addressing – Control transfer instruction and Address where control is transferred lies in the same segment Immediate displacement value specified in instruction Displacement is w.r.t IP register content Short jump – i.e (-27 < d < +27-1) = (-128 < d < +127 ) = (-80H < d < +7FH ) Long jump – i.e (-215 < d < +215 ) = ( < d < ) Example: JMP SHORT LABEL LABEL lies within (-128 to +127 ) from the current IP content 8 bit signed displacement ‘d’ 16 bit signed displacement ‘d’ Addressing Modes (continued...) 21-Sep-18

Intrasegment Direct Addressing – Short Jump or Near Jump The jump destination is in the same code segment To execute the jump, only the contents of Instruction Pointer (IP) register needs to be changed Code Segment CS: 3000H IP: 0000H JMP NEXT CS: 3000H IP: 0010H CS: 3000H IP: 0020H INC BX NEXT: Addressing Modes (continued...) 21-Sep-18

Intrasegment Indirect Addressing – Control transfer instruction and Address where control is transferred lies in the same segment Displacement value specified indirectly – as content of a register or a memory location in the instruction Used in unconditional instructions Example: JMP [BX] EffectiveAddr = [BX] PhyAddr = 10H*[CS]+[BX] Addressing Modes (continued...) 21-Sep-18

Intrasegment Indirect Addressing 60000 6FFFF Code Segment CS = 6000H BX = 75ABH Effective Addr = [BX] 675AB MOV AX, BX PhyAddr = 10H*[CS]+[BX] 61000 JMP [BX] Displacement from current location: 675AB = +65AB H= Addressing Modes (continued...) 21-Sep-18

Intersegment Direct Addressing – Control transfer instruction and Address where control is transferred lies in the different segments Branching from one code segment to another code segt CS and IP of destination address are specified in instruction Example: JMP 5000H: 2000H EffectiveAddr = PhysicalAddr = 2000H 10H * 5000H H = 52000H Addressing Modes (continued...) 21-Sep-18

Intersegment Direct Addressing Code Segment A Long Jump or Far Jump The jump destination is in a different code segment To execute the jump, has to change the contents of Code Segment (CS) register and IP register CS: 3000H IP: 0000H CS: 3000H IP: 0010H JMP NEXT Code Segment B CS: 6000H IP: 0000H CS: 6000H IP: 0050H INC BX NEXT: Addressing Modes (continued...) 21-Sep-18

Intersegment Indirect Addressing – Control transfer instruction and Address where control is transferred lies in the different segments Branching from one code segment to another code segt CS and IP of destination address are specified indirectly in the instruction Starting address of a memory block specified in instn (i.e) content of a memory block containing 4 bytes IP(LSB), IP(MSB), CS(LSB), CS(MSB) Example: JMP [2000H] EffectiveAddr = 2000H PhysicalAddr = 10H * DS H Addressing Modes (continued...) 21-Sep-18

Intersegment Indirect Addressing DS = 6000H 60000 6FFFF 62000 62002 62003 62001 60100 66H 44H 00H 70H 70000 7FFFF MSB LSB IP CS 66 44 74466 70 00 JMP [2000H] Addressing Modes (continued...) 21-Sep-18

8086 Instruction Set 21-Sep-18

Instruction Set (continued...)
Data Copy / Transfer Instructions Arithmetic Instructions Logical Instructions Shift and Rotate Instructions String Manipulation Instructions Branch and Loop Instructions Flag Manipulation Instructions Machine Control Instructions Instruction Set (continued...) 21-Sep-18

1. DATA TRANSFER INSTRUCTIONS Transfers data from one register or memory location to another register or memory location Source: Seg.Register / Gen.Register /Mem.location Destination: Seg.Register / Gen.Register /Mem.location Note: Both Source and Destination cannot be Mem.Locn Instruction Set (continued...) 21-Sep-18

General purpose byte or word transfer instructions
MOV Copy byte or word from specified source to specified destination PUSH Copy specified word to top of stack POP Copy word from top of stack to specified location XCHG Exchange bytes or exchange words XLAT Translate a byte in AL using a table in memory Simple input and output port transfer instructions IN Copy a byte or word from specified port to accumulator OUT Copy a byte or word from accumulator to specified port Instruction Set (continued...) 21-Sep-18

Special address transfer instructions: Flag transfer instructions
LEA Load effective address of operand into specified register LDS Load DS register and other specified register from memory LES Load ES register and other specified register from memory Flag transfer instructions LAHF Load (copy to ) AH with the low byte of the flag register SAHF Store (copy) AH register to low byte of flag register PUSHF Copy flag register to top of stack POPF Copy word at top of stack to flag register Instruction Set (continued...) 21-Sep-18

Comments MOV DS, 5000H Not Valid; immediate addressing with segment registers not permitted MOV AX, 5000H; MOV DS, AX MOV AX, [2000H] MOV AX, [SI] MOV AX , 50H[BX] PUSH AX PUSH DS PUSH [5000H] Immediate addressing Register addressing Direct addressing Indirect addressing Register relative / Indexed addr Push Higher Byte AH into the location pointed by SP and Push Lower Byte AL into the location pointed by SP-1; SPSP-2 Content of loc. 5000H followed by 5001H in DS are pushed into the stack Instruction Set (continued...) 21-Sep-18

Example 1 : *Knowing that, DS=2042H. SI=500H, AX=214E, MOV [SI], AX 21
Do not click the mouse to see the full animation Example 1 : *Knowing that, DS=2042H. SI=500H, AX=214E, MOV [SI], AX 21 4E AH AL 20921H 21 4E 20920H SI=500 DS=20420H DS=2042H Instruction Set (continued...) 21-Sep-18

Example 2 : XX 20000 2FFFF 2FFFE 2FFFD Physical Address Stack Segment PUSH AX SP = FFFE SS = 2000 FFFF FFFD AH AL 88 44 44 2FFFB FFFB 88 2FFFC FFFC Instruction Set (continued...) 21-Sep-18

Comments POP AX POP DS POP [5000H] XCHG [5000H], AX XCHG BX, AX IN AL, 03H IN AX, DX MOV DX, 0800H Pops stack top content pointed by SP into Lower Byte of the register / mem. location and next byte in the stack into Higher Byte of the register / mem. location ; SPSP+2 Content of stack top and next byte in the stack are popped into 5000H & 5001H in DS Exchanges data b/w AX & mem.loc [5000H] in data seg. Exchange data b/w AX & BX 03H is 8-bit port address [DX] is 6-bit port address Instruction Set (continued...) 21-Sep-18

Example 3 : 20000 2FFFF 2FFFE 2FFFD Physical Address XX Stack Segment POP AX SP = FFFE SS = 2000 FFFF FFFD AH AL xx 88 44 44 2FFFB FFFB 88 2FFFC FFFC Instruction Set (continued...) 21-Sep-18

Comments OUT 03H, AL OUT DX, AX MOV DX, 0300H OUT DX, AX Send data in AL to a port whose address is 03H Send data in AX to a port whose address is in DX Send data in AX to a port whose address is in DX, set as 0300H Instruction Set (continued...) 21-Sep-18

Example 4 : XLAT called translate instruction. The operation of XLAT is to change the value of AL with the memory pointed to by (AL+BX) AL Mem[AL+BX] dddd+mmmm data AL=dddd BX=mmmm AL=data for the example slides do not click the mouse to see the full animation Instruction Set (continued...) 21-Sep-18

More clearly the XLAT instruction converts the content of register AL, using a table. Its beginning address is contained in register BX. The content of register AL is interpreted as a relative address in the table. XLAT is the only instruction that adds 8 bit number to 16 bit number! XLAT does not Affect the flags.. Instruction Set (continued...) 21-Sep-18

8086 Instruction Set (continued...)
1 2 8 3 User KB(0-F) 16-Keys 8255 KBD interface 8086 CPU AL 7-seg Display 4 5 BX 7 9 6 LUT- Mem.Seg LUT - Example 5 : Program using XLAT Comments MOV AX, SEG TABLE MOV DS, AX MOV AL, CODE MOV BX, OFFSET TABLE XLAT Address of seg containing LUT is stored in DS Code of key pressed transferred to AL Offset of code LUT into BX used as Base Addr by XLAT EffectAddr =10*SEG + BX+AL AL [10*SEG + BX+AL] 8086 Instruction Set (continued...) 21-Sep-18

Comments LEA BX, ADR LEA SI, ADR[BX] LDS BX, 5000H LES BX, 5000H BX  Offset (ADR) SI  Offset (ADR) + [BX] BX(LB)  [5000H] BX(HB)  [5001H] DS/ES(LB)  [5002H] DS/ES(HB)  [5003H] Note: Effective Address is also called as Offset 8086 Instruction Set (continued...) 21-Sep-18

Comments LAHF SAHF PUSHF POPF AH  [Flag (LB)] Set/Reset all condition code flags except Overflow flag SP  SP-2; for each PUSH operation; Push FlagRegr(HB) followed by FlagRegr(LB) into the stack SS:SP SP  SP+2; for each POP operation; Pop into FlagRegr(LB) followed into FlagRegr(HB) from stack SS:SP 8086 Instruction Set (continued...) 21-Sep-18

Data Copy / Transfer Instructions Arithmetic Instructions Logical Instructions Shift and Rotate Instructions String Manipulation Instructions Branch and Loop Instructions Flag Manipulation Instructions Machine Control Instructions 8086 Instruction Set (continued...) 21-Sep-18

2. ARITHMETIC INSTRUCTIONS Performs Addition, Subtraction, Multiplication, Division, Increment, Decrement along with ASCII and Decimal adjustment Operands in : Immediate / Register / Memory locn. Note: Flag bits in flag register are affected 8086 Instruction Set (continued...) 21-Sep-18

Addition instructions: Multiplication instructions
Add specified byte to byte or specified word to word ADC Add byte + byte + carry flag (or) word + word + carry flag INC Increment specified byte or specified word by 1 AAA ASCII adjust after addition DAA Decimal (BCD) adjust after addition Multiplication instructions MUL Multiply unsigned byte by byte or unsigned word by word IMUL Multiply signed byte by byte or signed word by word AAM ASCII adjust after multiplication 8086 Instruction Set (continued...) 21-Sep-18

Subtraction Instructions:
Subtract byte from byte or word for word flag from word. SBB Subtract byte and carry flag from byte or word ad carry DEC Decrement specified byte or specified word by 1 NEG Negate – invert each bit of a specified byte or word and add 1. (form 2’s complement) CMP Compare two specified bytes or two specified words AAS ASCII adjust after subtraction DAS Decimal (BCD) adjust after subtraction 8086 Instruction Set (continued...) 21-Sep-18

Division Instructions:
Divide unsigned word by byte or unsigned DW by word IDIV Divide signed word by byte or signed DW by word AAD ASCII adjust before division CBW Fill upper byte of word with copies of sign bit of lower byte CWD Fill upper word of DW with sign bit of lower word 8086 Instruction Set (continued...) 21-Sep-18

Result is in destination operand All the condition code flags are affected Content of segment registers cannot be added Memory to memory addition not possible ADD Add ADD AX, 0100H ADD AX, BX ADD AX, [SI] ADD AX, [5000H] ADD [5000H], 0100H ADD 0100H 1. Immediate addressing 2. Register addressing 3. Indexed / indirect addressing 4. Direct addressing 5. Immediate addressing 6. Implicit addressing (destination AX) & immediate addressing Source : Regr / Mem.Locn / immediate Destination : Regr / Mem.Locn 8086 Instruction Set (continued...) 21-Sep-18

Same as ADD instruction Adds the carry flag bit with the result. All the condition code flags are affected ADDC Add with carry ADC 0100H ADC AX, BX ADC AX, [SI] ADC AX, [5000H] ADC [5000H], 0100H ADD 0100H 1. Immediate addressing 2. Register addressing 3. Indexed / indirect addressing 4. Direct addressing 5. Immediate addressing 6. Implicit addressing (destination AX) & immediate addressing Source : Regr / Mem.Locn / immediate Destination : Regr / Mem.Locn 8086 Instruction Set (continued...) 21-Sep-18

Register/Mem.content incremented / decremented by 1 All the condition code flags are affected except CF Immediate operand cannot be incremented INC Increment INC AX INC [BX] INC [5000H] 1. Register addressing 2. Register indirect addressing 3. Direct addressing DEC Decrement DEC AX DEC [BX] DEC [5000H] 1. Register addressing 2. Register indirect addressing 3. Direct addressing 8086 Instruction Set (continued...) 21-Sep-18

Destn.operand  Destn.operand – Source operand All the condition code flags are affected SUB Subtract SUB AX, 0100H SUB AX, BX SUB AX, [SI] SUB AX, [5000H] SUB [5000H], 0100H 1. Immediate addressing 2. Register addressing 3. Indexed / indirect addressing 4. Direct addressing 5. Immediate addressing Source : Regr / Mem.Locn / immediate Destination : Regr / Mem.Locn 8086 Instruction Set (continued...) 21-Sep-18

Destn.operand  Destn.operand – (Source operand + CF) All the condition code flags are affected SBB Subtract with borrow SBB AX, 0100H SBB AX, BX SBB AX, [SI] SBB AX, [5000H] SBB [5000H], 0100H 1. Immediate addressing 2. Register addressing 3. Indexed / indirect addressing 4. Direct addressing 5. Immediate addressing Source : Regr / Mem.Locn / immediate Destination : Regr / Mem.Locn 8086 Instruction Set (continued...) 21-Sep-18

Destn.operand – Source operand Result not stored anywhere All the condition code flags are affected ZF=1(equal); CY=1 (src > destn); CY =0, ZF=0 (src < destn) CMP Compare CMP AX, 0100H CMP BX, 0100H CMP BX, [SI] CMP BX, CX CMP [5000H], 0100H 1. Immediate addressing 2. Immediate addressing 3. Indexed / indirect addressing 4. Register addressing 5. Direct/Immediate addressing Source : Regr / Mem.Locn / immediate Destination : Regr / Mem.Locn 8086 Instruction Set (continued...) 21-Sep-18

AAA ASCII Adjust after addition Executed after ADD ADD must have added two ASCII no’s & result is in AL AAA converts AL to unpacked decimal digits(Implicit addressing) AX AH (8 bits) ALHIGH AL (8 bits) ALLOW (1) If 0 < ALLOW < 9 and AF=0, then ALHIGH = 0 (2) If 0 < ALLOW < 9 and AF=1, then ALLOW = ALLOW +06 and ALHIGH = 0 and AH=AH+1 (3) If ALLOW > 9, then AL=AL+06H and ALHIGH = 0 and AH=AH+1, ACF=CF= 1 8086 Instruction Set (continued...) 21-Sep-18

DAA Decimal Adjust Accumulator Executed after adding two packed BCD numbers Converts packed BCD numbers to unpacked BCD no’s Result has to be in AL AX AH (8 bits) ALHIGH AL (8 bits) ALLOW If ALLOW > 9 OR if AF=1, then DAA adds 06H to AL After adding 06H to AL, if ALHIGH > 9 OR if CF=1, then DAA adds 60H to AL. 8086 Instruction Set (continued...) 21-Sep-18

Logical Instructions:
NOT Logical Invert: Invert each bit of a byte or word in another byte or word AND Logical AND: AND each bit in a byte or word with the corresponding bit OR Logical OR: OR each bit in a byte or word with the corresponding bit in another byte or word XOR Logical XOR: Exclusive OR each bit in a byte or word with the corresponding bit in another byte or word TEST Logical Compare: AND operation to update flags, [OF, CF, SF, ZF, PF] but don’t change operands 8086 Instruction Set (continued...) 21-Sep-18

Logical Instructions:
NOT NOT AX; NOT [5000H]; AND AND AX, 0008H; AND AX, BX; AND [5000H], DX; OR OR AX, 0008H; OR AX, BX; OR DX, [5000H]; XOR XOR AX, 0098H; XOR AX, BX; XOR AX, [5000H]; TEST TEST AX, BX; TEST [5000H] 06H; TEST [BX][DI], CX 8086 Instruction Set (continued...) 21-Sep-18

Shift Instructions (count is either 1 or specified by CL)
4. SHIFT AND ROTATE INSTRUCTIONS SHIFT INSTRUCTIONS Shift Instructions (count is either 1 or specified by CL) SHL/ SAL Shift Left / Shift Arithmetic Left: Shift bits of byte or word left, put zero(s) in LSB(s). SHR Shift Right: Shift bits of byte or word right, put zero(s) in MSB(s). SAR Shift Arithmetic Right: Shift bits of word or byte right, copy old MSB into new MSB 8086 Instruction Set (continued...) 21-Sep-18

SHL/ SAL Shift bits of byte or word left, put zero(s) in LSB(s) 1. All flags are affected 2. Shift is through Carry Flag 3. Operand may reside in Register or Mem. Location but not immediate x Carry Flag MSB LSB SHL / SAL 1st execution 1 1 1 Carry Flag MSB LSB SHL / SAL 2nd execution 1 8086 Instruction Set (continued...) 21-Sep-18

SHR Shift bits of byte or word right, put zero(s) in MSB(s). 1. All flags are affected 2. Shift is through Carry Flag 3. Operand may reside in Register or Mem. Location x Carry Flag MSB LSB 1 SHR 1st execution 1 1 1 SHR 2nd execution 8086 Instruction Set (continued...) 21-Sep-18

SAR Shift bits of word or byte right, copy old MSB into new MSB 1. All flags are affected 2. Shift is through Carry Flag 3. Operand may reside in Register or Mem. Location x Carry Flag MSB LSB 1 SHR 1st execution 1 1 1 SHR 2nd execution 8086 Instruction Set (continued...) 21-Sep-18

Rotate Instructions (count is either 1 or specified by CL)
4. SHIFT AND ROTATE INSTRUCTIONS ROTATE INSTRUCTIONS Rotate Instructions (count is either 1 or specified by CL) ROL Rotate Left without Carry: Rotate bits of byte or word left, MSB to LSB and to CF ROR Rotate Right without Carry: Rotate bits of byte or word right, LSB to MSB and to CF RCL Rotate Left through Carry: Rotate bits of byte or word left, MSB to CF and CF to LSB RCR Rotate Left through Carry: Rotate bits of byte or word right, LSB to CF and CF to MSB 8086 Instruction Set (continued...) 21-Sep-18

ROL Rotate bits of byte or word left, MSB to LSB and to CF RCL Rotate bits of byte or word left, MSB to CF and CF to LSB ROL vs. RCL x Carry Flag 1 MSB LSB ROL 1 1 1 1st execution 2nd execution Carry Flag x 1 MSB LSB RCL 1 x 1 x 1 1 x 3rd execution 2nd execution 1st execution 8086 Instruction Set (continued...) 21-Sep-18

5. STRING MANIPULATION INSTRUCTIONS String Instructions REP An instruction prefix. Repeat following instruction until CX=0 REPE/REPZ Repeat while equal/zero REPNE/REPNZ Repeat while not equal/zero MOVX/MOVSB/ MOVSW Move byte or word from one string to another COMPS/COMPSB/ COMPSW Compare two string bytes or two string words SCAS/SCASB/ SCASW Scan a string. Compare a string byte with a byte in AL or a string word with a word in AX LODS/LODSB/ LODSW Load string byte into AL or string word into AX STOS/STOSB/STOSW Store byte from AL or word from AX into string 8086 Instruction Set (continued...) 21-Sep-18

Unconditional Branch Instructions:
6. BRANCH AND LOOP INSTRUCTIONS Unconditional Branch Instructions Conditional Branch Instructions Loop Instructions Unconditional Branch Instructions: CALL Call a procedure (subprogram), save return address on stack RET Return from procedure to calling program JMP Go to specified address to get next instruction 8086 Instruction Set (continued...) 21-Sep-18

Conditional Branch Instructions
JA/JNBE Jump if above/ jump if not below or equal JAE/JNB Jump if above or equal/ jump if not below JB/JNAE Jump if below/ jump if not above or equal JC Jump if carry =1 JBE/JNA Jump if below or equal/ jump if not above JE/JZ Jump if equal/ jump if zero JG/JNLE Jump if greater/ jump if not less than or equal JGE/JNL Jump if greater than or equal/ jump if not less than JL/JNGE Jump if less than/ jump if not greater than or equal JLE/JNG Jump if less than or equal/ jump if not greater than JNC Jump if no carry JNE/JNZ Jump if not equal/ jump if not zero 8086 Instruction Set (continued...) 21-Sep-18

Conditional Branch Instructions Interrupt Instructions:
JNO Jump if no overflow JNP/JPO Jump if not parity/ jump if parity odd (PF = 0) JNS Jump if not sign JO Jump if overflow JP/JPE Jump if parity/ jump if parity even JS Jump if sign Interrupt Instructions: INT Interrupt program execution, call service procedure INTO Interrupt program execution if OF=1 IRET Return from interrupt service procedure to main program 8086 Instruction Set (continued...) 21-Sep-18

Loop Instructions LOOP Loop through a sequence of instructions until CX=0 LOOPE/LOOPZ Loop through a sequence of instruction while ZF=1 and CX !=0 LOOPNE/LOOPNZ Loop through a sequence of instruction while ZF=0 and CX!=0. JCXZ Jump to specified address if CX=0. 8086 Instruction Set (continued...) 21-Sep-18

Flag Manipulation Instructions:
STC Set carry flag CLC Clear carry flag CMC Complement the status of carry flag STD Set direction flag CLD Clear direction flag STI Set interrupt enable flag (enable INTR) CLI Clear interrupt enable flag (disable INTR) 8086 Instruction Set (continued...) 21-Sep-18

Machine Control Instructions:
HLT Halt until interrupt or reset WAIT Wait until signal on the TEST pin is low LOCK An instruction prefix. Prevents another processor from taking the bus while the adjacent instruction executes NOP No action except fetch and decode 8086 Instruction Set (continued...) 21-Sep-18

Assembler Directives 21-Sep-18

Assembler Directives & Operators
Hints given to the assembler using predefined alphabetical strings to correctly understand the assembly language programs and prepare machine codes – called as ASSEBLER DIRECTIVES Hints given to the assembler to assign a particular constant with a label or Initialize particular memory locations or labels with constants - Called as Operators Operators perform arithmetic and logical tasks. Assembler Directives (continued...) 21-Sep-18

Assembler Directives used in
Microsoft Macro Assembler or Turbo assembler Directives 1.DB Define Byte 2. DW Define Word 3. DQ Define Quadword 4. DT Define Ten Bytes 5. END End of Program 6. ENDP End of Procedure 7. ENDS End of Segment 8. ASSUME Assume Logical Segment Name 9. SEGMENT Logical segment Assembler Directives (continued...) 21-Sep-18

Directives (continued….)
10. EQU Equate 11. EVEN Align on even memory address 12. EXTRN and PUBLIC External and Public 13. Local Local 14. Global Global 15. Group Group the related segments 16. Label Label 17. Length Byte length of a label 18. Name Logical name of a module 19. Org Origin 20. proc Procedure Assembler Directives (continued...) 21-Sep-18

Microsoft Macro Assembler or Turbo assembler Directives (continued….)
Operators used in Microsoft Macro Assembler or Turbo assembler Directives (continued….) 21. Far ptr Near pointer 22. Near ptr Far pointer Operators 1.Offset Offset of a label 2. Ptr Pointer 3. Seg Segment of a label 4. Short Short 5. ‘+ and -’ Addition and subtraction operators 6. Type Type Assembler Directives (continued...) 21-Sep-18

Assembler Directives (continued...)
1.DB DB directive is used to reserve bytes or bytes of memory location , with data type that may be a Constant Variable String etc Example - 1 PRICE DB 49h, 98h, 29h ; Directs assembler to - reserve an array of 3 bytes named as PRICE and initialize. Assembler Directives (continued...) 21-Sep-18

Example - 2 MESSAGE DB ‘GOOD MORNING’; Reserve an array of bytes equal to the number of characters in the string named as MESSAGE and initialize by the ASCII equivalent of these characters Example – 3 TEMP DB 100 DUP(?) ; Set 100 bytes of storage in memory and give it the name as TEMP, but leave the 100 bytes uninitialized. Program instructions will load values into these locations. DUP - Duplicates Assembler Directives (continued...) 21-Sep-18

2. DW DW directive is used to reserve words (16 bits) or words of memory location , with data type that may be a Constant Variable String etc Example - 1 WORDS DW 4987h, 1F98h, AB29h ; Directs assembler to reserve an array of 3 Words named as WORDS and initialize. Lower bytes stored in lower and upper bytes stored in higher addresses Assembler Directives (continued...) 21-Sep-18

Example - 2 STAR DW 5 DUP (1234H); Directs assembler to reserve an array of 5 Words named as STAR and initializes all the locations with Lower bytes stored in lower and upper bytes stored in higher addresses Assembler Directives (continued...) 21-Sep-18

Directives Directives
3. DQ DW directive is used to reserve 4 word bytes (i.e 4 x 8 bits) of memory location , with data type that may be a Constant Variable String etc; and may be initialized Directives 4. DT DW directive is used to reserve 10 bytes (i.e 10 x 8 bits) of memory location , with data type that may be a Constant ; Variable; String etc and may be initialized - Generally processed by numerical processors Assembler Directives (continued...) 21-Sep-18

5. END END of program directive marks the end of an assembly language program (ALP). Ignores all source lines available after this line Must be used as the last statement in the file 6. ENDP END of procedure directive marks the end of procedure. In an ALP - subroutines are called procedure. A procedure is an independent program module - PROCEDURE STAR - STAR ENDP Assembler Directives (continued...) 21-Sep-18

7. ENDS END of Segment directive - marks the end of logical segment. Logical segments are assigned with names using ASSUME directive Must be used the last statement in the segment along with segment name as prefix 8. ASSUME This directive is used to assign name for logical segments ASSUME directive is a MUST at the beginning of each ALP. 9. SEGMENT Marks the starting of logical segment Also assigns a name to the logical segment Assembler Directives (continued...) 21-Sep-18

Example ASSUME CS : CODE, DS : DATA DATA SEGMENT STAR DB 20 DUP (?) : DATA ENDS CODE SEGMENT CODE ENDS END Assembler Directives (continued...) 21-Sep-18

10. EQU EQU directive is used to assign a label with a value or symbol Used to reduce recurrence of numerical values or constants in ALP code One change in the EQU statement will give correct and modified code. When assembler comes across the label, it substitutes the numerical values Example CONST1 EQU H assigns constant 0510h with label CONST1 ADDITION EQU ADD assigns another label ADDITION with mnemonic ADD Assembler Directives (continued...) 21-Sep-18

11. EVEN Align on even memory address directive updates the location counter to next even address. - While starting the assembling process, the assembler initializes a location counter and updates it sequentially to the program variables; constants ; modules etc. as required. Example EVEN PROCEDURE ROOT : ROOT ENDP Assembler Directives (continued...) 21-Sep-18

12. EXTERN and PUBLIC EXTERN directive informs the assembler that the names / procedures / labels declared after this directive have already been defined in some other ALP module In the module where the names, procedures, labels actually appear must be declared PUBLIC MODULE1 SEGMENT PUBLIC FACTORIAL FAR MODULE1 ENDS MODULE2 SEGMENT EXTRN FACTORIAL FAR Example Assembler Directives (continued...) 21-Sep-18

13. LOCAL LOCAL directive informs the assembler that the labels / variables /constants / procedures declared after this directive are used ONLY by that particular module In some other module same labels / variables /constants / procedures can be used for different purposes. Single statement can be used to declare all labels / variables /constants / procedures Example LOCAL a, b, DATA, ARRAY, ROUTINE Assembler Directives (continued...) 21-Sep-18

14. GLOBAL LOCAL directive informs the assembler that the labels / variables /constants / procedures declared after this directive can be used by OTHER modules in the program Example ROUTINE PROC GLOBAL Procedure ROUTINE is declared as a global label Assembler Directives (continued...) 21-Sep-18

15. GROUP Forms logical groups of segments with similar purpose or types Assembler informs loader/linker to place group declared segments or operands must lie within 64KB memory segment Example PROGRAM GROUP CODE, DATA, STACK CODE, DATA, STACK segments lie within 64 KB which is named as PROGRAM Assembler Directives (continued...) 21-Sep-18

16. LABEL Used to assign a name to the current content of the location counter The type of the label must be specified (i.e) NEAR or FAR label, BYTE or WORD label Example After reserving 50 locations for DATAS, the next location will be assigned a label DATA-LAST and its type will be Byte and Far DATA SEGMENT DATAS DB 50H DUP (?) DATA-LAST LABEL BYTE FAR DATA ENDS Assembler Directives (continued...) 21-Sep-18

17. LENGTH Used to refer to the length of a data array or string Example MOV CX, LENGTH ARRAY Substitutes the length of the array ARRAY in bytes Directives 18. NAME Used to assign a name to an ALP module MULTI_PGM NAME : END Example Assembler Directives (continued...) 21-Sep-18

19. ORG Directs the assembler to start the memory allotment for the particular block or code from the declared address in the ORG statement Without ORG location counter is initialized to 0000 Example ORG 200H Initializes the location counter to the address 0200h instead of 0000h Assembler Directives (continued...) 21-Sep-18

20. PROC Marks the start of a named procedure NEAR / FAR specify the type of the procedure NEAR- called by the main program located within 64K of physical memory FAR – Called by the main program located at a more than 64K of physical memory Example RESULT PROC NEAR ROUTINE PROC FAR Procedure RESULT is placed in the same segment Procedure ROUTINE is placed in some other segment Assembler Directives (continued...) 21-Sep-18

21. FAR PTR Indicates the assembler that the label following FAR PTR is not within the same segment Address of label is of 32 bits (4 bytes) [2 bytes offset followed by 2 bytes segment address] Example JMP FAR PTR LABEL1 CALL FAR PTR ROUTINE Assembler Directives (continued...) 21-Sep-18

22. NEAR PTR Indicates the assembler that the label following FAR PTR is in the same segment Address of label is of 16 bits (2 bytes) [2 bytes offset only] Example JMP NEAR PTR LABEL1 CALL NEAR PTR ROUTINE Assembler Directives (continued...) 21-Sep-18

Operators 1. OFFSET OFFSET operator indicates the assembler to compute the16 bit displacement (offset) of the label and replace the string ‘OFFSET LABEL’ by the computed displacement Used with arrays, strings, labels and procedures to decide their offset in their default segments Example CODE SEGMENT MOV SI, OFFSET LIST CODE ENDS DATA SEGMENT LIST DB 10H DATA ENDS Assembler Directives (continued...) 21-Sep-18

Operators 2. PTR - PTR operator is used to declare the type of a label, variable or memory operand. - PTR operator is prefixed by BYTE or WORD Example MOV AL, BYTE PTR [SI] - Moves content of memory location addressed by SI to AL INC BYTE PTR [BX] - Increments byte content of memory location addressed by BX MOV BX, WORD PTR [2000H] - Moves 16 bit content of memory location 2000h to BX (i.e) [2000h] to BL, [2001h] to BH INC WORD PTR [2000H] - Increments word content of memory location 3000h and 3001h as a 16 bit number Assembler Directives (continued...) 21-Sep-18

Operators 3. SEG SEG operator is used to decide the segment address of the label, variable or procedure and substitutes the segment base address in place of ‘SEG’ label Example MOV AX, SEG ARRAY MOV DS, AX Moves the segment address of ARRAY in which it is appearing into the register AX and then into DS Assembler Directives (continued...) 21-Sep-18

Operators 4. SHORT SHORT operator indicates to the assembler that only one byte is required to code the displacement for a jump By specifying this way the assembler saves memory. Example JMP SHORT LABEL Operators 5. +, - Represents arithmetic addition and subtration Example MOV AL, [SI +2] MOV DX, [BX -5] MOV BX, [OFFSET LABEL +10H] Assembler Directives (continued...) 21-Sep-18

Operators 6. TYPE TYPE operator directs the assembler to decide the data type of the specified label and replace the ‘TYPE’ label by the decided data type. For byte type variable, the data type is 1; For word type variable, the data type is 2; For double word type, the data type is 4; Example MOV AX, TYPE STRING If STRING is a word array, then the value 0002h is moved in AX Assembler Directives (continued...) 21-Sep-18

Assembly Language Programming
21-Sep-18

Program Segment Structure
01/22/08 Program Segment Structure Data Segments Storage for variables Variable addresses are computed as offsets from start of this segment Code Segment contains executable instructions Stack Segment used to set aside storage for the stack Stack addresses are computed as offsets into this segment Segment directives .data .code .stack size Assembly Language Programming (continued...) 21-Sep-18

Assembly Language Programming (continued...)
01/22/08 Memory Models Model memory_model tiny : code+data <= 64K (.com program)‏ small : code<=64K, data<=64K, one of each medium : data<=64K, one data segment compact : code<=64K, one code segment large : multiple code and data segments huge : allows individual arrays to exceed 64K flat : no segments, 32-bit addresses, protected mode only (80386 and higher)‏ Assembly Language Programming (continued...) 21-Sep-18

Assembly Language Programming (continued...)
01/22/08 Program Skeleton Select a memory model Define the stack size Declare variables Write code organize into procedures Mark the end of the source file optionally, define the entry point .model small .stack 100H .data ;declarations .code main proc ;code main endp ;other procs end main Assembly Language Programming (continued...) 21-Sep-18

Assembly Language Program Example
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; ; This is an example program. It prints the ; ; character string "Hello World" to the DOS standard output ; ; using the DOS service interrupt, function ; hellostk SEGMENT BYTE STACK 'STACK' ;Define the stack segment DB 100h DUP(?) ;Set maximum stack size to 256 bytes (100h) hellostk ENDS hellodat SEGMENT BYTE 'DATA' ;Define the data segment dos_print EQU ;define a constant via EQU strng DB 'Hello World',13,10,'$' ;Define the character string hellodat ENDS hellocod SEGMENT BYTE 'CODE' ;Define the Code segment START: mov ax, SEG hellodat ;ax <-- data segment start address mov ds, ax ;ds <-- initialize data segment register mov ah, dos_print ;ah <-- 9 DOS 21h string function mov dx,OFFSET strng ;dx <-- beginning of string int 21h ;DOS service interrupt mov ax, 4c00h ;ax <-- 4c DOS 21h program halt function hellocod ENDS END START ; ‘END label’ defines program entry Assembly Language Programming (continued...) 21-Sep-18

Another Way to define Segments
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Use 'assume' directive to define segment types ; ; ; hellostk SEGMENT ;Define a segment DB 100h DUP(?) hellostk ENDS hellodat SEGMENT ;define a segment dos_print EQU ;define a constant strng DB 'Hello World',13,10,'$' ;Define the character string hellodat ENDS hellocod SEGMENT ;define a segment assume cs:hellocod, ds:hellodat, ss: hellostk START: mov ax, hellodat ;ax <-- data segment start address mov ds, ax ;ds <-- initialize data segment register mov ah, dos_print ;ah <-- 9 DOS 21h string function mov dx,OFFSET strng ;dx <-- beginning of string int 21h ;DOS service interrupt mov ax, 4c00h ;ax <-- 4c DOS 21h program halt function hellocod ENDS END START Assembly Language Programming (continued...) 21-Sep-18

Yet another way to define Segs
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Use .stack,.data,.code directives to define segment types ; ; ; .stack 100h ; reserve 256 bytes of stack space .data dos_print EQU ;define a constant strng DB 'Hello World',13,10,'$' ;Define the character string .code START: mov ax, SEG strng ;ax <-- data segment start address mov ds, ax ;ds <-- initialize data segment register mov ah, dos_print ;ah <-- 9 DOS 21h string function mov dx,OFFSET strng ;dx <-- beginning of string int 21h ;DOS service interrupt mov ax, 4c00h ;ax <-- 4c DOS 21h program halt function END START Assembly Language Programming (continued...) 21-Sep-18

Modular Programming 21-Sep-18

Modular Programming (continued...)
Reasons for breaking a program into small parts: Modules are easy to comprehend Different modules can be assigned to different programmers Debugging and testing done in orderly fashion Documentation – easily understood Modifications – localized Frequently used tasks can be programmed into modules that are stored in libraries and used by several programs. Modular Programming (continued...) 21-Sep-18

Assembler ; Linker and Relocator
21-Sep-18

Assembler; Linker; Relocator (continued...)
A Program that converts assembly language program into equivalent machine codes, which may further be converted to executable codes Assembler does the following in steps: Decides the address of each label Substitutes the values for each of the constants and variables Forms the machine code for mnemonics and data in the assembly language program During the above process, assembler finds out syntax errors, but logical errors are not found For completing these tasks assembler needs hints from the programmer ; like - Storage required for a particular constant or a variable, Logical names of the segment, Types of the different routines and modules, End of files, etc. Assembler; Linker; Relocator (continued...) 21-Sep-18

An assembler translates the assembly language program into machine language program Assembly language program à source codes Machine language program à object codes Assembler converts Source code into Object code Linker converts Object code into executable code Assembler; Linker; Relocator (continued...) 21-Sep-18

Assembler works in passes: In the first pass, it determines the displacement of the named data items, the offset of labels etc. and puts this information to in a symbol table. In the second pass, it produces the binary codes for each instructions and inserts the offsets etc. that it calculated in the first pass. It generates two files namely object file (.OBJ) and assembler list file (.LST). Assembler; Linker; Relocator (continued...) 21-Sep-18

Linker is a program used to join several object files into one large object file. While writing large programs it is good to divide them into modules so that each modules can be written, tested, debugged independently and then use linker to combine the modules to form the actual program. It produces two files - link file which contains the binary codes of all the combined modules and a link map file which contains the address information about the linked files. Assembler; Linker; Relocator (continued...) 21-Sep-18

Locators A locator is the program used to assign the specific addresses of where the segments of object code are to be loaded in to main memory. Examples include EXE2BIN which comes with the IBM PC DOS. Converts .exe to .bin files which has physical addresses Assembler; Linker; Relocator (continued...) 21-Sep-18

Assembler; Linker; Relocator
Debugger A debugger is the program which allows to load the object code program in to system memory. It allows to look at the contents of the registers and memory locations after a program is run. It also allows to set breakpoints at any points in the program. It allows to find the source of the problem into the program. There are lots of debuggers available like Borland Turbo Debugger, Microsoft’s Code view debugger etc. Assembler; Linker; Relocator 21-Sep-18

Stacks 21-Sep-18

Stack A stack is a Last-Input-First-Output (LIFO) read/write memory (i.e) data segment It is a top-down data structure, whose elements are accessed using SS and SP registers Stack pointer is decremented by 2 while ‘pushing into’ the stack Stack pointer is incremented by 2 while ‘poping off’ the stack Stacks (continued . . .) 21-Sep-18

Stack Stack is used to: Store return addresses whenever a procedure is called Save contents of registers / register status of the processor while calling a procedure Hold data or addresses that will be acted upon by the procedure Stacks (continued . . .) 21-Sep-18

Initializing Stack Memory
ASSUME CS:CODE, SS: STACK STACK SEGMENT STACKDATA DW 40 DUP(0) STACKTOP LABEL WORD STACK ENDS CODE SEGMENT MOV AX, STACK MOV SS, AX ;initialize stack Seg. Regr. LEA SP, STACKTOP ;initialize stack pointer ;program instructions CODE ENDS END Stacks (continued . . .) 21-Sep-18

Stack Instructions PUSH and POP
PUSH always transfers 2 bytes of data to the stack. Syntax : PUSH <src>; <src> could be any 2 byte Register or Memory location or Immediate value When PUSH is executed, the most significant byte is stored in stack segment pointed to by SP-1, and the least significant byte to location pointed by SP-2. Stacks (continued . . .) 21-Sep-18

Example -1 : Let SS=2000H; SP=100H, AX=31F2H,
Do not click the mouse to see the full animation Example -1 : Let SS=2000H; SP=100H, AX=31F2H, PUSH AX 31 F2 AX F2 200FD 31 200FE 20100 SP=00FD SP=0100 SP=00FE SS=2000H Stacks (continued . . .) 21-Sep-18

Example - 2 Assume SS=2000H, SP=100H, AX=31F2H, BX=413AH, CX=FFFFH. Show the changes in the stack after executing the following instructions: PUSH AX PUSH BX POP CX POP AX Stacks (continued . . .) 21-Sep-18

SS=2000H, SP=100H, AX=31F2H, BX=413AH, CX=FFFFH. PUSH AX PUSH BX
CH CL 41 3A BH BL 41 3A PUSH AX PUSH BX POP CX POP AX 3A 200FC 31 AH AL F2 41 200FD F2 200FE 31 200FF XX 20100 SP=0100h SP=00FEh SP=00FCh SS=2000H Stacks (continued . . .) 21-Sep-18

Example 11: Write an ALP to reverse string using stack operations.
STR DB ‘HELLO’, 00H ; REVSTR DB 256 DUP(?) MOV CX, 0000H ;count number of bytes LEA SI, STR; LEA DI, REVSTR NEXT-CHAR: MOV AL, [SI] CMP AL, 00 JE NEXT PUSH AX ; only care about AL INC CX; JMP NEXT-CHAR NEXT: CMP CX, 0000H; check if cx =0 or the string is null JE DONE-REV Stacks (continued . . .) 21-Sep-18

DONE-REV: MOV [DI],00; to terminate with null
POP AX MOV [DI],AL INC DI DEC CX; JMP NEXT DONE-REV: MOV [DI],00; to terminate with null Stacks (continued . . .) 21-Sep-18

Procedures 21-Sep-18

Procedures (continued . . .)
A procedure is a sequence of instructions written to perform a particular task Replacing a set of frequently used instructions by a procedure saves program memory space A CALL instruction in the main program causes to the execute the set of instructions contained in a procedure A RET instruction at the end of procedure returns execution to the next instruction in the main program Procedures (continued . . .) 21-Sep-18

PROCEDURE INSTRUCTIONS
MAINLINE OR CALLING PROGRAM CALL PROCEDURE INSTRUCTIONS RET NEXT MAINLINE INSTRUCTIONS Procedures (continued . . .) 21-Sep-18

21-Sep-18

Advantages of using Procedures
Saves program memory space Problem can be divided into small modules Allows reusability of code Disadvantage Takes more time to execute Procedures (continued . . .) 21-Sep-18

8086 CALL Instruction 8086 performs the following operations when a CALL instruction is executed Stores the address of the instruction after the CALL instruction on to the stack Changes the contents of Instruction Pointer (IP) register and in some cases the Code Segment (CS) register to contain and point to the starting address of the procedure Procedures (continued . . .) 21-Sep-18

Types of CALL Instruction
Direct Near (within segment) CALL Direct Far (inter segment) CALL Indirect Near (within segment) CALL Indirect Far (within segment) CALL Procedures (continued . . .) 21-Sep-18

8086 RET Instruction When 8086 does a NEAR CALL, it pushes the instruction pointer (IP) value (for the instruction after CALL) on to the stack A RET instruction at the end of a procedure pops this value back to instruction pointer (IP) to return to the calling program (main program). Procedures (continued . . .) 21-Sep-18

Macros 21-Sep-18

Macros A macro is the repeatedly appearing group of instructions, that is given a name at the start of the program. A macro can be defined anywhere in a program using the directives MACRO and ENDM Defining a Macro: name MACRO [optional arguments] statements.. statements.. ENDM Macros (continued . . .) 21-Sep-18

Macro name can be used in the actual program
Every occurrence of the macro name (apart from the definition) is replaced by the statements in the macro definition. Macros (continued . . .) 21-Sep-18

Macros Advantages Repeated small group of instructions replaced by one macro Errors in macros are fixed only once, in the definition Duplication of effort is reduced Programming is made easier and less error prone Generally quicker in execution than subroutines Disadvantages In large programs, macros produce larger code size than procedures Macros (continued . . .) 21-Sep-18

Comparison of Macros and Procedures
Advantage of using procedures is that the machine codes for the group of instruction in the procedures needs to be loaded into main memory only once. Disadvantage using the procedures is the need for the stack. Advantage of using macro is that it avoids the overhead time involved in calling and returning from a procedures. Disadvantage is that macros make the program occupy more memory than using a procedure. Macros (continued . . .) 21-Sep-18

Defining and calling a Macro without parameters
Example: To display the message MSG on CRT DISPLAY MACRO Mov AX, SEG Msg Mov DS, AX Mov DX, OFFSET Msg Mov AH, 09h INT 21h ENDM Macros (continued . . .) 21-Sep-18

Defining and calling a Macro with parameters
Example: To display two different messages MSG1 and MSG2 on the CRT DISPLAY MACRO MSG Mov AX, SEG Msg Mov DS, AX Mov DX, OFFSET Msg Mov AH, 09h INT 21h ENDM The parameter MSG can be replaced by MSG1 and MSG2 while calling the macro. : DISPLAY MSG1 DISPLAY MSG2 MSG1 DB OAH, 0DH, “Program terminated NORMALLY”,0AH,ODH,“$” MSG2 DB OAH, 0DH, “Retry, Abort, Fail”,0AH,ODH,“$” Macros (continued . . .) 21-Sep-18

Interrupts and Interrupt Service Routines
21-Sep-18

Interrupts and ISR (continued . . .)
What is an interrupt? Capability to suspend the execution of running program and execution of another program to fulfill specific requirement upon request After finishing the second program, automatically return to the first program and start execution from where it was left Interrupts and ISR (continued . . .) 21-Sep-18

Why interrupt capability is necessary?
To understand this - review of how µP/µC communicate with the outside world must be understood. Interrupts and ISR (continued . . .) 21-Sep-18

Basic block diagram of a µC
µP MEMORY I/O DEVICES BUS Interrupts and ISR (continued . . .) 21-Sep-18

First type of communication - Dedicated I/O
BUS µP I/O DEVICE 1 Single I/O device Interrupts and ISR (continued . . .) 21-Sep-18

Second type of communication - POLLED I/O or PROGRAMMED I/O
Device-1 Device-n BUS ...... You? Disadvantage: Not fast enough Wastes too much microprocessor time Interrupts and ISR (continued . . .) 21-Sep-18

Third type of communication - Interrupted I/O
Device-1 Device-n BUS ...... Interrupts are useful when I/O devices are slow Interrupts and ISR (continued . . .) 21-Sep-18

Most microprocessors allow normal program execution to be interrupted by some external signal or by a special instruction in the program. In response to an interrupt, the microprocessor stops executing its current program and calls a procedure which “services” the interrupt. A special instruction --- IRET --- at the end of interrupt-service procedure returns execution to the interrupted main program. Interrupts and ISR (continued . . .) 21-Sep-18

Sources of 8086 interrupts 8086 interrupts can be classified into two types: 1) Predefined interrupt Some error condition produced by execution of an instruction, e.g., trying to divide some number by zero. (Interrupt due to exceptions) 2) User defined interrupt i) Hardware interrupt An external signal applied to NMI, INTR pins ii) Software interrupt Execution of interrupt instruction INT Interrupts and ISR (continued . . .) 21-Sep-18

NMI (Non Maskable Interrupt): Any interrupt request at NMI input pin cannot be masked or disabled by any means; type is implicit INTR: This hardware interrupt can be masked using Interrupt Flag (IF); 256 Types (00h to FFh); to handle more than one interrupts that occur at a time, Programmable Interrupt Controller is required. INT: This is a software interrupt; the type is specified in the instruction At the end of each instruction cycle, 8086 checks if any interrupt service has been requested. If yes, then 8086 responds to the interrupt by stepping through the following series of actions: Interrupts and ISR (continued . . .) 21-Sep-18

8086 decrements SP by 2 and pushes flag register content into the stack. 8086 disables INTR input by clearing IF flag in flag register The TF (trap) flag in flag register is Reset Decrements SP again by 2 and pushes current CS content into the stack. Decrements SP again by 2 and pushes current IP content into the stack. Does an indirect far jump to the start of the procedure written to respond to the interrupt. Interrupts and ISR (continued . . .) 21-Sep-18

1. Push FLAGS 2. Clear IF 3. Clear TF 4. Push CS 5. Push IP 6. Fetch ISR address Interrupt Service Routine (ISR) main Program PUSH registers ... .... POP registers IRET POP IP POP CS POP FLAGS Interrupts and ISR (continued . . .) 21-Sep-18

How does 8086 get to Interrupt Service Routine?
8086 loads its CS and IP registers with the address of ISR. So, the next instruction to be executed is the first instruction of ISR Interrupts and ISR (continued . . .) 21-Sep-18

How does 8086 get the address of Interrupt Service Routine (ISR)?
In an 8086 system, each “interrupter” (external and internal ) has an id#; 8086 treats this id# as interrupt-type# After receiving INTR signal, 8086 sends an INTA signal After receiving INTA signal, interrupter releases it’s id#, (i.e.) type# of the interrupt. 8086 multiplies this id# or type# by 4 to produce the desired address of the location in the Interrupt Vector Table (IVT), where ISR address is stored. 8086 reads 4 consecutive bytes starting from this location to get the starting address of ISR First 2 bytes are loaded in to IP Second 2 bytes to CS Interrupts and ISR (continued . . .) 21-Sep-18

Interrupt Vector Table (IVT)
In an 8086 system, the first 1Kbytes (1024 bytes) of memory, from to 003FF, is set aside as a Table for storing the starting addresses of interrupt service routines. Since 4 bytes are required to store CS and IP values for each ISR, the Table can hold the starting addresses for up to 256 ISRs. The starting address of an ISR is often called the interrupt vector or the interrupt pointer. So the Table is referred to as interrupt-vector table or interrupt-pointer table. Interrupts and ISR (continued . . .) 21-Sep-18

The 256 interrupt vectors are arranged in the table in memory as follows in the next slide. Note : The IP value is put in as the lower word of the vector and CS as higher word of the vector Each double word interrupt vector is identified by a number from 0 to 255 (00h to FFh) INTEL calls this number as the TYPE of the interrupt Interrupts and ISR (continued . . .) 21-Sep-18

... AVAILABLE 3FFH TYPE 255 FOR USER (224) 080H TYPE 32 TYPE 31
RESERVED (27) 014H TYPE 5 TYPE 4 010H Overflow INTO TYPE 3 Predefined/ 00CH One Byte INT Dedicated/Internal TYPE 2 Interrupts Pointers 008H NON-MASKABLE (5) TYPE 1 004H SINGLE STEP CS Base Address TYPE 0 IP Offset 000H DIVIDE ERROR

What happens if two or more interrupts occur at the same time?
Higher priority interrupts will be served first Interrupts and ISR (continued . . .) 21-Sep-18

Priorities of 8086 interrupts
Interrupt Type Priority Divide Error, INT n, INT0 NMI INTR Single Step HIGHEST LOWEST Interrupts and ISR (continued . . .) 21-Sep-18

Differences between CALL and INT:
S.No CALL Instruction INTn instruction 1 Upon the execution ,the control will jump to any one of the 1 MB of memory locations . Upon execution the control will jump to a fixed location in the vector table. 2 The user can insert in the sequence of instructions of a program Can occur at any time activated by hardware 3 Once initiated it cannot be masked Can be masked 4 When initiated ,it stores the CS:IP of the next instruction on the stack When initiated ,it stores the CS:IP of the next instruction and also the flag register on the stack. 5 The last instruction of the subroutine will be RET The last instruction of the ISS will be IRET Interrupts and ISR (continued . . .) 21-Sep-18

The Interrupt sequence of 8086 Microprocessor:
External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal interrupt occurs. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt Acknowledge (INTA) to hardware interface. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware interface. The contents of the flag registers are pushed onto the stack. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-step feature. Interrupts and ISR (continued . . .) 21-Sep-18

The contents of the code segment register (CS) are pushed onto the Stack. The contents of the instruction pointer (IP) are pushed onto the Stack. The ISR address from the interrupt vector table (IVT) is fetched, by finding (4 x N). Where N is the ‘type’ of interrupt. In the IVT, the first 2 bytes starting from 4 x N is placed into the IP and the next 2 bytes from (4xN +2) is placed into the CS, so that the next instruction is executed from the ISR addressed by the interrupt vector. While returning from the ISR by the Interrupt Return (IRET) instruction, the IP, CS and Flag (PSW) registers are popped from the stack and returns to the state prior to the interrupt. Interrupts and ISR (continued . . .) 21-Sep-18

Byte and String Programming
21-Sep-18

Strings A string is a series of bytes or words stored in successive memory locations 8086 can perform the following operations on strings Moving a string from one place in memory to another Compare two strings Search a string for a specified character Strings (continued . . .) 21-Sep-18

String Instructions B stands for byte, and W stands for word
Strings (continued . . .) 21-Sep-18

Moving a String MOVSB/ MOVSW Instruction
Copies a byte or word from a location in the data segment (DS) to the location in the extra segment (ES) Offset of source in data segment must be in SI register Offset of destination in extra segment must be in DI register For multiple byte/word moves the count is stored in CX register Strings (continued . . .) 21-Sep-18

Role of Direction Flag in Moving a String
DF = 0 SI & DI will be incremented by 1 or 2 after every byte or word is moved DF = 1 SI & DI will be decremented by 1or 2 after every byte or word is moved Strings (continued . . .) 21-Sep-18

A program to copy a string of bytes from one location in memory to another
Strings (continued . . .) 21-Sep-18

LEA, CLD & REP Instructions for moving a string
LEA (Load Effective Address) this instruction determines the offset of the variable or memory location named as the source and puts it in the specified 16-bit register CLD (Clear Direction Flag) REP (Repeat) A prefix written before one of the string instruction Causes string instruction to be repeated until CX=0 Strings (continued . . .) 21-Sep-18

DATA SEGMENT MSG1 DB ‘TIME FOR A NEW HOME’ MSG2 DB ‘JUMP OVER TO MSG3’ MSG3 DB 23 DUP(0) DATA ENDS CODE SEGMENT ASSUME CS:CODE, DS: DATA, ES: DATA START: MOV AX, DATA MOV DS, AX ;initialize data segment register MOV ES, AX ;initialize extra segment register LEA SI, MSG1 ;point SI at source string LEA DI, MSG3 ;point DI at destination string MOV CX, 19 ;use CX register as counter CLD ;clear direction flag, so counter decrements REP MOVSB ;move string bytes until all moved CODE ENDS Strings (continued . . .) 21-Sep-18

LODSB and LODSW For LODSB this is how it is done AL = DS:[SI]
if D = 0 then SI = SI + 1 else SI = SI – 1 And LODSW is the same except that SI by 2 Strings (continued . . .) 21-Sep-18

STOSB and STOSW For STOSB Store byte in AL into ES:[DI]. Update DI.
For STOSW Store word in AX into ES:[DI]. Update DI. How STOSB executes? ES:[DI] = AL if DF = 0 then DI = DI + 1 Else DI = DI - 1 And STOSW executes the same as STOSB but DI is incremented or decremented by 2 Strings (continued . . .) 21-Sep-18

INTERRUPTS ,DOS CALLS INPUT /OUTPUT SERVICES
On the machines based on Intel 80xx series (8086,8088 etc.), running on DOS, the input/output is carried out in the form of services provided by the hardware and the operating systems. They are called as ROM-BIOS, and DOS services respectively, and are in the form of interrupts. Interrupts An interrupt occurs when any currently executing program is interrupted. Interrupts are generated for a variety of reasons, usually related to the services related to the external devices connected to the machine, example: keyboard, printer, monitor, etc. There can be other reasons for the interrupts, like an error condition, trap etc.

INT 8086 recognizes two kinds of interrupts, hardware interrupts and software interrupts. Hardware interrupts are generated when the peripheral, connected to the CPU requests for some service. A software interrupt is a call to a subroutine located in the operating system, usually the input-output routine. INT (interrupt) instruction is used within application programs to request the services of DOS, or ROM-BIOS. The INT instruction calls an operating system subroutine, identified by a number, in the range 0 - FFh. The syntax is INT number The CPU processes an interrupt instruction, using the interrupt vector table (IVT). It is situated in the first 1K bytes of memory, and has a total of 256 entries, each of 4bytes. The entry in the interrupt vector table, is identified by the number, given in the interrupt instruction, and in turn points to an operating system subroutine. The actual address in this table varies from machine to machine.

PROCESSING AN INTERRUPT

STEPS 1. The number following the INT mnemonic tells the CPU which entry to locate in the interrupt vector table. The address of the entry can be found by multiplying the number by 4. Example: the subroutine corresponding to INT 10h will be placed at address a 40h , while for INT 3h will be placed at OCh. 2. The CPU jumps to the address stored in the interrupt vector table. The actual routine for servicing the INT 10h, is placed at this address. 3. The CPU loads the CS register and the IP register, with this new address in the IVT, and transfers the control to that address, just like a far CALL, 4. IRET (interrupt return) causes the program to resume execution at the next instruction in the calling program.

DOS FUNCTION CALLS INT 21 H is called a DOS function call. There are some 100 different functions supported by this interrupt, identified by a function number placed in the AH register, prior to calling INT.

INT 21 FUNCTION 01 H Reads the character from the keyboard, and echoes the character on the monitor. If no character is ready, waits until one is available. Calls with: AH = 01 Returns: AL = 8 bit data input

INT 21 FUNCTION 01 H Example: Read one character from the keyboard into register AL, with echo, and store it in the variable VAR 1 PGM: MOV AH,01H INT 21 H MOV VAR1,AL VAR1 DB 0

INT 21 FUNCTION 02 H Outputs the character on the monitor
Calls with: AH = 02 DL = 8 bit-data (usually ASCII, if you want it printed on the screen) Returns: nothing Example: transmit the character '*' on the screen MOV AH, 02 MOV DL, '*' INT 21h

INT 21 FUNCTION 08 H Reads a character from the input device, without echoing it on the output device. Rest all other things are same as that of function 01

INT 21 FUNCTION 09 H Output a string on the standard output device.
A string must be terminated by a '$' character, which is not transmitted. Any other code, including the control codes, like, newline, tab etc., can be embedded in the string Calls with: AH = 09 DS:DX = segment:offset of string Returns: nothing

INT 21 FUNCTION 09 H Example: CR EQU ODh ; code for carriage return
LF EQU OAh ; code for line feed DATA SEGMENT STR DB 'Hello world!',CR,LF,'$' DATA ENDS CODE SEGMENT MOV AH,09 MOV DX, -DATA MOV DS,DX MOV DX, OFFSET -STR INT 21h

INT 21 FUNCTION 0A H Reads a character string of up to 255 characters from the console and stores it in a buffer. Backspace key may be used to erase the characters, ENTER is used to terminate the string. All the characters are echoed on the console. Before the function is called, a buffer is initialized of length, equal to the maximum length of the string required plus two. The first byte of the buffer specifies the maximum number of bytes it can hold, including the carriage return (initialized by the user), the second byte is supplied by MS-DOS to signal the number of characters actually read, excluding the carriage return. Call with: AH = OA h DS:DX = segment: offset of buffer Returns: nothing

Example: DATA SEGMENT BUFF DB 81 ; max length of string,; including CR, 81 characters DB 0 ; actual length of string used DB 81 DUP(0) DATA ENDS

EXAMPLE CODE SEGMENT MOV AH,0A H MOV DX,DATA MOV DS,DX
MOV DX,OFFSET BUFF INT 21 H CODE ENDS

INT 21 FUNCTION 4C H Terminate with a return code. Performs a final exit to DOS, passing back a return code. MS-DOS closes all the previously opened files, and updates the directory. Calls with: AH = 4Ch AL = return code Returns: nothing Example: return to DOS normally MOV AH,4Ch MOV AL, 00 INT 21h

End of Unit-1 Introduction to 8086 (continued.....) 21-Sep-18

EC6504 Microprocessor and Microcontrollers

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