MOTOROLA 68HC11 MICROCONTROLLERS

MOTOROLA 68HC11 MICROCONTROLLERS
UNIT-IV MOTOROLA 68HC11 MICROCONTROLLERS SRI VENKATEWARA COLLEGE OF ENGINEERING

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UNIT IV - MOTOROLA 68HC11 MICROCONTROLLERS Instruction set addressing modes – operating modes- Interrupt system- RTC Serial Communication Interface – A/D Converter PWM and UART. SRI VENKATEWARA COLLEGE OF ENGINEERING

INTRODUCTION TO MC 68HC11 MICROCONTROLLER
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Block Diagram Of MC68HC11 SRI VENKATEWARA COLLEGE OF ENGINEERING

INTRODUCTION Motorola Inc ,one of the pioneers in microcontroller manufacturing has introduced this 8-bit microcontroller M68HC11 in the year and it is descended from the Motorola 6800 microprocessor. Now it is produced by Freescale Semiconductors. It is a CISC microcontroller , optimized for low power consumption and high-performance operation. SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd.. The 68HC11 chip has built-in EEPROM/ROM, RAM, digital I/O, timers, A/D converter, PWM (Pulse width modulator) generator, and synchronous and asynchronous communications channels. SRI VENKATEWARA COLLEGE OF ENGINEERING

SALIENT FEATURES The HCMOS MC68HC11 is an advanced 8-bit MCU with numerous on-chip peripheral capabilities. Up to 10MIPS Throughput at 10MHz 256 Bytes of RAM , 512 Bytes of In-System Programmable EEPROM. Eight channel 8-bit Analog to Digital Convertor One serial peripheral interface, with a speed up to 1M (baud rate) SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd… The MC68HC11 is available in two packages . One is 48-pin dual inline package (DIP) and the other is the 52 Pin Plastic Leaded Chip Carrier(PLCC) known as Lead quad pack. In the 48 pin DIP package 38 pins are available for I/O functions.(34 I/O lines+ 2 interrupt lines + 2 control lines). Similarly in a 52 PLCC pack 42 pins are meant for different I/O functions, and the remaining are used for interrupt and other signals. Dual in-line Package (DIP) Plastic Leaded Chip Carrier (PLCC) SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd.. MC68HC11 has one universal Asynchronous Serial Communications Interface (UART) Six powerful addressing modes (Immediate, Direct, Extended, Indexed, Inherent and Relative) Power saving STOP and WAIT modes It is based on HCMOS Technology and has a common internal bus for the address and data of 8-bits. It has an MCU clock whose frequency can be reduced to zero. As the MCU is completely MOSFET based the power dissipation is negligible in stop or wait states. So, this is optimized for low power consumption and high performance operation. SRI VENKATEWARA COLLEGE OF ENGINEERING

CPU FEATURES An 8MHz XTAL(external clock) with 2 MHz clock related operations. A 16-bit program counter that loads a powerup value from a reset vector address 0xFFFE – 0xFFFF Two 8- bit Accumulators A and B work as general purpose registers. They can be concatenated as a 16-bit double accumulator [D]. Two 16-bit Index registers Ix and Iy can be used as pointers to memory locations and hold the 16 bit addresses of memory locations . One 16 –bit stack pointer ,which decreases by 1 after the push of each byte. Two external interrupts IRQ ,XIRQ .One of this can be configured as non-maskable external interrupts. Although this is an 8-bit processor ,it has some 16-bit instructions.(ADD,Sub,shift and rotate) SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Registers The MC68HC11 microcontroller has a rich set of registers and they are classified into two categories : CPU registers and I/O registers. REGISTER ORGANISATION CPU registers SRI VENKATEWARA COLLEGE OF ENGINEERING

Program Counter(PC): It is a 16-bit register which stores the address of the next instruction to be executed. The 68HC11 fetches the instruction one byte at a time and increments the PC by 1 after fetching each instruction byte. After the execution of an instruction the PC is incremented by the number of bytes of the executed instruction. SRI VENKATEWARA COLLEGE OF ENGINEERING

Condition Code Register (CCR)
This is an 8-bit register used to keep track of the program execution status , control the execution of conditional branch instructions and enable/disable the interrupt handling . This register contains five status indicators, two interrupt masking bits, and a STOP disable bit. The register is named for the five status bits since that is the major use of the register. SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd. These status flags reflect the results of arithmetic and other operations of the CPU as it performs instructions. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag, which is used only for BCD arithmetic operations is only affected by the add accumulators A and B (ABA), ADD, and add with carry (ADC) addition instructions SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd.. The N bit reflects the state of the most significant bit (MSB) of a result. For two’s complement, a number is negative when the MSB is set and positive when the MSB is 0. The Z bit is set when all bits of the result are 0s. Compare instructions do an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags. SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd… The C bit is normally used to indicate if a carry from an addition or a borrow has occurred as a result of a subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. The STOP disable (S) bit is used to allow or disallow the STOP instruction. Some users consider the STOP instruction dangerous because it causes the oscillator to stop; however, the user can set the S bit in the CCR to disallow the STOP instruction. If the STOP instruction is encountered by the CPU while the S bit is set, it will be treated like a no-operation (NOP) instruction, and processing continues to the next instruction. SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd.. The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. After any reset, the I bit is set by default and can be cleared only by a software instruction. When any interrupt occurs, the I bit is automatically set after the registers are stacked but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. The XIRQ mask (X bit) is used to disable interrupts from the XIRQ pin. After any reset, X is set by default and can be cleared only by a software instruction SRI VENKATEWARA COLLEGE OF ENGINEERING

Parallel I/O PORTS There are 5 on chip I/O ports. They are Port A , Port B , Port C, Port D and Port E Port A (8 bits) 1 bidirectional pin, 4 output pins, 3 input pins , Also used for timer Port B (8 bits) 8 output pins, Also used as address in expanded mode SRI VENKATEWARA COLLEGE OF ENGINEERING

Contd.. Port C (8 bits) 8 bidirectional pins also used as data/address in expanded mode. Port D (6 bits) 6 bidirectional pins (controlled by direction register), Also used for asynchronous (SCI) and synchronous serial (SPI) I/O Port E (8 bits) 8 input pins , Also used for A/D converter The direction of the pins are controlled by the data direction register’s (DDR(A-E)) in the pulse accumulator control (PACTL) SRI VENKATEWARA COLLEGE OF ENGINEERING

Features of I/O Ports SRI VENKATEWARA COLLEGE OF ENGINEERING

The MC68HC11 has 21 independent interrupts . In this,6 are non- maskable and 15 are maskable . The three high priority interrupts are RESET , HIRQ and IRQ . SRI VENKATEWARA COLLEGE OF ENGINEERING

TIMERS The MC68H11 has one 16-bit free-running 16-bit counter with a 4-stage programmable pre-scaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record (latch) the time when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals or for timing software delays. SRI VENKATEWARA COLLEGE OF ENGINEERING

SELF PROTECTION All pins of M68HC11 have internal inherent diode clamps to Vss .This MCU has certain special internal circuit arrangements such that the MCU can operate at VDD 7 volts with out damage . The watch dog timer will always provide protection from any malfunction. The watch dog timer also provides self protection to the MCU from damage. SRI VENKATEWARA COLLEGE OF ENGINEERING

OPERATING MODES The 68HC11 can operate in one of the four modes: Single-chip mode: uses internal memory for program & data. Expanded mode :allows for use of external memory. Bootstrap mode: used to load programs into RAM. Test mode : used by Motorola to test the chip operation SRI VENKATEWARA COLLEGE OF ENGINEERING

Single chip (MODA=0, MODB=1)
i. No external address and data bus functions CPU can only access on-chip memory ii. Ports B and C are general purpose parallel I/O iii. All software needed to control MCU must be in internal memory iv. On reset, execution begins at address #E000

Expanded multiplexed (MODA=MODB=1)
i. External memory and peripheral devices can be accessed by time-multiplexed address-data bus ii. Port B used for high byte of address (output) iii. Port C provides low byte of address (output) and 8- bit data (bi-directional) iv. External address latch is required v. Execution begins at address #E000

Bootstrap (MODA=MODB=0)
i. On power up or reset, the program in the bootstrap ROM is executed ii. CPU waits for a 256-byte program segment to be downloaded through the serial link and stored starting at address #0000 iii. Execution then begins at address $0000 iv. Permits wide variety of programs to be downloaded

Test Mode (MODA=1, MODB=0)
i. Primarily used to test the chip by the manufacturer ii. Overrides some automatic protection mechanisms

HC11 Addressing Modes Instructions all need operands (source, destination) Operands may be in accumulators, memory, or the instruction itself Addressing modes determine how to find the operands Operands may be in decimal (base-10) or hexadecimal (base-16) Unannotated numbers are in decimal Numbers preceded with ‘$’ are in hex $32, $A2, $54B3 Useful when the number is conceptually in binary Memory addresses are traditionally in hex

Addressing Mode Inherent Immediate Direct, Extended Indexed Relative

Inherent The simplest addressing mode is Inherent Mode
Operands are accumulators specified by the instruction opcode ABA ;add accumulator B to accumulator A (result goes in A) INCB ;increment acc. B by one LSRD ;logical shift right acc. D (by one)

Immediate Immediate addressing specifies a constant value for an operand The ‘#’ indicates immediate data. ‘$’ means the data is in hexadecimal Immediate, decimal LDAA #00 ;Load Acc. A with the value 0010 LDAB #$C2 ;Load Acc. B with C216 (19410) LDY #$123A ;Load 123A16 (466610) into index Y Immediate, hex Be careful not to write values that are too large 255 ($FF) is the max for A and B, ($FFFF) for others

Memory Addressing Direct mode specifies a memory location as an operand We usually use hex for addresses LDAA $ ;loads memory[0016] to acc. A LDAB 21 ;loads memory[2110] into acc. B LDY $1C ;loads value from mem[1C16] into ;upper 8 bits of Y and from ;mem[1D16] into lower 8 bits of Y Direct mode can only use 1-byte addresses (locations 0-255) LDAA 314 ;not direct mode (address > 255) Extended mode allows 2-byte addresses (up to 65535) LDAA $32A2 ;loads memory[$32A2] into acc. A Extended mode takes one more cycle than direct mode to execute

Using an Index Indexed mode determines the address by adding a constant offset to the specified index register LDAA $20,X ;loads mem[$20+X] into acc. A If register X has the value $D000, then this reads memory location $D020 ($D000+$20) and puts it into acc. A Indexed mode can only be used with the index registers X and Y Indexed mode is useful for structures and arrays Structures: Use the index register to hold a pointer to the start of the struct, use the offset to specify the field in it Arrays: Use the offset for the base of the array, compute the distance to the desired item and put it in an index register

Addressing Mode Summary
Inherent For register-to-register operations - e.g. INCA Immediate For constants (any number that doesn’t come from memory or an accumulator) – e.g. LDAA #13 Direct, Extended To access a specific memory location e.g. LDAA $06 Indexed To access a memory location that depends on a computed value – e.g. LDAA $04,Y Relative Used only with branching

Motorola 68HC11 Instructions
68HC11 Instructions have variable lengths Careful coding can keep applications small and able to fit in the EPROM We don’t have to worry about this if we’re using expansion Mode. The opcode is always 1 byte an additional 0-3 bytes specify the data to work with. SRI VENKATEWARA COLLEGE OF ENGINEERING

Motorola 68HC11 Instruction Set
Accumulator and Memory Instructions Stack and Index Register Instructions Condition Code Register Instructions Program Control Instructions SRI VENKATEWARA COLLEGE OF ENGINEERING

Accumulator and Memory Instructions
HC11 Instructions Accumulator and Memory Instructions Can be broken up into these 6 general types: Loads, stores, and transfers Arithmetic operations Multiply and divide Logical operations Data testing and bit manipulation Shifts and rotates SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions Almost all MCU activities involve transferring data from memories or peripherals into the CPU or transferring results from the CPU into memory or I/O devices. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions This group of instructions supports arithmetic operations on a variety of operands; 8- and 16-bit operations are supported directly and can easily be extended to support multiple-word operands. Twos-complement (signed) and binary (unsigned) operations are supported directly. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions Compare instructions perform a subtract within the CPU to update the condition code bits without altering either operand. Although test instructions are provided, they are seldom needed since almost all other operations automatically update the condition code bits. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions One multiply and two divide instructions are provided. The 8-bit by 8-bit multiply produces a 16-bit result. The integer divide (IDIV) performs a 16-bit by 16-bit divide, producing a 16-bit result and a 16-bit remainder. The fractional divide (FDIV) divides a 16-bit numerator by a larger 16-bit denominator, producing a 16-bit result (a binary weighted fraction between 0 and ) and a 16-bit remainder. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions This group of instructions is used to perform the Boolean logical operations AND, inclusive OR, exclusive OR, and one’s complement. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions This group of instructions is used to operate on operands as small as a single bit, but these instructions can also operate on any combination of bits within any 8-bit location in the 64-Kbyte memory space. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions All the shift and rotate functions in the M68HC11 CPU involve the carry bit in the CCR in addition to the 8- or 16-bit operand in the instruction, which permits easy extension to multiple-word operands. SRI VENKATEWARA COLLEGE OF ENGINEERING

Stack and Index Register Instructions
HC11 Instructions Stack and Index Register Instructions SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions This table summarizes the instructions available for the 16-bit index registers (X and Y) and the 16-bit stack pointer. SRI VENKATEWARA COLLEGE OF ENGINEERING

Condition Code Register Instructions
HC11 Instructions Condition Code Register Instructions These instructions allow a programmer to manipulate bits of the CCR. SRI VENKATEWARA COLLEGE OF ENGINEERING

Program Control Instructions
HC11 Instructions Program Control Instructions 1. Branches 2. Jumps 3. Subroutine calls and returns 4. Interrupt handling 5. Miscellaneous SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions These instructions allow the CPU to make decisions based on the contents of the condition code bits. All decision blocks in a flow chart would correspond to one of the conditional branch instructions summarized here SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions The jump instruction allows control to be passed to any address in the 64-Kbyte memory map. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions These instructions provide an easy way to divide a programming task into manageable blocks called subroutines. The CPU automates the process of remembering the address in the main program where processing should resume after the subroutine is finished. This address is automatically pushed onto the stack when the subroutine is called and is pulled off the stack during the RTS instruction that ends the subroutine SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions This group of instructions is related to interrupt operations, we will get to there use later. SRI VENKATEWARA COLLEGE OF ENGINEERING

HC11 Instructions NOP is a do nothing instruction, just wastes an instruction cycle. STOP is used to put the CPU into a low power mode. TEST is a reserved instruction only used at the factory when making the chips. SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Interrupts SRI VENKATEWARA COLLEGE OF ENGINEERING

Polling and Interrupts
CPU may need to provide support (called a service) to external devices. How? We can POLL devices We can have an Interrupt system We can have a combination of the two SRI VENKATEWARA COLLEGE OF ENGINEERING

Polling “Ask” each device sequentially if it needs service. Note, no devices may need servicing during the poll. SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupts Device “interrupts” CPU to indicate that it needs service. SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Interrupts Interrupt system is “built-in” to 6811 Special interrupt software instructions Special interrupt hardware resources What needs to interrupt? External Devices Keyboards, Mouse, Sensors, etc. Internal Events Reset, Illegal Operation, User Interrupt, etc SRI VENKATEWARA COLLEGE OF ENGINEERING

Types of Interrupts Maskable The program can choose to “ignore” a maskable interrupt by setting the I bit equal to 1 in the CCR. This is called “masking” the interrupt. Setting the I bit = 0 “unmasks” the interrupt, allowing interrupts to be serviced. Condition Code Register SRI VENKATEWARA COLLEGE OF ENGINEERING

Types of Interrupts Non-maskable interrupts A program cannot choose to ignore a non-maskable interrupt. A non-maskable interrupt is used for events that must always be serviced. Example: Reset A special subroutine called an Interrupt Service Routine (ISR) is used to service the interrupt The MC68HC11 has 21 independent interrupts. In this, 6 are non- maskable and 15 are maskable. The three high priority interrupts are RESET , HIRQ and IRQ . SRI VENKATEWARA COLLEGE OF ENGINEERING

Preserving the Program Context
The program context, which is the content of all registers in the 68HC11, must be the same when the main program resumes as it was at the instant of interrupt. To do this, the 68HC11 stacks all the registers as shown in the following figure: SRI VENKATEWARA COLLEGE OF ENGINEERING

This occupies nine locations on the stack. Therefore any programs that use interrupts must initialize the Stack Pointer (SP) before any interrupts are allowed. The RTI simply unstacks the six registers (CC, B, A, X, Y, PC) in that order SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupt Vectors The 68HC11 reserves a set of interrupt vectors in the upper end of ROM (locations FFC0-FFFF). The following table shows the locations of the vectors for each of the various interrupts on the 68HC11. SRI VENKATEWARA COLLEGE OF ENGINEERING

Example The service routine for an IRQ interrupt is to start at $3000, a convenient location we have selected in user RAM. What must be done to make this happen, and what are the steps along the way? Solution During initialization the code 7E (JUMP to $3000) must be written into locations 00EE-00F0. When an IRQ interrupts occurs, the 68HC11 will go to FFF2 and FFF3 where it finds 00EE written. So it will load the PC with 00EE and the program will start there. But the instruction at 00EE is a JUMP to 3000, and it will start executing the service routine there. SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupt Service Routines (ISR)

ISR is a special subroutine that is designed to “service” the interrupt Also called an “interrupt handler” Let’s examine the interrupt process Interrupt Process Interrupt occurs CPU waits until the current instruction has finished being executed. Note: PC is pointing to next instruction to execute All CPU registers including the program counter (PC) and condition code register (CCR) are pushed onto stack Interrupt bit is set (STI) to mask further interrupts. In most cases, you don’t want the ISR to itself be interrupted. The PC is loaded with address of the Interrupt Service Routine (ISR) ISR is executed. The last instruction in the ISR must be RTI. RTI = Return from Interrupt SRI VENKATEWARA COLLEGE OF ENGINEERING

Return from Interrupt Your ISR should almost always end with a RTI instruction RTI – Return from Interrupt What does RTI do? Pulls all registers from stack. The I bit in the pulled CCR is clear, so interrupts are enabled. PC contains address of next instruction Continues interrupted program SRI VENKATEWARA COLLEGE OF ENGINEERING

Example of ISR SRI VENKATEWARA COLLEGE OF ENGINEERING

LED Circuit Example Switch Light On Light Off SRI VENKATEWARA COLLEGE OF ENGINEERING

Polling Example SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 LED Example Polling Example
Pseudo-code (Polling) * Use PA0 for Input, PA6 for output Configure PortA ; Repeat IF(PA0=0) then PA6=0 ; Turn LED OFF Else PA6=1; Turn LED ON EndIF Until Forever SRI VENKATEWARA COLLEGE OF ENGINEERING

Symbols ********************************************************** *Symbols Data EQU $0000 ; This is the address of the data space Program EQU $E000 ; This is the start of the program space Reset EQU $FFFE ; This is the reset vector * Constants PORTA EQU $ ; Port A Address PACTL EQU $ ; Port A Control Register PACONF EQU % ; This configs PortA for I/O mode LED_BIT EQU % ; This it the LED bit MASK EQU % ; This is the input bit mask SRI VENKATEWARA COLLEGE OF ENGINEERING

Polling Example *************************************************************** * Program ORG Program ; start of Program Start: LDAA #PACONF ; Load Port A conf bits STAA PACTL ; Configure port A * * Let's use If(Bit2 = 0) then LED OFF, Else LED ON Loop: LDX #PortA ; Load X with address of port A BRCLR 0,X MASK LED_OFF ; Branch to LED_OFF if PA0 = 0 BSET 0,X LED_BIT ; Turn on LED Bit BRA Loop ; Check switch again LED_OFF: BCLR 0,X LED_BIT ; Turn the LED OFF BRA Loop ; Check switch again Note: This program continually checks to switch SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupt Example SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 LED Example Interrupt Example
Pseudo-code (Interrupt) * Use PA6 for output Configure PortA ; Enable Interrupts Execute any program ISR: *Executed only when interrupt occurs Read PortA If PA0=0 Then LED=0 Else LED=1 Return from Interrupt SRI VENKATEWARA COLLEGE OF ENGINEERING

Symbols ********************************************************** *Symbols Data EQU $0000 ; This is the address of the data space Program EQU $E000 ; This is the start of the program space Reset EQU $FFFE ; This is the reset vector IRQ EQU $FFF2 ; This is the IRQ vector * Constants PORTA EQU $ ; Port A Address PACTL EQU $ ; Port A Control Register PACONF EQU % ; This configs PortA for I/O mode LED_BIT EQU % ; This is the LED bit Mask EQU % ; This is the input bit SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupt Example *************************************************************** * Program ORG Program ; start of Program Top: LDAA #PACONF ; Load Port A conf bits STAA PACTL ; Configure port A CLI ; Enable interrupts * The main program can do anything * Let’s just wait * Loop: BRA Loop * This is the ISR. It will only execute when an interrupt occurs ISR: LDX #PORTA BRCLR 0,X MASK LED_OFF ; If input=0 then Goto LED_OFF LED_ON: BSET 0,X LED_BIT ; Turn LED ON BRA Done ; We are done LED_OFF: BCLR 0,X LED_BIT ; Turn LED OFF Done: RTI ; Return from interrupt SRI VENKATEWARA COLLEGE OF ENGINEERING

Summary Polling Interrupt Switch Input: PA PA0 and IRQ Main Program: Checks Switch Anything ISR: Not needed Required SRI VENKATEWARA COLLEGE OF ENGINEERING

Advanced Interrupts SRI VENKATEWARA COLLEGE OF ENGINEERING

Multiple Devices Use Interrupt to indicate that a device needs to be serviced. ISR then “polls” each device to determine who needs service SRI VENKATEWARA COLLEGE OF ENGINEERING

Multiple Devices May need external logic to “arbitrate” devices SRI VENKATEWARA COLLEGE OF ENGINEERING

Priority with Multiple Devices
What if two devices request an interrupt at the same time? Use a “priority” scheme to determine which device gets serviced first. 68HC11 Built-in Priority Scheme IRQ Real Time Interrupt Timer Input Capture – 1-3 Timer Output Compare – 1-5 Timer Overflow Pulse Accumulator Serial Interface Can be changed via the HPRIO ($103C) register SRI VENKATEWARA COLLEGE OF ENGINEERING

Real Time Clock (RTC) SRI VENKATEWARA COLLEGE OF ENGINEERING

Real Time Clock (RTC) User occasionally want a computer to perform certain I/O operations at specified times. A clock, which is based on the interrupts at preset intervals. An interrupt service routine executes on each timeout (overflow) of this clock. This timing device once started never resets or never reloaded with another value. Once it is set, it is not modified later. SRI VENKATEWARA COLLEGE OF ENGINEERING

RTC Used in a system to save the time and date. Used in a system to initiate return of control to the system (OS) after the set system clock periods SRI VENKATEWARA COLLEGE OF ENGINEERING

RTC Application • Assume that a hardware timer of an RTC for calendar is programmed to interrupt after every 5.15 ms (=1 day period/ 2 24 ) • Assume each tick (interrupt) a service routine runs and updates at a memory location. Within one day (86400 s) there will be 2 24 ticks, the memory location will reach 0x after reaching the maximum value 0xFFFFFF. SRI VENKATEWARA COLLEGE OF ENGINEERING

RTC with 5.5 ms tick • Within 256 days there will be 2 32 ticks, the memory location will reach 0x after reaching the maximum value 0xFFFFFFFF. • A battery is used to protect the memory for long period. SRI VENKATEWARA COLLEGE OF ENGINEERING

RTC for implementing a software A hardware 16-bit timer ticks from processor clock after 0.5 µs. It will overflow and execute an overflow interrupt service routine after µs = ms. The interrupt service routine can generate a port bit output after every time it runs or can call a software routine or send a message for a task. If n = 30, the RTC initiated software will run every 30 × ms, which is close to 1 s. SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 microcontroller RTC Pulse Accumulator Control Register, PACTL and two lowest significance bits, RT1-RT0 (1st and 0th). PACTL is write only. If the RT1-RT0 pair is set =0-0, an RTC interrupt can occur after pulses of the E clock. If the E clock pulses are of 2 MHz and T is 0.5 µs, the interrupt from a real time clock occurs after every ms. SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 microcontroller RTC If the RT1-RT0 pair is 01, an interrupt can occur after pulses of the E clock, that is, after ms. If the RT1-RT0 pair is 10, the interrupt can occur after pulses of the E clock, that is after ms. If the RT1-RT0 pair is 11, an interrupt can occur after pulses of the E clock, that is, after ms. The real time clock is based on a free running counter. RT1-RT0 bits control its rate factor SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 microcontroller RTC RTC disabled or enabled by the I bit in the CC (clock control) register Interrupts from real time clocks are also locally masked by the 6th bit, RTI in timer interrupt mask register2, TMASK2. SRI VENKATEWARA COLLEGE OF ENGINEERING

Unmask and reset to mask of real time interrupt RTI is set to unmask and reset to mask the real time interrupt locally. If RTI and I bits permit the interrupt request for real time, the microcontroller fetches the lower and higher bytes of the interrupt servicing routine address from the addresses 0xFFF0 (higher byte) and 0xFFF1 (lower byte) SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Serial I/O SRI VENKATEWARA COLLEGE OF ENGINEERING

Parallel I/O Multiple I/O lines to transfer data from 6811 to Ext Device SRI VENKATEWARA COLLEGE OF ENGINEERING

Serial I/O Minimum of two lines needed to transfer data from 6811 to Ext Device SRI VENKATEWARA COLLEGE OF ENGINEERING

Why Serial I/O? Simple to implement. Can be very slow. Sending one bit at a time We must send synchronization and/or error checking bits with every data packet. This adds “overhead” to our data transmission. SRI VENKATEWARA COLLEGE OF ENGINEERING

Parallel Data Transfer Example
Assume an 8-bit parallel interface with a transfer rate of 1Megabyte/s. How long will it take to transfer a 15Megabyte file? SRI VENKATEWARA COLLEGE OF ENGINEERING

Parallel Data Transfer Solution
Assume an 8-bit parallel I/O interface with a transfer rate of 1Megabyte per second. How long will it take to transfer a 15Megabyte file? Transfer time: 15 Megabytes * 1 second/Megabyte = 15 seconds SRI VENKATEWARA COLLEGE OF ENGINEERING

Serial Data Transfer Example
Assume an serial interface with a transfer rate of 1Megabit per second. Also, assume an overhead of 2 bits for each byte of data transferred. That is, we need to send 10 bits for every 8 bits of data transferred. How long will it now take to transfer a 15Megabyte file? SRI VENKATEWARA COLLEGE OF ENGINEERING

Serial Data Transfer Solution
Transfer rate = 1Megabit/s Overhead is 2 bits/byte How long will it now take to transfer a 15Megabyte file? Solution: Total Megabits = 15 Megabytes*(10 bits/byte) = 150 Megabits Transfer time: 150 Megabits* (1 second/Megabit) = 150 seconds Note: this is 10x the parallel transfer rate SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Serial I/O Two types: SCI – Serial Communications Interface Asynchronous: No clock needed SPI – Serial Peripheral Interface Synchronous: Clock needed SRI VENKATEWARA COLLEGE OF ENGINEERING

Asynchronous Serial I/O
Minimum of two lines needed to transfer data from 6811 to Ext Device SRI VENKATEWARA COLLEGE OF ENGINEERING

Synchronous Serial I/O
Three lines needed to transfer data from 6811 to Ext Device Extra line is used for clock line. SRI VENKATEWARA COLLEGE OF ENGINEERING

Using the Asynchronous Serial I/O (Ser. Comm. Interface.) on the 68HC11 Initialize the interface Data rate (baud rate) Word length Interrupts, if needed Write to the Data Register Read from the Data Register SRI VENKATEWARA COLLEGE OF ENGINEERING

Initializing the Interface
Polling Method SRI VENKATEWARA COLLEGE OF ENGINEERING

Top Level Pseudo-Code 68HC11
Initialize the interface Set baud rate Set Mode Turn-on transmitter and receiver SRI VENKATEWARA COLLEGE OF ENGINEERING

Set the Baud Rate SRI VENKATEWARA COLLEGE OF ENGINEERING

Baud-$102B Baud Rate Control Reg
TCLR SCP1 SCP0 RCKB SCR2 SCR1 SCR0 7 6 5 4 3 2 1 Bits Scp1 Scp0 Scr2 Scr1 Scr0 Baud Rate K Other bits used for test mode SRI VENKATEWARA COLLEGE OF ENGINEERING

Set the Mode SRI VENKATEWARA COLLEGE OF ENGINEERING

SCCR1 - $102C SCI Control Register 1
M Wake 7 6 5 4 3 2 1 Bits T8 = Transmit Bit 8 used for 9-bit data R8 = Receive Bit 8 used for 9-bit data M = Mode Select 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit SRI VENKATEWARA COLLEGE OF ENGINEERING

Turn on the transmitter and receiver SRI VENKATEWARA COLLEGE OF ENGINEERING

SCCR2 - $102D SCI Control Register 2
TIE TCIE RIE ILIE TE RE RWU SBK 7 6 5 4 3 2 1 Bits TE = Transmit Enable 0 = Disable (default) 1 = Enable This bit should be 1 to use Port D for serial I/O RE = Receiver Enable 0 = Disable (default) 1 = Enable This bit should be 1 to use Port D for serial I/O SRI VENKATEWARA COLLEGE OF ENGINEERING

Pseudo-code 68HC11 Code SRI VENKATEWARA COLLEGE OF ENGINEERING

Pseudo-code Initialize the Serial Port
SCCR1  Mode_Configuration_byte CB = % ; 1 start, 8 data, 1 stop Baud  Baud_Configuration_byte CB = % ; 9600 baud SCCR2  TR_Configuration_byte CB = % ; Xmit and Rcvr Enable SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Assembly language Initializing the Serial Port
* Assume Baud=$1028, SCCR1=$102C, and SCCR2=$102D LDAA #MODE_CB STAA SCSR1 LDAA #Baud_CB STAA BAUD LDAA #TR_CB STAA SCSR2 SRI VENKATEWARA COLLEGE OF ENGINEERING

Writing to the data register
Polling SRI VENKATEWARA COLLEGE OF ENGINEERING

Writing to the serial output port (polling) Repeat Until Transmit_buffer=empty SCDR  A ; assume A register holds data SRI VENKATEWARA COLLEGE OF ENGINEERING

Checking Transmit Buffer SRI VENKATEWARA COLLEGE OF ENGINEERING

SCSR-$102E SCI Status Reg Check status bit TRDE=1 before writing new data TDRE TC RDRF IDLE OR NF FE 7 6 5 4 3 2 1 Bits TDRE = Transmit data register empty flag 0 = not empty. Data are still loaded in SCDR from transmission 1 = empty. SCDR is empty. The next byte can be written to SCDR TC = Transmit complete flag 0 = Transmitter is busy sending a character 1 = Transmitter is done sending the last character. This bit checks the output shift register which is used by TXD SRI VENKATEWARA COLLEGE OF ENGINEERING

Transmitting the Data SRI VENKATEWARA COLLEGE OF ENGINEERING

SCDR - $102F SCI Data Register
To transmit data, write to register SCDR = $102F T7 T6 T5 T4 T3 T2 T1 T0 7 6 5 4 3 2 1 Bits X=Not Used B=Bidirectional SRI VENKATEWARA COLLEGE OF ENGINEERING

Block Diagram Writing to Serial Port
$102F STAA SDSR TDRE=1 when all bits have been transferred to Parallel to Serial Buffer 8-bits Parallel to Serial Buffer 1 bit PD1 Serial Out 7 6 5 4 3 2 1 PortD RXD TXD SCK MISO MOSI SS SRI VENKATEWARA COLLEGE OF ENGINEERING

Port D - $1008 Serial I/O Register
Serial output bit = PD1 1 SS SCK MOSI MISO TXD RXD 7 6 5 4 3 2 1 Bits X=Not Used B=Bidirectional SRI VENKATEWARA COLLEGE OF ENGINEERING

Reading from the data register
Polling SRI VENKATEWARA COLLEGE OF ENGINEERING

Reading from the serial output port (polling) Repeat Until Receiver_buffer=full A  SCDR ; SRI VENKATEWARA COLLEGE OF ENGINEERING

Reading from the data register
Checking Receiver Buffer SRI VENKATEWARA COLLEGE OF ENGINEERING

SCSR-$102E SCI Status Reg Check status bit RDRF to determine when to read the next byte. TDRE TC RDRF IDLE OR NF FE 7 6 5 4 3 2 1 Bits RDRF = Receiver data register flag full 0 = Data register is not full. 1 = Data register has new data Idle = Idle line detected flag 0 = The receive line is active (or has not been active since last IDLE) 1 = The receive line has become idle Used in half-duplex mode SRI VENKATEWARA COLLEGE OF ENGINEERING

SCDR - $102F SCI Data Register
To receive data, read location SCDR= $102F R7 R6 R5 R4 R3 R2 R1 R0 7 6 5 4 3 2 1 Bits X=Not Used B=Bidirectional SRI VENKATEWARA COLLEGE OF ENGINEERING

Pseudo-code Reading from the Serial Port
* Assume data are stored in the A register Repeat Until RDRF=1 ; SCDR  A Return SRI VENKATEWARA COLLEGE OF ENGINEERING

Block Diagram Reading from Serial Port
LDAA SDSR RDRF=1 when all bits have been loaded from serial to parallel buffer 8-bits Serial to Parallel Buffer Serial In PD0 1-bit 7 6 5 4 3 2 1 PortD RXD TXD SCK MISO MOSI SS SRI VENKATEWARA COLLEGE OF ENGINEERING

Parity SRI VENKATEWARA COLLEGE OF ENGINEERING

XOR GATE Equation Symbol Truth Table A B Y 1 SRI VENKATEWARA COLLEGE OF ENGINEERING

XNOR GATE Symbol Truth Table A B Y 1 Equivalence Function SRI VENKATEWARA COLLEGE OF ENGINEERING

Parity Use extra bit for error checking or parity Two types with one bit Odd Parity: Number of ones in data+parity is odd. Even Parity: Number of ones in data+parity is even. Transmitter generates parity bit Use XOR/XNOR function. Odd Parity = XNOR of all of the data bits Even Parity = XOR of all of the data bits Receiver checks parity bit Use same function of all bits (including parity) If output is one, a parity error has occurred SRI VENKATEWARA COLLEGE OF ENGINEERING

Parity Example Assume even parity and given Serial data = $32 In binary = % we have 3 bits (odd), so we XOR all of the data bits and find that the parity bit is 1, which makes the total number of bits even. i.e. 1, Let’s assume no errors in the transmission, at the receiver, we also have: 1, Check parity: XOR of = 0 No error in transmission SRI VENKATEWARA COLLEGE OF ENGINEERING

Parity Example Assume even parity and given Serial data = $32 In binary = % we have 3 bits (odd), so we XOR all of the data bits and find that the parity bit is 1, which makes the total number of 1 bits even. i.e. 1, Let’s assume a single bit error in the transmission, at the receiver, we have: 1, Check parity: XOR of = 1 ERROR in transmission Note: with only one bit, we can only DETECT a single bit error. If two bits are in error, our system will NOT detect the error Using more bits allows us to Detect and Correct error. Hamming Codes: Digital Communications Error SRI VENKATEWARA COLLEGE OF ENGINEERING

Parity in 68HC11 SRI VENKATEWARA COLLEGE OF ENGINEERING

SCCR1 - $102C T8,R8, and M bits R8 T8 M Wake 7 6 5 4 3 2 1 Bits Must generate and check parity manually!!! T8 = Transmit Bit 8 used for parity data R8 = Receive Bit 8 used for parity data M = Mode Select (use mode=1 for parity) 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit SRI VENKATEWARA COLLEGE OF ENGINEERING

SCSR-$102E SCI Status Reg Other status bits TDRE TC RDRF IDLE OR NF FE 7 6 5 4 3 2 1 Bits OR = Receiver overrun error full 0 = No overrun error 1 = An overrun has occurred. Overrun occurs if new character has been received before old data have been read. The new data are lost. NF = Noise Flag 0 = No noise detected during last character read. 1 = Noise detected. 6811 samples each data bit three times, different answers will set NF SRI VENKATEWARA COLLEGE OF ENGINEERING

SCSR-$102E SCI Status Reg Other status bits TDRE TC RDRF IDLE OR NF FE 7 6 5 4 3 2 1 Bits FE = Framing Error 0 = No framing error 1 = Framing error has occurred. If the stop bit is not detected correctly, a framing error will occur. SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupts SRI VENKATEWARA COLLEGE OF ENGINEERING

Configure Interrupt Vector Table (IVT) Initialize the interface Set baud rate Set Mode Turn-on transmitter and receiver Turn-on interrupts TIE bit (Bit 7) in SCCR2 for Transmitter RIE bit (Bit 5) in SCCR2 for Receiver * Normally, only turn one of them on at a time!!! Enable maskable interrupts (CLI) SRI VENKATEWARA COLLEGE OF ENGINEERING

ISR Pseudo-Code 68HC11 Temporarily disable additional interrupts We don’t want our ISR interrupted “Acknowledge” the interrupt request Device sending the request will “quit” asking for service Service the Interrupt Return from the Interrupt SRI VENKATEWARA COLLEGE OF ENGINEERING

Interrupt Control Bits
TIE and RIE SRI VENKATEWARA COLLEGE OF ENGINEERING

SCCR2 - $102D TIE TIE TCIE RIE ILIE TE RE RWU SBK 7 6 5 4 3 2 1 Bits TIE = Transmit Interrupt Enable 0 = Disable (default) 1 = Enable When enabled, generates an SCI interrupt when SCDR is empty TCIE = Transmit Complete Interrupt Enable 0 = Disable (default) 1 = Enable When enabled, generates an SCI interrupt with the output register is empty. SRI VENKATEWARA COLLEGE OF ENGINEERING

SCCR2 - $102D RIE TIE TCIE RIE ILIE TE RE RWU SBK 7 6 5 4 3 2 1 Bits RIE = Receive Interrupt Enable 0 = Disable (default) 1 = Enable This bit should be 1 to used Port D for serial I/O ILIE = Idle line Interrupt Enable 0 = Disable (default) 1 = Enable When enabled, generates an interrupt when the serial line is idle. SRI VENKATEWARA COLLEGE OF ENGINEERING

Pseudo-code Initialize the Serial Port
SCCR1  Mode_Configuration_byte CB = % ; 1 start, 8 data, 1 stop Baud  Baud_Configuration_byte CB = % ; 9600 baud SCCR2  TR_Configuration_byte CB = % Setting the interrupts, SCCR2  Interrupt_Configuration_byte CB = CB | % (Transmitter) CB = CB | % (Receiver) SRI VENKATEWARA COLLEGE OF ENGINEERING

ANALOG TO DIGITAL CONVERTER

Analog signals Analog output is typical of most transducers and sensors. Need to convert these analog signals into a digital representation so the microcontroller can use it. Some characteristics of analog signals. Maximum and minimum voltages Precise continuous signals Rate of voltage change SRI VENKATEWARA COLLEGE OF ENGINEERING

Analog-to-Digital Converters
The ideal transfer function of a 3-bit ADC Full-scale (input voltage) range (FSR) Analog signal is continuous Digital – finite and discrete In general n-bit converter Total of 2n output codes SRI VENKATEWARA COLLEGE OF ENGINEERING

Quantization Error and Full Scale(FS)
The difference between an input value and its quantized value (such as round-off error) is referred to as quantization error. Another term – Full Scale input – the largest analog voltage that a converter can detect. Voltages greater than the FS input will result in a converted value of Similarly inputs less than the minimum input voltage result in SRI VENKATEWARA COLLEGE OF ENGINEERING

Quantization Error of the 68HC11
Graphical view It is a rounding error between the analog input voltage to the ADC and the output digitized value. SRI VENKATEWARA COLLEGE OF ENGINEERING

The 68HC11 The 68HC11 has an 8 bit A/D converter which results in 256 possible digital output values. The resolution = FSR/256 The FSR of the 68HC11 is 0 to 5.12V so the resolution is 20mV/1bit 5.12V/256 = V/bit = 20.3 mV/bit Meaning – input change of 20mV changes LSB SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 ADRs 68HC11 has 4 A-to-D conversion registers When a conversion is done, result is placed in one of the ADRx registers, where x is 1 to 4. SRI VENKATEWARA COLLEGE OF ENGINEERING

Math Conversion equation
The output-input characteristic equation of an ADC D = (1/resolution)Vm Where D is the decimal value of the output word and Vm is the measured voltage. Example The input voltage is 2.56V – what is the converted digital value? Output D = (1bit/20mV)2560mV = 128 Converting to binary gives which will be stored in one of the 4 result registers. SRI VENKATEWARA COLLEGE OF ENGINEERING

Port E and ADR addresses
When using Port E as a digital port the port is accessed through address $100A The A/D control register, ADCTL, is at address $1030 The ADR registers are at addresses – these are read only registers. ADR1 - $1031 ADR2 - $1032 ADR3 - $1033 ADR4 - $1034 SRI VENKATEWARA COLLEGE OF ENGINEERING

ADCTL register To use the A/D converter on the 68HC11 the users only needs to write to ADCTL for the CPU to read results from the register. There are 8 A/D channels but only 4 results from one of the two groups of 4 can be stored at any one time. Could also use the 4 registers to save 4 conversions from one input pin ADCTL register – controls how the A/D converter works and how the registers are used. SRI VENKATEWARA COLLEGE OF ENGINEERING

The bits in the control register
Bit 7 – Conversion complete – a read only bit Cleared any time the control register written to Set when the A/D completes the 4th conversion and results stored in registers. Conversion starts immediately after a write to this register. If a conversion was in progress it is aborted to allow the initiation of the new conversion. When set up for continuous conversion results are updated automatically. SRI VENKATEWARA COLLEGE OF ENGINEERING

Control register continued
Bit 6 – unused Bit 5 – SCAN Value of 0 – single conversion mode – conversion takes place after a write to the register. Value of 1 – continuous conversion mode – conversions take place in round robin mode on the enabled analog input pins. Bit 4 – Multiple/Single Channel Control (MULT) Value of 0 – Single channel – Consecutive conversions results are stored in consecutive ADRx registers Value of 1 – each pin in the group is converted and the result stored in the ADR register. SRI VENKATEWARA COLLEGE OF ENGINEERING

More on control register
Bits 3,2,1,0 – Channel select bits For the 48-pin package – only 4 A/D inputs How the CD, CC, CB, CA control bits work The MULT bit says 1 channel or all 4 Table lists specific group and pin(s) SRI VENKATEWARA COLLEGE OF ENGINEERING

Example of interface setup
What configuration is needed in the ADCTL register for the A/D to convert continuously group 0? Solution: Bits 7 and 6 are don’t cares Bit 5 = 1 convert continuously Bit 4 = 1 group of 4 channels Bits 3 and 2 = 00 group 0, PE0-3 Bits 1 and 0 are not used. Value of xx11 00xx or could store $30 SRI VENKATEWARA COLLEGE OF ENGINEERING

Setup example 2 What value needs to be written to the ADCTL register to have continuous conversions of pin PE0? What assembler language instructions would you use to set up this? Set ADCTL as follows: Bits 7 and 6 – don’t cares Bit 5 – 1 convert continuously val – Bit 4 – 0 single channel Bit 3,2,1,0 – 0000 the value for PE0 The assembler code (assumes A accumulator is free) LDAA #$20 STAA $1030 SRI VENKATEWARA COLLEGE OF ENGINEERING

Example 3 Your system has 2 analog sensors. You only need to acquire the value of a given sensor at certain points. How would this be set up. Probably through subroutines. Specifications of the problem Sensor 1 – on pin PE0-ADR1 Sensor 2 – on pin PE1-ADR2 The valx values for the code val1 – val2 – How is the A/D being set up for conversion? Could also be done with and SRI VENKATEWARA COLLEGE OF ENGINEERING

Signal setup for A/D use
The 68HC11 needs 2 reference input voltages. A low voltage reference – VRL – pin 51 A high voltage reference – VRH – pin 52 To prevent damage the analog input signals must be current limited. Input current should not exceed 25mA Connect signal through a resistor of value 1kW to 10kW SRI VENKATEWARA COLLEGE OF ENGINEERING

Input sensors Transducers, such as pressure, temperature, and acceleration, covert the physical quantity being monitored into and output of voltage, current, or resistance. To get the signal to the 68HC11 the signal needs to be a voltage. SRI VENKATEWARA COLLEGE OF ENGINEERING

PULSE WIDTH MODULATION(PWM)

The 68HC11 Family offers a selection of Pulse-Width Modulation (PWM) options to support a variety of applications. Up to six PWM channels can be selected to create continuous waveforms with programmable rates and software selectable duty cycles from 0 to 100%. Stepper motors can be easily controlled using PWM, as well as DC motors. The torque and speed of a DC motor can be controlled by altering the voltage or the duty cycle of the PWM easily. SRI VENKATEWARA COLLEGE OF ENGINEERING

To start PWM operation, the data sheet suggests the software should: Set the period in the on-chip timer/counter that provides the modulating square wave. Set the on-time in the PWM control register. Set the direction of the PWM output, which is one of the general-purpose I/O pins. Start the timer. Enable the PWM controller. SRI VENKATEWARA COLLEGE OF ENGINEERING

UART SRI VENKATEWARA COLLEGE OF ENGINEERING

UART Universal Asynchronous Receiver Transmitter Serial Data Transmission SRI VENKATEWARA COLLEGE OF ENGINEERING

68HC11 Microcontroller UART Registers RSR Receive Shift Register RDR Receive Data Register TDR Transmit Data Register TSR Transmit Shift Register SCCR Serial Communications Control Register SCSR Serial Communications Status Register UART Flags TDRE Transmit Data Register Empty RDRF Receive Data Register Full SRI VENKATEWARA COLLEGE OF ENGINEERING

UART Block Diagram SRI VENKATEWARA COLLEGE OF ENGINEERING

Transmitter Operation
Microcontroller waits until TDRE = '1‘ If TDRE is 0 then, Loads data into TDR Clears TDRE UART transfers data from TDR to TSR Sets TDRE UART outputs start bit ('0') then shifts TSR right eight times followed by a stop bit ('1') SRI VENKATEWARA COLLEGE OF ENGINEERING

Transmitter SM Chart SRI VENKATEWARA COLLEGE OF ENGINEERING

Receiver Operation UART waits for start bit Shifts bits into RSR When all data bits and stop bit are received RSR loaded into RDR Set RDRF Microcontroller waits until RDRF is set Read RDR Clear RDRF SRI VENKATEWARA COLLEGE OF ENGINEERING

Sampling RxD SRI VENKATEWARA COLLEGE OF ENGINEERING

Baud Rate Generator Select Bits BAUD Rate 000 38,462 001 19,231 010 9615 011 4808 100 2404 101 1202 110 601 111 300.5 SRI VENKATEWARA COLLEGE OF ENGINEERING

MOTOROLA 68HC11 MICROCONTROLLERS

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MOTOROLA 68HC11 MICROCONTROLLERS

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