March 2003 doc.: IEEE 802.15-3/139r1 May 2003 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [STMicroelectronics.

March 2003 doc.: IEEE /139r1 May 2003 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [STMicroelectronics proposal for IEEE a Alt PHY] Date Submitted: [09 May, 2003] Source: [Didier Helal (Primary) Philippe Rouzet (Secondary)] Company [STMicroelectronics] Address [STMicroelectronics, 39 Chemin du Champ des Filles 1228 Geneve Plan-les-Ouates, Switzerland] Voice [ or ], Fax [ ], philippe Re: [This is a response to IEEE P Alternate PHY Call For Proposals dated 17 January 2003 under number IEEE P /372r8 ] Abstract: [This document contents the proposal submitted by ST for an IEEE P Alternate PHY based on UWB technique.] Purpose: [Presentation to be made during May IEEE TG3a session in Dallas, Texas] Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

STMicroelectronics Proposal for IEEE 802.15.3a Alternate PHY
May 2003 STMicroelectronics Proposal for IEEE a Alternate PHY May 2003, Dallas, Texas Didier Hélal, Philippe Rouzet R. Cattenoz, C. Cattaneo, L. Rouault, N. Rinaldi, L. Blazevic, C. Devaucelle, L. Smaïni, S. Chaillou Didier Helal and Philippe Rouzet, STM

Contents UWB PHY Proposal Performances at 110Mb/s, 200Mb/s, 480Mb/s
May 2003 Contents UWB PHY Proposal Proposed Modulation Proposed MAC Enhancements Proposed other criteria definition Performances at 110Mb/s, 200Mb/s, 480Mb/s PHY protocol Criteria MAC protocol Enhancement Criteria General Solution Criteria Didier Helal and Philippe Rouzet, STM

May 2003 Contents UWB PHY Proposal Proposed Modulation Proposed MAC Enhancements Other criteria definition Performances at 110Mb/s, 200Mb/s, 480Mb/s PHY protocol Criteria MAC protocol Enhancement Criteria General Solution Criteria Didier Helal and Philippe Rouzet, STM

Proposed Modulation Pulse Position + Polarity Modulation
March 2003 doc.: IEEE /139r1 May 2003 Proposed Modulation Pulse Position Polarity Modulation Number of bits per pulse = 1, 2, or 3 1 bit/pulse=POL+POS 1 ; 2 bits/pulse=POL+POS 1,2 ; 3 bits/pulse=POL+POS 1,2,3,4 Tp = 300ps : de-correlate PPM symbols ; minimize ISI (one PRP to the following one) Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

MODULATION 55 Mbps 61.5 Mbps Pol 1/3 5.4ns 110 Mbps 123 Mbps Pol+2ppm
March 2003 doc.: IEEE /139r1 May 2003 MODULATION PAYLOAD Bit Rate Target PAYLOAD Bit Rate Effective Modulation Code-rate PRP 55 Mbps 61.5 Mbps Pol 1/3 5.4ns 110 Mbps 123 Mbps Pol+2ppm 200 Mbps 247 Mbps 2/3 480 Mbps 486 Mbps Pol+4ppm 7/8 SELECT BEST MODES ADD a SLIDE WITH LOW DATA RATES : 55Mbps and less ? Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Equally spaced Positions
May 2003 1 bit / pulse 2 bits / pulse 3 bits / pulse Equally spaced Positions 1 2 3 4 t Tp = 300ps Didier Helal and Philippe Rouzet, STM

May 2003 BIT MAPPING Gray-invert mapping: takes advantage from the bi-orthogonal modulation PPM+Polarity. 000 001 011 010 101 100 110 111 Didier Helal and Philippe Rouzet, STM

Channel coding options
March 2003 doc.: IEEE /139r1 May 2003 Channel coding options Turbo codes PCCC (Parallel Concatenation of Convolutional Codes) Code rate 1/3. With puncturing:1/2, 2/3,7/8. RSC (recursive systematic convolutional) 13,15(octal def.). Block size: 512. Low latency : 5 s Convolutional codes for lower complexity Code rate 1/3. With puncturing:2/3,7/8 Constraint length: 7 -> [133,145,175] UPDATE from last results on optimized TC Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Adaptive band Pulse shape
May 2003 Adaptive band Pulse shape Pulse shape should be adapted to any regulation, provided the pulse power spectral density fits emission mask. Flexibility on pulse shape enables compatibility with more stringent regulations worldwide. See ref. IEEE /211r0. Didier Helal and Philippe Rouzet, STM

Example of a full band pulse shape P1
May 2003 Example of a full band pulse shape P1 Average TX power = 0.3 mW Peak emission power in 50MHz = -10 dBm BW-10dB = 7.26 GHz Didier Helal and Philippe Rouzet, STM

March 2003 doc.: IEEE /139r1 May 2003 FRAME: Known Training Sequence for Frame Synchronization and Channel Estimation Frame Preamble Modulated user data Frame Preamble PRP Time Hopping + Polarity Common to all sent datas 2-PPM + Polarity (Time Hopping optional) Example of a simplified emitted pulse train Pulse shape not shown (use rectangle for clarity) Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

March 2003 doc.: IEEE /139r1 May 2003 BEACON is a regular frame with appended preamble for Coarse Synchronization Beacon Beacon Preamble Frame Sync.+ Ch. Est Piconet Information Coarse Sync. PRP GIVE TIME-HOPPING+POLARITY CODES Time Hopping + Polarity Time Hopping + Polarity 2-PPM + Polarity (Time Hopping optional) Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Contention Free Period
March 2003 doc.: IEEE /139r1 Scenario May 2003 Cell synchronization Cell synch Cell synch Frame synch COARSE SYNCHRONIZATION Superframe N Superframe N+1 Contention Free Period Beacon Contention Access Period preamble preamble header body MCTA 1 MCTA n CTA 1 CTA 2 CTA x CTA m preamble … … … … Preamble Detection (search one sequence among 20) Alignement (find end of beacon preamble) Split slide ? Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Cell synchronization FINE SYNCHRONISATION March 2003
doc.: IEEE /139r1 Scenario May 2003 Cell synchronization Cell synch Cell synch Frame synch FINE SYNCHRONISATION Superframe N Superframe N+1 Contention Free Period Beacon Contention Access Period preamble preamble header body MCTA 1 MCTA n CTA 1 CTA 2 CTA x CTA m preamble … … … … Body Frame sent to DEV-A by DEV-B Header Preamble Frame Synchronisation Fine Synchronisation only (made jointly with ch.est.) Split slide ? DEV-A and DEV-B are synchronized to PNC’s clock DEV-A’s clock is synchronized to DEV-B’s clock, and can start to demodulate the data contained in the frame sent by DEV-B. DEV-A wakes up, and needs to synchronize to DEV-B’s clock. Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Contention Free Period Cell Synchronization = Coarse + Fine + Clock
March 2003 doc.: IEEE /139r1 Scenario May 2003 Cell synchronization Cell synch Cell synch CLOCK SYNCHRONISATION - correct clock drift between TX DEV and RX DEV Frame synch Superframe N Superframe N+1 Contention Free Period Beacon preamble Contention Access Period preamble preamble header body MCTA 1 MCTA n CTA 1 CTA 2 CTA x CTA m … preamble … … … Split slide ? Cell Synchronization = Coarse + Fine + Clock Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Coarse Sync: Beacon Preamble Construction
May 2003 Coarse Sync: Beacon Preamble Construction Quadratic-Congruence Hadamard (QCH) sequence. Length of QCH sequence for coarse sync.: LC = 79. TH code: Polarity code: derived from row of a Hadamard matrix of size 80 x 80. PRP = 5.4 ns. TH offset resolution: 50ps. Sequence is repeated R = times. Duration of coarse sync beacon preamble: DC = R*LC *PRP = 52.5 s. Append after this beacon preamble, the regular frame preamble. 20 different sequences to distinguish between piconets are enough. i = 1,2,…,20: sequence number n = 0,1,…,78: TH offset index One sequence: LC*PRP End of Beacon Preamble (EOBP) signature ….. + + + 120 repetitions - - Beacon preamble duration: DC = 52.5 s Didier Helal and Philippe Rouzet, STM

Proposed MAC is compliant with existing MAC IEEE 802.15.3
May 2003 MAC enhancements Proposed MAC is compliant with existing MAC IEEE Introduction of optional minor MAC adaptations to optimize Receiver power consumption Complexity (synchronization) Performance (ARQ) Goal is to avoid CCA challenge Didier Helal and Philippe Rouzet, STM

May 2003 MAC improvements MCTAs and Slotted Aloha used instead of CAP (CCA difficult with UWB-PHY) Approximate frames Times Of Arrival (TOAs) Announced by source DEV at the begining of CTA Used for channel estimation & synchronization Several ways of TOA signaling possible (I.e. one example presented after) Benefits : ARQ scheme can be improved (One ACK per CTA to lower overhead) Hook for localization feature Didier Helal and Philippe Rouzet, STM

Proposed TOA use by MAC for Frame synchronization
May 2003 Proposed TOA use by MAC for Frame synchronization Joint Channel Estimation and Frame Synchronization Estimation valid during channel stationarity (1ms) Frame preamble built from repetition of QCH sequences (same family as coarse sequences) : duration = 3.4 s Use of approximate frame TOAs to manage different lengths of frames MIFS MIFS MIFS 3 MIFS Frame 4 MIFS Frame 5 MIFS 6 MIFS Frame 1 Frame 2 CTA slot in superframe TOA 1 TOA 2 TOA 3 TOA 4 TOA 5 TOA 6 TOA 1 TOA 2 TOA 3 TOA 4 TOA 5 TOA 6 CTA Header announcing TOAs Didier Helal and Philippe Rouzet, STM

PHY Header, MAC Header (802.15.3 format), HCS use 61.5Mb/s mode
May 2003 PHY-SAP Data Throughput close to Payload Bit Rate Payload Bit Rate (Mb/s) PHY-SAP Throughput (Mb/s) 5 frames PHY-SAP Throughput (Mb/s) 1 frame T_DATA (1020 Bytes MPDU) 61.5(mandatory) 58.2 56.9 s 123 (mandatory) 110.87 106.27 66.34 s 247 (optional) 203.19 188.25 33.04 s 486 (optional) 342.15 301.8 16.79 s Optimized Packet Overhead Times T_PA_ INITIAL T_PHYHDR T_MACHDR T_HCS T_MIFS T_SIFS CONT T_RIFS 3.4s 0.26s 1.3 s 1s 5s 10 s PHY Header, MAC Header ( format), HCS use 61.5Mb/s mode Didier Helal and Philippe Rouzet, STM

Out-of-band rejection filter
May 2003 Out-of-band rejection filter Proposed: use elliptic filter with poles placed at known out-of-band interferers. e.g. BP 3rd order with pole at 2.45GHz Didier Helal and Philippe Rouzet, STM

May 2003 Contents UWB PHY Proposal Proposed Modulation Proposed MAC Enhancements Proposed other criteria definition Performances at 110Mb/s, 200Mb/s, 480Mb/s PHY protocol Criteria MAC protocol Enhancement Criteria General Solution Criteria Didier Helal and Philippe Rouzet, STM

Proposed Alternate PHY enables Single Chip FULL CMOS solution
May 2003 Proposed Alternate PHY enables Single Chip FULL CMOS solution Through DIRECT SAMPLING on 1 BIT and DIGITAL MATCHED FILTERING Learn pulse signature after channel propagation Didier Helal and Philippe Rouzet, STM

Demodulation is performed by Match-Filtering
May 2003 Demodulation is performed by Match-Filtering Demodulation Rx signal Match-filtering Tx signal Channel Estimation Average Compound Channel Response Channel+ Noise The match-filter is the estimate of the pulse signature through channel propagation No pulse shape is assumed by receiver ! Take advantage of multi-path (complete immunity) Didier Helal and Philippe Rouzet, STM

Channel estimation easy to implement
March 2003 doc.: IEEE /139r1 May 2003 Channel estimation easy to implement Each point of the channel estimation can be seen as one finger of a rake receiver 64 ns = 1280 fingers of 50 ps width Channel estimation consists in coherent integration of received pulses. One bit ADC makes the operation a simple increment/decrement No multiplication or complex operator ! Estimated gate count of the whole channel estimation block bit slice number of gates * number of bit of the counter * number of channel point (20*7*1280 = gates) Power consumption Parallel hardware implementation of all fingers Frequency of operations is low (1/PRP) Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

MAC+BB+RF on same silicon except BP filter and Antenna
May 2003 UWB System-on-Chip Block Diagram RF block Antenna BP Filter Pulse Generator Clock Synthesizer 1-bit ADC TDD Switch ABR Optional LNA PTC Frag-mentation TX Preparation TX Data Channel Coding Modulation & coding TX Control PTC Channel estimation Synchronization RX Control Channel Decoding Demodulation Defrag- mentation RX Data MAC block (Bottom part) Baseband block PTC = Piconet Time Control ABR = Adaptive Band Rejection MAC+BB+RF on same silicon except BP filter and Antenna Didier Helal and Philippe Rouzet, STM

May 2003 Link Budget Optional Noise figure for all RX chain referred at the antenna output Antenna Pulse Generator ABR TDD Switch BP Filter Clock Synthesizer G = 16dB 1dB loss 2dB loss 1-bit ADC ABR LNA NF = 9dB 2dB NF = 3.5dB Clock Jitter : 10ps rms (maximum from 0.13m silicon measurements) Implementation loss = jitter effect <2dB (varies with pulse shape) + 2dB margin in order to enable simplest demodulation Didier Helal and Philippe Rouzet, STM

110Mbps @ 10m, CM4 EFFECTIVE THROUGHPUT 123 Mbps MAXIMUM RANGE 14 m
May 2003 10m, CM4 EFFECTIVE THROUGHPUT 123 Mbps MAXIMUM RANGE 14 m CM3 adds 0.1 dB to margin Didier Helal and Philippe Rouzet, STM

55Mbps @ 10m, CM4 EFFECTIVE THROUGHPUT 61.5 Mbps MAXIMUM RANGE 17 m
May 2003 10m, CM4 EFFECTIVE THROUGHPUT 61.5 Mbps MAXIMUM RANGE 17 m Didier Helal and Philippe Rouzet, STM

200Mbps @ 4m, CM2 EFFECTIVE THROUGHPUT 247 Mbps MAXIMUM RANGE 8 m
May 2003 4m, CM2 EFFECTIVE THROUGHPUT 247 Mbps MAXIMUM RANGE 8 m Didier Helal and Philippe Rouzet, STM

480Mbps @ 1m , CM2 EFFECTIVE THROUGHPUT 486 Mbps MAXIMUM RANGE 2.8 m
May 2003 1m , CM2 EFFECTIVE THROUGHPUT 486 Mbps MAXIMUM RANGE 2.8 m CM1 adds 1 dB to margin Didier Helal and Philippe Rouzet, STM

Option for 480Mbps extended range
May 2003 Option for 480Mbps extended range EFFECTIVE THROUGHPUT 500 Mbps MAXIMUM RANGE 5 m Performances can be improved by using: PRP = 4ns TC with code rate 2/3. Didier Helal and Philippe Rouzet, STM

Comparison on different pulse shapes
May 2003 Comparison on different pulse shapes 2 4 6 8 10 12 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 3-7GHz 7 sub-bands Pulse P2 BW = GHz At 110Mbps, CM4 or CM3, Link budget margin is 3 dB BW = ; GHz At 110Mbps, CM4 or CM3, Link budget margin is 1.7dB Monopulse Adaptive band PPM-UWB system easily accommodates regulation impact on pulse shape Didier Helal and Philippe Rouzet, STM

Coexistence and regulatory impact
May 2003 Coexistence and regulatory impact Coexistence with in-band systems ensured by TX pulse shaping or filtering System is independent from pulse shape Transmit power control reduces interferences Helped by location awareness capability (distance can be estimated with 3cm resolution) No impact on current regulation FCC’s Part 15 rules followed Additional spectrum protection can be supported Power Management modes are supported (DSPS, PSPS, APS) Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets
May 2003 Simultaneously operating Piconets Single Interferer Interferer dint CM1, CM2, CM3 or CM4 multipath channel CM1, CM2, CM3 or CM4 multipath channel TX DEV dref Rx level = (limit PER=8%) + 6dB RX DEV Modulation : 2-PPM, Prp =5.4 ns, CR 1/3, 123 Mbps Continuous overlapping interferer transmission (worst condition) Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Single piconet interferer
May 2003 Simultaneously operating Piconets Single piconet interferer Dref/Dint is better than 3 (for 123 Mbps modulation) CM3, CM4 supports ~3 meters for a Ref 10 meters Interfering channel slightly impacts performance (better for low density channel such as CM1 and CM2, instead of CM3,CM4) -> 2.5 meters instead of 3 meters Pulse BW impact performances Dref/Dint ~ (BW) PRP or Datarate impact performances Dref/Dint ~ (PRP) using the same modulation scheme, just changing PRP (and along the datarate) Gracefull degradation of performance in case of strong UWB interferer by adjusting PRP Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Effect of TH
May 2003 Simultaneously operating Piconets Effect of TH Effect of Time hopping in modulated data on interferer immunity Small effect, equivalent of ~0.1 dB Effect is marginal on average but smooth some worst case Marginal improvement for a marginal added complexity TH may be kept as on option in standard (TBD) Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Multiple Piconet interferers
May 2003 Simultaneously operating Piconets Multiple Piconet interferers 3 Interferers dint CM3 or CM4 multipath channel Free space channel TX DEV dref Rx level = (limit PER=8%) + 6dB RX DEV Modulation : 2-PPM, Prp =5.4 ns, CR 1/3, 123 Mbps Continuous overlapping interferer transmission (worst condition) Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Multiple piconet interferer
May 2003 Simultaneously operating Piconets Multiple piconet interferer Multiple Interferer use free space channel Low width of pulse means small effect on receiver Infinite rake architecture and 1 bit sampling gives strong performance here 2 Interferers : Dref/Dint is better than 40 (for 123 Mbps modulation) CM1, CM2, CM3, CM4 supports 2 ~0.25 meters for a Ref 10 meters 3 Interferers : Dref/Dint is better than 13 (for 123 Mbps modulation) CM3, CM4 supports 3 ~0.7 meters for a Ref 10 meters Didier Helal and Philippe Rouzet, STM

Interference and Susceptibility
May 2003 Interference and Susceptibility System supports low Signal-to-Interferer-Ratios : SIR > -50dB for any in-band narrow-band Interferer Adaptive Band Rejection 802.11a OFDM interferer : SIR>-30dB (at 5.3GHz or other) Generic in-band interferer : SIR>-30dB (at any frequency) BaseBand Filtering rejection : SIR > -20dB All out-of-band interferers supported (according to IEEE a proposed criteria). Didier Helal and Philippe Rouzet, STM

Power Consumption estimates
May 2003 Power Consumption estimates PAYLOAD Bit Rate Target PAYLOAD Bit Rate Effective Modulation Code-rate PRP Power Consumption 55 Mbps 61.5 Mbps Pol 1/3 5.4ns 180mW 110 Mbps 123 Mbps Pol+2ppm 200mW 200 Mbps 247 Mbps 2/3 480 Mbps 486 Mbps Pol+4ppm 7/8 230mW Hypothesis : convolutional coding, channel estimation operating during 10% of time Didier Helal and Philippe Rouzet, STM

May 2003 Gate count & Consumption calcul (1/2) Example with the Channel Estimation Each point of the channel estimation can be seen as one finger of a rake receiver.(I.e. 64 ns = 1280 fingers of 50 ps width) The channel estimation consists to integrate coherently pulses. As the front-end is a one bit ADC, for each point of the channel, the operation is simply an increment/decrement. (I.e 1280 Inc/Dec for each pulse in TS, 1000 pulses -> 1.2 M Inc/Dec, No multiplication or complex operator !) Estimated gate count : We need about 20 gates for each bit slice of an up-down counter : on flip-flop, and add-sub and a few more for count gating. So the gate count of the whole channel estimation block is : 20 * number of bit of the counter * number of point of the channel (Using parallel hardware implementation of each finger, to keep low clock rate of 1/PRP) Consumption : As the increment/decrement operation needs to be done only at each pulse the frequency is 1/PRP. The estimation of the consumption in 0.13 m is 6 nW/Gate/MHz Didier Helal and Philippe Rouzet, STM

Gate count & Consumption calcul (2/2)
May 2003 Gate count & Consumption calcul (2/2) Didier Helal and Philippe Rouzet, STM

Current Demonstrator Platform
March 2003 doc.: IEEE /139r1 May 2003 Current Demonstrator Platform RF transmitter and receiver : ASIC. First chipset already in test Full chipset on September 2003 Baseband Today : off-the-shelves board (Nallatech BenNuey) with FPGA Xilinx Virtex2 6000 End of 2003 : ASIC 0.13 m Current progress in demonstrator shows low risk manufacturability (Baseband in FPGA today implies easy migration to ASIC, RF already in test) Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Lay-out of the clock generation block
May 2003 Lay-out of the clock generation block CMOS 0.13m Didier Helal and Philippe Rouzet, STM

FPGA Floorplaning and Routing
March 2003 doc.: IEEE /139r1 May 2003 FPGA Floorplaning and Routing Current estimates on gate count and power consumption are based on real implementation Design Information Target Device : x2v6000 Target Package : bf957 Target Speed : -4 Mapper Version : virtex2 -- $Revision: 1.4 $ Mapped Date : Fri May 09 11:15: Design Summary Number of errors: Number of warnings: 0 Number of Slices: ,606 out of 33, % Number of Slices containing unrelated logic: out of 25, % Number of Slice Flip Flops: ,298 out of 67, % Total Number 4 input LUTs: ,944 out of 67, % Number used as LUTs: ,305 Number used as a route-thru: ,639 Number of bonded IOBs: out of % IOB Flip Flops: Number of GCLKs: out of % Didier Helal and Philippe Rouzet, STM Didier Helal and Philippe Rouzet, STM

Easy Manufacturability and attractive form factor
May 2003 Easy Manufacturability and attractive form factor Full system can be built in CMOS technology single chip Die size estimated at less than 5mm2 in 0.13m Antenna size : expected 3cm x 3cm (printed PCB) Time to Market can be less than 1.5 years ! Didier Helal and Philippe Rouzet, STM

Monopulse Adaptive band PPM assets
May 2003 Monopulse Adaptive band PPM assets Theoretical capacity is linear with BW Per bit energy maximized (for a given datarate and spectrum limit) Simultaneously operating piconets supported UWB interference rejection varies along with BW.PRP product Given a modulation scheme, dref/dint ~ sqrt(BW) Synchronization use of full BW, good energy level available, short sequence possible, fine synch and channel estimation optimized joint process Good localization ability thanks to better channel time resolution Less fading issues, optimal energy capture (using infinite rake architecture) Didier Helal and Philippe Rouzet, STM

Monopulse Adaptive band assets
May 2003 Monopulse Adaptive band assets Pulse shape (so BW) is not hard coded in standard Backward compatibility between technology generations E.g GHz in 0.13um and GHz in 90nm Flexible data rate : PRP is easily changed Compatibility between High and Low Data Rate devices Complexity decreases along with data rate Power consumption decreases with data rate Didier Helal and Philippe Rouzet, STM

General Solution Criteria MAC Protocol Enhancement Criteria
May 2003 CRITERIA REF LEVEL STM RESPONSE General Solution Criteria Unit Manufacturing Complexity 3.1 B Low - Single chip solution Signal Robustness Interference and Susceptibility 3.2.2 A Out-band and In-band Interferers rejected at down to 0.3m Coexistence 3.2.3 Pulse shaping or filtering Technical Feasibility Manufacturability 3.3.1 Easy - full CMOS Time To Market 3.3.2 year Regulatory Impact 3.3.3 Flexible emitted pulse shape Scalability 3.4 C Scalable data rates, ranges and power consumption Location awareness 3.5 Supported + built in “hooks” MAC Protocol Enhancement Criteria MAC Enhancements And Modifications 4.1 Compliant Didier Helal and Philippe Rouzet, STM

PHY Protocol Criteria May 2003 CRITERIA REF. LEVEL STM RESPONSE
Size And Form Factor 5.1 B Single Chip 5mm2 PHY-SAP Payload Bit Rate & Data Throughput Payload Bit Rate 5.2.1 A All rates supported up to 1Gbps (+Low Data Rates) PHY-SAP Data Throughput 5.2.2 Short preamble and inter-frame space Simultaneously Operating Piconets 5.3 Different preambles for piconets TH+polarity code division Signal Acquisition 5.4 Short synchronization time (good sequence/continuous sampling) Link Budget 5.5 Margin is 4.8dB at 10m (2dB for lowest complexity) Sensitivity 5.6 dBm (-75.7dBm for lowest dBm (-77.6dBm for lowest Multi-Path Immunity 5.7 Channel Estimation + Matched-Filter Retrieves all energy Power Management Modes 5.8 All modes supported Power Consumption 5.9 Very Low. ADC already scaled for highest data-rates Antenna Practically 5.10 cmx3cm printed Didier Helal and Philippe Rouzet, STM

Proposal matches all criteria at Very Low Cost and
May 2003 Proposal matches all criteria at Very Low Cost and Very Low Power Consumption Thank you for your attention Questions are welcome… Didier Helal and Philippe Rouzet, STM

May 2003 BACKUP SLIDES Didier Helal and Philippe Rouzet, STM

May 2003 Simultaneously operating Piconets Single piconet interferer : Hypothesis Simulation hypothesis Reference link is a multipath channel in CM3 or CM4 (CM1 and CM2 are short range and “easy case”, no near far, so not considered for first simulations), several (5) channels of each CM are used Rx level is tuned to get 6 dB above the limit of 8% PER (limit level is known from performance simulation as Eb/No for the current simulated channel, 200+ packets simulated to get the reference) Interferer level is set from dint simulated (P.d² is constant, and Tx power is same for Ref and for interferer) Interferer channel is a multipath channel in CM1,2,3 or 4 (5 channels of each are used) Modulation used is 2-PPM, Prp =5.4 ns, CR 1/3, 123 Mbps Simulation operation : dint is tuned to get the reference PER limit of 8% (only the WORST case ratio of distance : dref /dint is kept as result) Didier Helal and Philippe Rouzet, STM

May 2003 Simultaneously operating Piconets Single piconet interferer Simulation results P1(3-10GHz) at Eb/No ~ 6.2 dB Worst case ratio Dref/dint (= Near far factor) Int is CM1 Int is CM2 Int is CM3 Int is CM4 Ref is CM1 (5 channels used) 3.7 =10m/2.7m 3.6 =10m/2.8m 3.2 =10m/3.1m 3.1 =10m/3.2m Ref is CM2 3.8 =10m/2.6m 3.6 =10m/2.8m 3 =10m/3.3m Ref is CM3 4 =10m/2.5m 3.2 =10m/3.1m 3.1 =10m/3.2m Ref is CM4 3.8 =10m/2.6m 3.4 =10m/2.9m 3.0 =10m/3.3m Didier Helal and Philippe Rouzet, STM

May 2003 Simultaneously operating Piconets Single piconet interferer Simulation results P2 (3-7GHz) at Eb/No ~ 6.2 dB Worst case ratio Dref/dint (= Near far factor) Int is CM1 Int is CM2 Int is CM3 Int is CM4 Ref is CM1 * Ref is CM2 Ref is CM3 (5 channels used) 3.3 =10m/3.0m 2.8 =10m/3.5m 2.9 =10m/3.4m 2.7 =10m/3.6m Ref is CM4 2.8 =10m/3.5m 2.9 =10m/3.4m Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Single piconet interferer PRP effect
May 2003 Simultaneously operating Piconets Single piconet interferer PRP effect Simulation results P1 at Eb/No ~ 6.2 dB, CR=1/3, PRP=10.8 ns 61.5 Mbps (half data rate since double PRP, but better Interferer rejection) Worst case ratio Dref/dint (= Near far factor) Int is CM1 Int is CM2 Int is CM3 Int is CM4 Ref is CM1 (5 channels used) * Ref is CM2 Ref is CM3 7.1 =10m/1.4m 5.8 =10m/1.7m 5.2 =10m/1.9m 5.0 =10m/2.0m Ref is CM4 4.8 =10m/2.1m Didier Helal and Philippe Rouzet, STM

Simultaneously operating Piconets Multiple piconet interferers
May 2003 Simultaneously operating Piconets Multiple piconet interferers Simulation hypothesis Reference link is a multipath channel in CM3 or CM4 (CM1 and CM2 are short range and “easy case”, no near far, so not considered for first simulations), several (5) channels of each CM are used Rx level is tuned to get 6 dB above the limit of 8% PER (limit level is known from performance simulation as Eb/No for the current simulated channel, 200+ packets simulated to get the reference) Interferer level is set from dint simulated (P.d² is constant, and Tx power is same for Ref and for interferer) 2 or 3 independent UWB source interferers Interferer channel is a free space channel Modulation used is 2-PPM, Prp =5.4 ns, CR 1/3, 123 Mbps Simulation operation : dint is tuned to get the reference PER limit of 8% (only the WORST case ratio of distance : dref /dint is kept as result) Didier Helal and Philippe Rouzet, STM

May 2003 Simultaneously operating Piconets Multiple piconet interferers Simulation results P2 (3-7GHz) at Eb/No ~ 6.2 dB ! P1 for interferer ! Preliminary Figures Worst case ratio Dref/dint (= Near far factor) 2 Interferers 3 Interferers Ref is CM1 TBD Ref is CM2 Ref is CM3 (5 channels used) 50 (=10m/0.2m) 17 (=10m/0.6m) Ref is CM4 14 (=10m/0.7m) Didier Helal and Philippe Rouzet, STM

May 2003 Simultaneously operating Piconets Multiple piconet interferers Simulation results P1 (3-10GHz) at Eb/No ~ 6.2 dB Worst case ratio Dref/dint (= Near far factor) 2 Interferers 3 Interferers Ref is CM1 (5 channels used) 40 (=10m/0.25m) 13 (=10m/0.75m) Ref is CM2 Ref is CM3 50 (=10m/0.2m) 14 (=10m/0.7m) Ref is CM4 Didier Helal and Philippe Rouzet, STM

Channel Estimation Algorithm
May 2003 Channel Estimation Algorithm The channel response is estimated with the training sequence Coherent integrations (on the received pulses) reduces noise and ISI effects. Most of channel energy is recovered by so. SNR at RX is good enough to reduce PRP and to increase data rate. System is independent from transmitted pulse shape No need for Pulse Template Didier Helal and Philippe Rouzet, STM

channel decoding architecture
May 2003 channel decoding architecture Uncorrelates bit errors at the input of the decoder : C=code rate BTC=Turbo code block length. demapping and soft A priori per bit Probability calculations. Adds scalability Channel estimation depuncture channel decoder (Turbo decoder or Viterbi decoder) NPPM Correlations Deinterleaving BL=BTC/C descrambling APP calculations RF N-PPM (number of Pulse positions) soft values corresponding to each PPM position at Pulse Repetition Frequency. Didier Helal and Philippe Rouzet, STM

May 2003 Turbo code Latency is mainly due to the storage of one block into the channel de-interleaver. @110Mbps: 512/110e6~5us. @ 55Mbps: 512/55e6=10us. Complexity: RAM: bits. ~500 kGates Didier Helal and Philippe Rouzet, STM

Performance Indicators
May 2003 Coarse synchronization Hypotheses No clock jitter present No clock drift present Send at max power allowed by FCC PRP = 10.8 ns Superframe ~= 10 ms CM3 channels utilised Most proposed pulse shapes will do Dimension preamble sequence for worst conditions: m Performance Indicators False Alarm probability (PFA): a preamble is detected where there is none A target PFA ~ 10-4 is assumed Missed Detection probability (PMD): the preamble is not detected A target PMD ~ 10-4 is assumed Beacon training sequence length ~ overhead percentage ~ synchronization time Didier Helal and Philippe Rouzet, STM

Coarse Sync: Timeline First step: Preamble Detection
May 2003 Coarse Sync: Timeline First step: Preamble Detection Goal: search sequentially one sequence among 20 possible. Done over the first 120 repetitions of the QCH sequence. If piconet present and SNR >~ -7dB: Integration over 3 repetitions of the QCH sequence is enough. Sequence will be detected within 10 ms (at most 2 superframe beacons necessary). If piconet present but bad radio conditions: need to combine 4 or more QCH sequences to achieve detection. Second step: Alignment Goal: find end of beacon preamble. Done with aid of EOBP signature. Try to correlate with last 5 replicas of the beacon preamble: [+1 +1 –1 –1 +1]. Didier Helal and Philippe Rouzet, STM

Coarse sync: pulse comparison
May 2003 Coarse sync: pulse comparison PRP = 5.4 ns, L = 237, THR = 111 CM3 10 10 -1 10 -2 PMD 10 -3 P , no jitter P , 10ps jitter P3.1-7, no jitter P3.1-7, 10ps jitter P , 10ps jitter P3.1-5, no jitter P3.1-5, 10ps jitter P , no jitter 10 -4 10 -5 -10 -9.5 -9 -8.5 -8 -7.5 -7 -6.5 -6 -5.5 -5 SNR [dB] Didier Helal and Philippe Rouzet, STM

Channel estimation Simulation Results
May 2003 Channel estimation Simulation Results Loss due to reduction of training sequence length from 6s to 3s equals 1dB Didier Helal and Philippe Rouzet, STM

Pulse Repetition Period at 110Mb/s
May 2003 Pulse Repetition Period at 110Mb/s CR = Code Rate All PRP values in nanosecond Low order modulation preferred to minimize gate count/cost for low data-rate devices Didier Helal and Philippe Rouzet, STM

May 2003 Pulse Repetition Period at 200Mb/s CR = Code Rate All PRP values in nanosecond Low order modulation preferred to enable intermediate data-rate devices Didier Helal and Philippe Rouzet, STM

May 2003 Pulse Repetition Period at 480Mb/s CR = Code Rate All PRP values in nanosecond Larger PRP preferred to avoid too small inter-position delay ! Didier Helal and Philippe Rouzet, STM

Pulse Repetition Period at 1Gb/s
May 2003 Pulse Repetition Period at 1Gb/s CR = Code Rate All PRP values in nanosecond Larger PRP preferred to avoid too small inter-position delay in PPM Didier Helal and Philippe Rouzet, STM

Manufacturability Architecture matches full CMOS implementation
May 2003 Manufacturability Architecture matches full CMOS implementation Low cost, single chip product Using today’s silicon technology Simulation proven hardware architecture SystemC model used (synthesized model available) Performance and gate complexity estimated from chipset and FPGA implementation Demonstrator in development 0.13 m CMOS technology Size and form factor Single chip silicon allows small size like PC card, memory stick, …, and would be usable in portable devices Didier Helal and Philippe Rouzet, STM

Power consumption Low power Architecture
May 2003 Power consumption Low power Architecture Minimum RF front end (low power with respect to alternative architecture) Demodulation processed in digital Channel estimation gates (~2/3 of demodulation count) used only during frame preamble (<10% of time) Typical clock frequency is PRP (only RF front end is high speed) Digital power consumption will scale as Moore’s law in future technology Didier Helal and Philippe Rouzet, STM

Scalability Low data rate (LDR) permits lower power, lower complexity
May 2003 Scalability Low data rate (LDR) permits lower power, lower complexity Channel estimation power cost can be reduced for low data rate (need less path, and shorter sequence) Simple modulation (polarity) compatible with HDR devices High data rate scalable easily ST expect data rate of up to 750 Mbps shortly 1 Gbps theoretically possible for high-end products Didier Helal and Philippe Rouzet, STM

May 2003 Location awareness Relative location (distance between stations) available at almost no cost Thanks to channel estimation principle 2 performance levels possible (implementor choice) A few decimeters accuracy (simple processing) A few centimeters accuracy (signal processing of estimated channel) Minimal additional hooks in MAC Didier Helal and Philippe Rouzet, STM

May 2003 Multipath immunity Channel estimation principle allows capture of most received energy Equivalent to infinite rake architecture Excellent performance in worst multipath environment Pulse shape/spectrum independent The receiver architecture don’t need a-priori knowledge on pulse shape (this is why it is so easy to match specific regulation) Dense multipath channel with overlapping pulses don’t degrade performance Didier Helal and Philippe Rouzet, STM

March 2003 doc.: IEEE 802.15-3/139r1 May 2003 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [STMicroelectronics.

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March 2003 doc.: IEEE 802.15-3/139r1 May 2003 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [STMicroelectronics.

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Presentation on theme: "March 2003 doc.: IEEE 802.15-3/139r1 May 2003 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [STMicroelectronics."— Presentation transcript:

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About project

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