1. Chapter 3 Hardware/Software Design Flows and Development Environments
Professor Ruei-Xi Chen
SJU/CSIE

2. Outline 3.1 Software Development Toolchain 3.2 Software Compilers
3.3 Hardware Design Flow
3.4 FPGA Implementation for Hardware Design

3. 3.1 Software Development Toolchain
3.2 Software Compilers
3.3 Hardware Design Flow
3.4 FPGA Implementation for Hardware Design

4. 3.1 Embedded System Development Environment
Target Device
Embedded System Target Board
Host System
Cross-Development Toolchain
Connections for Host and Target
JTAG: Parallel port for download bootloader
UART: Serial port for target terminal (minicom)
Ethernet: tftp & NFS services protocols
JTAG
RS232
Ethernet
Target
Host

5. 3.1 What is a ToolChain?
A toolchain is the set of computer programs (tools) that are used to create a product
The tools may be used in a chain
It is used widely to refer to any set of linked development tools
A software development toolchain consists of a number of components:
Text editors
For entering source code
Compiler and linker
To transform the source code into an executable program and libraries to provide interfaces to the operating system
Debuggers

6. 3.1 How about Building a Toolchain?
How about building a cross-development toolchain?
It is a difficult and painful task!
It can take days or weeks!
Lots of details to be learned in building components, such as:
Need to build gcc twice
One for the gcc
Another for the compiler which is needed for the C library
Lots of decisions to be made, such as:
Versions of glibc
Configuration of your platform
etc.

7. 3.1 Suitability of Precompiled Toolchain
You can get one precompiled toolchain from several locations...
You just need to know where they are!
Cautions!
Toolchains are not relocatable
Install them in a fixed location if they were built for that location
Such as: /usr/local/<arch>
Make sure that the toolchain you picked is just suits for what you need:
C libraries
Compilers
The library versions...

8. 3.1 What is the GNU Toolchain?
The programming tools produced by the GNU project
For programming both applications and operating systems
A vital component in Linux kernel development
A standard tool for developing software for embedded systems
Such as the ARM embedded systems

9. 3.1 Projects that Included in the GNU Toolchain
GNU make:
Build and compilation automation
GNU Compilers:
gcc, the well known C,C++ complier supported variable platforms
GNU Binutils including:
Assembler (as), linker (ld) and other binary file tools
GNU Debugers:
gdb, the command line interactive debugging, including remote debugging
Libraries:
glibc, the GNU C runtime library

10. 3.1 Selection of ARM Linux Toolchain
arm-linux build of the GNU compiler
Cross-compilation from Unix (Linux or Solaris) or Windows host
Snapshots available at
Choice of C library
Glibc – standard GNU C library
uCLibc
Newlib – smaller library
Decide on which library to use when building the cross compilation tool chain

11. 3.1 Why Linux? Linux is a Unix clone written from scratch
by Linus Torvalds with assistance from a loosely-knit team of hackers across the Net
Linux aims towards POSIX compliance
Linux has all the features you would expect in a modern fully-fledged Unix, including:
true multitasking
virtual memory
shared libraries
demand loading
shared copy-on-write executables
proper memory management
TCP/IP networking.

12. 3.1 ARM Embedded Linux Cross Dev-Environment
Solution 1:
Linux/UNIX Workstation:
(1) Host Linux: vsftpd, sshd, vim, make, …
(2) Target OS (Linux/uClinux source), and
arm-elf-toolchain for linux, [and IDEs]
Solution 2:
Windows-based Virtual Machine :
(1) Windows OS (XP,…), [Hyper Terminal],
(2) VMware + Virtual Machine OS and Drivers [RH9/Fedora/Debian/Symbian…]: minicom, tftp, vim, make, …
[or using Cygwin]
(3) Target OS (Linux/uClinux source), and
arm-elf-toolchain for linux, [and IDEs]
Embedded Target Boards

13. 3.1 Target System Connections
Printer Cable
for downloading bootloader
JTAG
Host
RS232 Cable (SUB9 male-to-male) used for target terminals
Embedded
Target
ARM
RS232
Null
Modem
RS232
(DTE)
DCE
(DTE)
Ethernet Cable
for downloading image files

14. 3.1 ARM Cross-Development Toolkit
C Source
Assembler
C Libraries
ASM Source
.aof
Object
Libraries
.aif
debug
ARMsd
Development
board
ARMulator
System model
C Compiler
Linker

15. 3.1 System Requirement Hardware Host : PC Target : XSBase255 Software
OS : Linux or Virtual Machine (Fedora, ...)
Original Packages (*.tar.gz) Directory
/home/Co_design/Lab_2/Kernel
rmk7-pxal-XSBase255B
/home/Co_design/Lab_2/Toolchain
hybus-arm-linux-R1.1.tar.gz
Embedded Software Directory for:
Kernel, Cross-Toolchain, Work, Image

16. 3.1 Connections of PXA-255 Dev-Environments
JTAG Interface
TMS
Test Mode Selection
TCK
Test Clock
TDO
Test Data Out
TDI
Test Data In
nTRST
JTAG Reset
System Reset
Intel® XScale Family

17. 3.1 PXA-255 Dev. ToolKit Bootloaders Images: “x-boot255”
Download tools: Jflash-XSBASE
Kernel packages
“ root.tar.gz”
Filesystems
“root_Xscale.tar.gz”
Toolchain packages
“hybus-arm-linux-R1.1.tar.gz”
BOOTP, TFTP and NFS Service
“bootp i386.rpm”
“tftp-server i386.rpm”

18. 3.1 PXA-255 Development Procedures
Download the bootloader to the Target board
./Jflash-XSBASE x-boot255
Installation of Toolchain
tar xvzf hybus-arm-linux-R1.1.tar.gz
Adding Auto-paths and sourcing it
Setup kernel
tar xvzf root.tar.gz
Kernel Configuration
Setup Services (Install BOOTP, TFTP, NFS services)
Build Filesystems
tar xvzf root_Xscale.tar.gz
Download the Linux Kernel and Filesystem Image to the Target (tftp)
Build Applications
Edit Applications, and make
Run Applications via UART, tftp, or NFS protocols

19. 3.1 File Directories Applications Original Bootloader Image: x-boot255
Original Toolchain Package:
hybus-arm-linux-R1.1.tar.gz
Target kernel
(Installation)
Original Kernel Package:
root.tar.gz
Toolchain
(Installation)
NFS directory for target sharing files
Login location

20. 3.1 Download Bootloader Download Bootloader for XSBase255
The execution file for downloading bootloader’s via JTAG port
Jflash-XSBASE
The bootloader image.
x-boot255
Command to Download the Bootloader
./Jflash-XSBASE x-boot255

21. 3.1 Steps to Install Toolchain for XSBase255
Original Toolchain Package:
hybus-arm-linux-R1.1.tar.gz
Toolchain Folder After Installation
/usr/local/hypus-arm-linux-R1.1/
Steps of installation
Duplicating Files
cp hybus-arm-linux-R1.1.tar.gz /usr/local/
Unpacking Files
cd /usr/local/
tar xvzf hybus-arm-linux-R1.1.tar.gz
Adding Auto-paths
vi ~/.bash_profile
Add a new line: “PATH=$PATH:/usr/local/hybus-arm-linux-R1.1/bin”
Exit and save .bash_profile,
Sourcing, type: source ~/.bash_profile

22. 3.1 Install Kernel The original Kernel Package 2.4.18-root.tar.gz
Unpack the XSBase255 kernel file, typing:
tar xvzf root.tar.gz
The kernel folder built after installation
rmk7-pxal-XSBase255B

23. 3.1 Network Environment Using dual physical LAN cards
And using dual virtual LAN cards

24. 3.1 Virtual Machine Networking
Bridged Networking
Network Address Translation (NAT)
Host-Only Networking
Sophisticated Virtual Networks

25. 3.2 Software Compilers 3.1 Software Development Toolchain
3.3 Hardware Design Flow
3.4 FPGA Implementation for Hardware Design

26. 3.2 Software Programs and Compilers
Source code
The collection of program files
Any sequence of statements and/or declarations written in some human-readable computer programming language
Languages
High level languages (source code)
C/C++, Java, BASIC, …
Lower level languages
Assembly language (source code)
The machine dependent mnemonic languages
Machine language (binary code)
Compilers
Programs that translate source code from a high level language to a lower level language
Interpreters
Execute code from the human readable form

27. 3.2 Cross-Compilers
Generate another processor’s executable code from a processor platform, such as:
GNU C Compiler for ARM generates ARM executable code from x86 platform
gcc : arm-linux-gcc (arm-elf-gcc)
g++ : arm-linux-g++ (arm-elf-g++)
ar : arm-linux-ar (arm-elf-ar)
strip : arm-linux-strip (arm-elf-strip)
GCC: GNU Compiler Collection
Cross compilers are used to generate software that can run on computers with a new architecture or on special-purpose devices that cannot host their own compilers

28. 3.2 Embedded Software Design Flow
Host IDE
Open Source
Edit Source
.c, .h, .s
Cross Compiler
& Assembler .s .o
Runtime
Libraries .o
Linker
Executable file
Target Board
Debugger

29. 3.2 Stages of Compilation Preprocessing
Converts all preprocessing statements into true C code
(such as #include, #define and #ifdef)
Compiling
Converts preprocessed input into assembly language output
Assembling
Convert the assembly language code into relocatable binary object outpu
Linking
Link the relocatable object file into an executable output file

30. 3.2 Four Compilation Stages of GNU C Compiler
arm-elf-gcc Execution
Stages of
Compilation
(arm-elf-gcc)
Input Files
Output Files
Preprocessing
(cpp)
Compiling
(-gcc)
Assembling
(arm-elf-as)
Linking
(arm-elf
-ld)
Input file:
Output file:
stage-opt:
C code (.c)
Preprocessed (.i) -E
Preprocessed (.i)
Assembler (.s) -S
Assembler (.s)
Object (.o) -c
Object (.o)
Executable (.elf)
(none)

31. 3.2 ARM Software Development Concept
IDE Environment
ARM Tools, Libraries, Host/Target
ARM©
ASM
Value-Add Extensions
Embedded RTOS, Drivers, Stacks, Services
DSP
Others
C/C++

32. 3.2 Commands of GNU Compiler for ARM
Use the GNU Compiler for the ARM:
arm-elf-gcc [stage-opt] [other-opts] -mcpu=arm7tdmi in-file -o out-file
To convert C source code to a binary object file:
arm-elf-gcc -c -O2 -g -mcpu=arm7tdmi filename.c -o filename.o
To convert multiple binary object files into an executable file (the general case):
arm-elf-ld filename1.o filename2.o … -o filename.elf
To convert C source code to an executable file (for use with Insight only, not Komodo):
arm-elf-gcc -O2 -g -mcpu=arm7tdmi filename.c -o filename.elf
To convert C source code to assembly language source code:
arm-elf-gcc -S -fverbose-asm -mcpu=arm7tdmi filename.c -o filename.s

33. 3.2 Compilation with the file name suffix
.c C source; preprocess
.C C++ source; preprocess, compile, assemble
.cc C++ source; preprocess, compile, assemble
.cxx C++ source; preprocess, compile, assemble
.m Objective-C source; preprocess, compile, assemble
.i Preprocessed C; compile, assemble
.ii Preprocessed C++; compile, assemble
.s Assembler source; assemble
.S Assembler source; preprocess, assemble
.h Preprocessor file; not usually named on command line
Other An object file to be fed straight. Any file name with no recognize suffix is treated this way

34. 3.2 Debugging Options -g
Include debugging information in the relocatable binary object or executable output file
-Wall
Warn about potential bugs and questionable constructs that may exist in your C code
Highly useful; use often!
-fverbose-asm
This causes the compiler to insert comments into the output
To help you understand the resulting assembly language code

35. 3.2 Linux - Debugging Kernel debug
With JTAG connection use commercial debugger for early kernel bring up
Use Kgdb to debug kernel
Commercial debuggers offer additional features to debug and profile the Linux kernel:
Choice of halted/running system debug
Profiling
Application debug
Use GDB over serial or networking link
Either natively or in cross-debug environment
Choice over graphical front-end used
Use commercial debuggers for debugging over JTAG

36. 3.2 Test GCC Cross Compiler
Download test.tar.gz
Extract & Make
tar zxf test.tar.gz
cd test
make
file test.elf
What is the test.elf?
ELF 32-bit LSB executable, ARM, version 1 (ARM), statically linked, not stripped

37. 3.3 Hardware Design Flow 3.1 Software Development Toolchain
3.2 Software Compilers
3.3 Hardware Design Flow
3.4 FPGA Implementation for Hardware Design

38. 3.3 Top-Down Design Methodology

39. 3.3 Design Domain

40. 3.3 SoC HW/SW Co-Design Fundamentals
Based on parallel hardware and software development
Use the pre-built architecture platform
Construct of generic hardware and software IP blocks
IPs have already been characterized and debugged
The key steps
The hardware and software partitioning
For optimization of the application-specific system
Use the existing hardware/software IP blocks as a guide

41. 3.3 FPGA Design Flows Xilins ISE Design Flow
Altera Quartus-II Design Flow

42. 3.3 Xilinx ISE Design Flow

43. 3.3 Create An ISE Project Create a project
Create files and add them to the project, including a user constraints (UCF) file
Add any existing files to the project
Assign constraints such as:
timing constraints
pin assignments
area constraints

44. 3.3 Functional Verification
Before synthesis, run behavioral simulation
Also known as RTL simulation
After Translate, run functional simulation
Also known as gate-level simulation
Using the SIMPRIM library
After device programming, run in-circuit verification

45. 3.3 Design Implementation
Implement design, steps:
Translate
Map
Place and Route
Review generated reports to improve design:
Process properties
Constraints
Source files
Synthesize and implement the design again until design requirements are met.

46. 3.3 Timing Verification
Run static timing analysis at the following points in the design flow:
After Map
After Place & Route
Run timing simulation at the following points in the design flow:
After Map (for a partial timing analysis of CLB and IOB delays)
After Place and Route (for full timing analysis of block and net delays)

47. 3.3 Xilinx Device Programming
Create a programming file (BIT)
To program your FPGA
Generate a PROM, ACE, or JTAG file
For debugging
Or to download to your device
program the device
Use iMPACT
Use a programming cable

48. 3.3 Altera FPGA Design Flow

49. 3.3 Design Steps for a Quartus II Project
Run the New Project Wizard
Run the Timing Wizard (Assignments Menu)
Compile the Design (Processing Menu)
Verification
Simulation
FPGA Configuration
Emulation

50. 3.3 Run the New Project Wizard
Specify:
Project directory, name, and top-level entity
Project design files
Altera device family
Device (or device information for automatic device selection)
Other EDA tools to be used
Review:
project settings

51. 3.3 Run the Timing Wizard Specify requirements:
For overall circuit frequency (fMAX)
Or for one or more clock signals
Enter project-wide system requirements:
set-up time (tSU)
hold time (tH)
clock-to-output time (tCO)
and pin-to-pin time (tPD)
Specify default external delays to and from device pins
Enter settings to control timing analysis and timing-driven compilation.

52. 3.3 Compile the Design Compile the design:
Choose one of the following methods:
Choose Start Compilation (Processing menu)
Use the shortcut on the menu toolbar
Click Start from the Compiler Tool (Processing menu)
Refer to the Compilation Report window to view information on:
compiler settings
resource usage
compilation equations

53. 3.4 FPGA Implementation for Hardware Design
3.1 Software Development Toolchain
3.2 Software Compilers
3.3 Hardware Design Flow
3.4 FPGA Implementation for Hardware Design

54. 3.4 A Typical Digital System

55. A view inside the controller and datapath controller and datapath
3.4 The FSMD Design Model
FSMD: FSM with Datapath
A view inside the controller and datapath
controller and datapath …
controller
datapath
state
register
next-state
and
control
logic
registers
functional
units
controller
datapath …
external
control
inputs
control outputs
data
outputs
FSMD
Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

56. 3.4 The ASM Method ASM: Algorithmic State Machine
Techniques for designing finite state machines
Advantages:
reduces design errors
produces robust designs
self documenting
easy to automate
Design flow
System Specification
ASM Chart Definition
Assignment of State Codes
FSM Specification
URL:

57. 3.4 Three Symbols for the ASM Chart
ASM Utilizes the following three symbols:
STATE BOX
INPUT BOX
CONDITIONAL OUTPUT BOX

58. 3.4 Case Study: An 8 bit Multiplier Unit Controller
Implementing the controller of an 8 bit multiplier unit as a finite state machine
System Specification

59. 3.4 System Specification
Datapath Design
ASM Chart Definition

60. 3.4 ASM Table vs FSM Code
(a) ASM Table
(b) FSM VHDL Code

61. 3.4 Run the New Project Wizard
File New Project Wizard

62. End of
Chapter 3