1. EE 22442 - Embedded Systems Fall 2015
Chapter Eleven:
Data acquisition and manipulation
EE Embedded Systems Fall 2015
Belal H. Sababha, Ph.D.
Assistant Professor of Electrical & Computer Engineering
Computer Engineering Department
King Abdullah II Faculty of Engineering
Princess Sumaya University for Technology
Amman, 11941, Jordan
Phone: ext. 222
Web:

2. Introduction In the chapter we will learn about:
The main features of a data acquisition system.
The characteristics of an analog-to-digital converter.
The characteristics of the 16F873A analog-to-digital converter.
How the 16F873A analog-to-digital converter can be applied.
Some simple data manipulation techniques.
The use of comparators and the 16F873A comparator capability.

3. The main idea – analog and digital quantities, their acquisition and use

4. The data acquisition system

5. The analog-to-digital converter
An ADC determines a digital output number that is equivalent of an input voltage.
The design of such circuits is a non-trivial task.
Many very different ADC circuits have been developed, targeted towards different applications.
Some, like the dual ramp ADC, are slow but with very high accuracy, and useful for precision measurements such as digital voltmeters.
Others, like the Flash converter (not to be confused with Flash memory technology), are fast but of lesser accuracy, and are used to convert high-speed signals such as video or radar.
Others, like the successive approximation ADC, are of medium speed and medium accuracy, and useful for general-purpose industrial applications.
This is the type most commonly found in embedded systems. Descriptions of how this type of ADC circuit works can be found in most electronics textbooks [see Ref. 1.1].

6. ADC Characteristics
An ADC is characterized principally by the following features:
Conversion characteristics
Conversion speed
 Digital interface

7. Conversion characteristics
Input Range and Voltage reference
Output Range and n-bit ADC
Step Size
Resolution

8. Conversion characteristics …cnt’d
Input voltage infinitely variable.
Fixed Number of Output values.
Min and Max Values:
Input (Analog) : e.g V
Output (Digital): e.g. 0x00 – 0xFF
For an n-bit ADC, the maximum output value will be ((2^n) – 1
The input range (0-5V or -5V – 5V) usually relates in a direct way to the value of the voltage reference, which forms part of the ADC.
The higher the number of output bits, the higher will be the number of output steps and the finer is the conversion.
Step Size, Resolution: This is the amount by which the input has to change to go from one output value up to the next.
In the diagram, the resolution is the width of one step in the conversion characteristic.

9. Conversion speed
The time it takes an ADC to do its work is called the conversion time.
A slow ADC, with a high conversion time, will only be able to convert low-frequency signals - Nyquist’s criterion must always be satisfied.
The conversion time of an ADC defines which type of signal it can be used to convert.
High-accuracy ADCs generally take longer to complete a conversion.

10. Digital interface
The digital interface is made up of the control signals and the data output.
A signal to the ADC that causes a conversion to start.
When the conversion is complete, the ADC signals that completion with an output signal.
A further signal causes the ADC to output its data.
Depending on the type of interface required, the ADC has a parallel or serial data interface.
An ADC always works in conjunction with a ‘voltage reference’.
This is a device or circuit that maintains a very precise and stable voltage, and is based around a zener diode or a band-gap reference.
The ADC effectively uses the voltage reference as the ruler with which it measures the incoming voltage.
An ADC is only as good as its voltage reference.
For accurate A-to-D conversion, a good ADC must be used with a good reference.

11. Signal conditioning – amplification and filtering
The input voltage should traverse as much of its input range as possible, without exceeding it.
Most signal sources, say a microphone or thermocouple, produce very small voltages. Therefore, in many cases amplification is needed to exploit the range to best effect.
Voltage level shifting may also be required, for example if the signal source is bipolar while the ADC input is unipolar (voltage is positive only).
If the signal being converted is periodic, then a fundamental requirement of conversion is that the conversion rate must be at least twice the highest signal frequency. (Nyquist sampling criterion).
Anti-aliasing filtering may therefore be required to ensure that the Nyquist criterion is satisfied.

12. Optimal Voltage Range for A/D Conversion
Needs a low reference voltage (VRL) and a high reference voltage (VRH) in performing A/D conversion.
VRL is often set to ground level.
VRH is often set to VDD.
Most A/D converter are ratiometric, i.e.,
A 0 V (or VRL) analog input is converted to the digital code of 0.
A VDD (or VRH) analog input is converted to the digital code of 2n – 1.
A k-V input will be converted to the digital code of k  (2n – 1)  VDD.
The A/D conversion result will be the most accurate if the value of analog signal covers the whole voltage range from VRL to VRH.
The A/D conversion result k can be translated back to an analog voltage VK by the following equation:
VK = VRL + (range  k)  (2n – 1)

13. Example:
Example: Suppose that there is a 10-bit A/D converter with VRL = 1 V and VRH = 4V. Find the corresponding voltage values for the A/D conversion results of 25, 80, 240, 500, 720, 800, and 900. Solution: range = VRH – VRL = 4V – 1V = 3V V(25) = 1 V + (3  25)  (210 – 1) = 1.07 V V(80) = 1 V + (3  80)  (210 – 1) = 1.23 V V(240) = 1 V + (3  240)  (210 – 1) = 1.70 V V(500) = 1 V + (3  500)  (210 – 1) = 2.47 V V(720) = 1 V + (3  720)  (210 – 1) = 3.11 V V(800) = 1 V + (3  800)  (210 – 1) = 3.35 V V(900) = 1 V + (3  900)  (210 – 1) = 3.64 V

14. Scaling Circuit
Some transducer has the an output voltage in the range of 0 ~ VZ, where VZ < VDD.
VZ can be much smaller than VDD.
When VZ is much smaller than VDD, the A/D conversion result cannot be accurate.
The solution to this problem is to use an scaling circuit to amplify the transducer output
to cover the whole range of 0 V to VDD.
AV = VOUT  VIN = (R1 + R2)  R1
= 1 + R2/R1
Example 12.2 Choose appropriate values of R1 and R2 in Figure 12.6 to scale a voltage
in the range of 0~200mV to 0~5V.
Solution: AV = 1 + R2/R1 = 5V / 200mV = 25
R2/R1 = 24
Choose R1 = 10 K ohm and R2 = 240 K ohm to achieve the desired ratio.

15. Voltage Translation Circuit
Some transducer has output voltage in the range from V1 to V2 (V2 > V1).
The accuracy of the A/D conversion will be more accurate if this voltage can be scaled and shifted to 0 ~ VDD.
The circuit shown below can shift and scale the voltage from V1 to V2 to the range of 0~VDD.

16. Example
Example: Choose appropriate resistor values and the adjusting voltage so that the circuit shown in previous slide can shift the voltage from the range of –1.2 V ~ 3.0 V to the range of 0V ~ 5V.
Solution: Applying the Equation on the lower and higher ends of the range:
𝑉 𝑂𝑈𝑇 = 𝑅 𝑓 𝑅 1 𝑉 𝐼𝑁 − 𝑅 𝑓 𝑅 2 𝑉 1
0 = -1.2  (Rf/R1) – (Rf/R2)  V1
5 = 3.0  (Rf/R1) – (Rf/R2)  V1
By choosing R0 = R1 = 10 KΩ, R2 = 50 K Ω, Rf = 12 K Ω,
and V1 = -5V, one can translate and scale the voltage to the desired range.

17. The analog multiplexer
In case of multiple inputs, an analog multiplexer is used.
Having multiple ADCs, is costly and space-consuming.
The multiplexer acts as a selector switch, choosing which input out of several is connected to the ADC at any one instant.
The multiplexer is built around a set of semiconductor switches.
The semiconductor switch is an imperfect device.
When switched ‘on’, it has internal series resistance, which can range from tens to thousands of ohms. This can impact on the data acquisition process, as we shall see.

18. Sample and Hold
Because most ADCs are unable to accurately convert a changing voltage, a ‘Sample and Hold’ (S&H) circuit is often found.
This takes a sample of the voltage, like a snapshot, and holds it steady for the duration of the conversion.
A circuit of a simple but practical S&H is shown in Figure 11.3.
At its heart are just a semiconductor switch and a capacitor. When the switch is closed, the capacitor charges up to the input voltage VS. At this moment, ideally Vo = Vc = Vs

19. Acquisition time
Problem with the shown circuit: There is a series resistance in the signal path. This is represented by the resistor in the circuit.
When the switch closes, therefore, the capacitor voltage Vc does not take on the signal voltage immediately, but rises towards it exponentially.
The voltage rise is given by: Vc = Vs {1- exp(t/RC)}
Our interest from a data acquisition point of view is to ensure that the voltage has risen sufficiently close to its final value with the switch closed, before the switch is opened (the signal is then ‘held’) and a conversion allowed to start.
The time that Vc (and hence Vo) takes to reach a value deemed to be acceptable is called the ‘acquisition time’.

20. Timing and microprocessor control

21. Data acquisition in the microcontroller environment
Embedded systems need ADCs, so it is natural to expect to find an ADC integrated onto a microcontroller as one of its peripherals.
ADCs and microcontrollers do not make happy bedfellows.
To operate to a good level of accuracy, an ADC needs a quiet life (electronically speaking), with excellent and clean power supply and ground, and freedom from electromagnetic interference.
A microcontroller, being a digital device, tends to corrupt its power supply and ground with a voltage spike on every switching edge.
As a consequence, with all its intensive internal digital activity, it radiates a smog of local interference.
Therefore, to integrate an ADC onto a microcontroller is at best a compromise and high accuracy is not usually possible.
ADCs are widely available in the microcontroller environment, with many microcontrollers having an on-chip ADC. These are mostly 8- or 10-bit.

22. The PIC 16F87XA ADC module
The input multiplexer, seen to the right of the diagram, has five channels for the 16F873A and ’F876A, and eight for the 16F874A and ’F877A.

23. Controlling the ADC
The ADC is controlled by two SFRs, ADCON0 (Figure 11.7) and ADCON1 (Figure 11.8).
The result of the conversion is placed in two further SFRs, ADRESH and ADRESL.
Other SFRs also have an important impact on the ADC.
These include TRISA and (for the 40-pin devices) TRISE.
Any bits used for analog input must be set as inputs in these.
Registers PIR1 and PIE1, which contain the ADC interrupt flag and interrupt enable bits respectively, are also used.

26. Control sequence Switching on Setting the conversion speed
Configuring the input channels and selecting the voltage reference
Starting a conversion and flagging its end
Formatting the result

27. Switching on
The ADC is switched on and off by the ADON bit of ADCON0. Switching it off when not needed offers a slight power-saving advantage.

28. Setting the conversion speed
Operation of the 16F87XA ADC is governed by the ADC clock, which has a period TAD.
A full 10-bit conversion takes around 12 TAD cycles, depending slightly on which clock source is chosen.
The user can select the clock frequency from a number of options.
There is an upper limit to the clock frequency.
For the 16F87XA the minimum clock period for correct operation is 1.6 us (Electrical Characteristics), or a frequency of 625 kHz. This implies a fastest conversion time of 19.2 us.
If conversion is too slow, charge leaks from the storage capacitance and the conversion becomes inaccurate.
Best practice is to set the ADC clock frequency such that it has a period equal to or just more than 1.6 us.
Selection of the ADC clock source is controlled by bits ADCS2 in ADCON1, and ADCS1 and ADCS0 in ADCON0.
Various divisions of the main clock frequency are possible.
There is also a dedicated RC oscillator which can be chosen. This has a typical period of 4 us, but may range from 2 to 6 us.
If the system clock is fast (> 500 KHz), it is usually appropriate to use it to derive the clock source. If the system clock is slow, however, it is better to use the RC oscillator.

29. Configuring the input channels and selecting the voltage reference
The way the input port bits are used is defined by the setting of bits PCFG3 to PCFG0 of ADCON1.
Any port pin that is to be used as an analog input must be set as an input in its TRIS register.
Selecting the input channel: CHS2 to CHS0 in ADCON0

30. Starting a conversion and flagging its end
A conversion is initiated by setting bit GO/DONE in register ADCON0.
When the conversion is complete the bit is returned to zero by the hardware.
Completion of conversion is also signaled by an ADC interrupt flag ADIF.
Completion of conversion may therefore be detected by testing either of the bits: GO/DONE or ADIF, or by enabling the interrupt and responding to it in an ISR.

31. Formatting the result
The result of the conversion is placed in registers ADRESH and ADRESL.
The result can be left justified, in which case the eight most significant bits appear in ADRESH.
This is useful if only an 8-bit result is required, as the contents of ADRESL can then be ignored.
In most other cases a right justified result will be the more useful.
The formatting is controlled by bit ADFM in ADCON1.

32. Formatting the result … cnt’d

33. Repeated conversions
When a conversion is complete, the converter waits for a period of 2 × TAD before it is available to start a new conversion cycle.
Once this time is up, either the same input channel may be converted again, or a new one (which may already have been selected) may be converted.
A best possible conversion time of 28.5 us was calculated in Section If a period of 2 × TAD is added to this, i.e. 3.2 us for fastest possible, then the complete conversion cycle time becomes 31.7 us. If successive conversions are intended, this implies a maximum sampling rate of around 30 kHz. Note, however, that this figure takes no account of software overheads, which would tend to slow the conversion rate.

34. Trading off conversion speed and resolution
The conversion times deduced above are not particularly fast by today’s standards and there will be occasions when a faster conversion time is needed.
One option is to use an external ADC.
Another is to consider whether the full 10-bit resolution is needed.
If it is not, then the conversion time can be reduced.

35. Some simple data manipulation techniques
Fixed- and floating-point arithmetic
Binary to Binary Coded Decimal conversion

36. Live Demo Example and Live Demo void ATDinit(void);
unsigned int ATDread(void);
void main() {
unsigned int k;
TRISD = 0; // PORTD is output
TRISB = 0; // PORTB is output
ATDinit(); // initialize the ATD module
while(1){
k = ATDread();
PORTD= k;
PORTB= k>>8; }
void ATDinit(void){
ADCON1 = 0xF0; // right justified, all channels are analog
TRISA= 0xFF; // Port A is input
ADCON0 = 0x59; //prescale 16, channel3, dont start conversion, power on ATD
unsigned int ATDread(void){
ADCON0 = ADCON0 | 0x04; // set the GO bit, start the conversion
while(!(ADCON0 & 0x04)); // wait until the GO/DONE bit is reset, the ATD reading is ready
return ((ADRESH<<8)|(ADRESL));
Live Demo
Example and Live Demo