1. Design of a Diversified Router: Memory Usage
John DeHart

2. LC: Notes on Memory Usage
3 SRAM Channels of 8MB each per NP
3 RDRAM Channels 0f 256MB  768 MB per NP
Shared between XScale and Microengines.
bit words of Local Memory per MicroEngine
Parameters:
N: Max number of packets in the system at any given time.
M: Max number of queues that need to be supported
BatchSize: Number of slots in Scheduling Data Structure Segments (8 for now)
Data Structures Stored in SRAM:
Buffer Descriptors
32 Bytes each
Number needed: N
IXP Queue Descriptors
16 Bytes each
Number needed: M
QM Queue Data (QLen, Weight, Threshold)
12 Bytes each
Scheduling Data Structure Segments:
BatchSize*8 + 4B (address) + 4B (pointer to next) + 1 Bytes each
Number needed: (M/8) + x
Where x is the number of extra/spare needed to operate alogorithm
X <= 10 is probably sufficient
Data stored in DRAM:
Packet Buffers
2KB each
SRAM Adr(32b)
Next Ptr(32b)
QID(20b)
Credit(32b)
QID
credit
QID
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QID
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QID
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QID
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QID
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QID
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3. Notes on Memory Usage
1 SRAM Channel for IXP Queue Descs, QM Queue Data and Scheduling Data Structure:
16*M + 12*M + ((M/8)+10)*(72) <= 8MB (0x = )
28*M + 9M <= 8MB ( )
37*M <=
M <=
So, lets say we will support 128K Queues (131071)
17 bits of QID gives us a range of 0 –
1 SRAM Channel for Buffer Descriptors
32*N <= 8MB (0x = )
N <= (0x40000)
Max of 256K packets in the system
1 SRAM Channel still free
On NPE this would be used for:
MR specific data region
MR configuration data
Etc.
DRAM usage for 256K Packets:
256K * 2K per buffer = 512 MB
Out of 768MB available.

4. Local Memory Usage What Blocks make use of Local Memory?
Specifically what blocks access tables in Local Memory that are updated by the Control Plane?

5. Extra
The next set of slides are for templates or extra information if needed

6. Text Slide Template

7. Image Slide Template