1. EEL 3705 / 3705L Digital Logic Design
Fall 2006 Instructor: Dr. Michael Frank
Lecture Module #3: Lab #1 Prep & Intro. to Boolean Algebra
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

2. Topics for Today (Fri. 1/12)
Administrivia:
“Reading Assignment #1” has been posted
Due Friday of next week.
Lab Assignment #1 has been posted.
YOU MUST COMPLETE THE PRE-LAB BEFORE LAB!
HW#1 will be posted shortly.
Homeworks are generally due 1 week after they are assigned.
Today’s Lecture:
Preparation for Lab #1
Creating & simulating logic gates in Quartus
Topic #2, Combinational Digital Logic
Subtopic 2.2. Design of combinational logic circuits
Analytical combinational design
Boolean algebra
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M. Frank, EEL3705 Digital Logic, Spring 2007

3. M. Frank, EEL3705 Digital Logic, Spring 2007
Lab #1 Prep
Creating and Simulating Basic Logic Gates in Quartus, Selecting pins for the MAX 7000 chip
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M. Frank, EEL3705 Digital Logic, Spring 2007

4. M. Frank, EEL3705 Digital Logic, Spring 2007
Lab #1 Assignment
Given: A 1-paragraph description of a (very simple) design scenario (“design a controller for a Smoke Alarm System”),
Your task is to go through a complete structured engineering process for this design problem…
This includes the following steps:
In Pre-Lab:
Define the design context & detailed requirements
Create a top-level design for your controller
Create detailed designs for its components (very simple in this case)
Create and execute a simulation testing plan
Create a plan to build and test a prototype design
Write all of the above up as a structured, professional engineering document
In the actual lab, all you need to do is:
Execute your plan for prototype construction & testing
Record the results in your lab notebook
At home later, add sections on your results & their interpretation to your pre-lab report to make your lab report
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

5. Top-Down Design Process
This assignment is an example of a “top-down” design process
Widely used for large design projects in industry
In such a process,
You define your system-level requirements,
Then create a system-level design that breaks down the whole system into its subsystems,
Then define the subsystem requirements,
Then create a top-level design for each subsystem, breaking it down into sub-sub-systems or components,
Then define the component requirements,
Then design the individual components…
(There may be additional levels of subsystems/components as needed.)
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M. Frank, EEL3705 Digital Logic, Spring 2007

6. M. Frank, EEL3705 Digital Logic, Spring 2007
Design Scenario
Design a logic circuit to implement a building smoke alarm system.
The building is to be protected by a smoke alarm system that comprises two smoke detectors, a sprinkler, and an automatic telephone dialer that calls the fire department. The sprinkler is to be activated if either smoke detector detects smoke, and the fire department should be called whenever both smoke detectors detect smoke. Each smoke detector has a single active-low output called that is asserted whenever it detects smoke particles. The sprinkler has an active-low input called that must be asserted to turn the sprinkler on. Likewise, the telephone dialer initiates a call whenever its active-low input signal is asserted.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

7. A general picture of what is meant by the “System Design Context”
This cloud represents the outside environment in which your system will be used (it might be only rather vaguely defined)
Larger engineered system that your subsystem will be part of
Other subsystems that you’re not responsible for designing
inputs
outputs
This blue oval is the specific subsystem that you’re in charge of designing
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M. Frank, EEL3705 Digital Logic, Spring 2007

8. M. Frank, EEL3705 Digital Logic, Spring 2007
Your Job as a Designer
For the particular subsystem you’re in charge of designing,
First, create a “Top-Level Design” or “System Architecture” for it
Break down your system (blue oval) in a logical way into well-defined subsystems or components (rectangles below), with clearly defined interfaces between them, and clearly defined functional requirements.
The detailed design of each of these subsystems can then be done yourself, or handed off to other engineers on your team, or other design teams
This process can be repeated through as many levels as necessary, until it “bottoms out” at the level of already-existing components…
This permits even very large engineering projects to still be accomplished effectively…
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

9. Simulating Logic Gates in Quartus
Bring up Quartus [latest version installed?]
Interactively demonstrate procedure to:
Select and place logic gates
Wire them to I/O pins
Create input waveforms
Run simulation
View output waveforms
Show not, and2, nand2, band2, bnand2…
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M. Frank, EEL3705 Digital Logic, Spring 2007

10. Example Circuit: AND gate interfaced with active-low I/O devices
Go through example project in Quartus…
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M. Frank, EEL3705 Digital Logic, Spring 2007

11. MAX Package Pin Assignments
From MAX 7000 PLD Family Datasheet (p.61):
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M. Frank, EEL3705 Digital Logic, Spring 2007

12. M. Frank, EEL3705 Digital Logic, Spring 2007
That tells us what the package pins are… Now, what about the plug headers?
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M. Frank, EEL3705 Digital Logic, Spring 2007

13. Mapping from header holes to package pins
From page 7 in the UP2 User Guide.
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M. Frank, EEL3705 Digital Logic, Spring 2007

14. MAX UP2 Header Pin Assignments
See UP2 User Guide, p. 7, table segment display pins in green taken from p.9, table 4 P2
VCCINT
GLCRn
GCLK1 12 13
VCCIO
GND
dot2 d2 g2 f2 P1 X 74
TDI 14 15 c2 73 72
GND 11 9 7 5 3 1 83 81 79 77 75 16 17
TDO b2 71 70 X 10 8 6 4 2 84 82 80 78 76 18 19
GND a2
dot1 e2 69 68
OE2
OE1
GND 20 21
VCCIO g1 67 66
VCCIO 22 23
TMS f1 e1 65 64
VCCIO 24 25
GND d1 63 62
TCK
VCCIO 26 27 c1 61 60 b1 28 29 34 36 38 40 42 44 46 48 50 52 X
GND 59 58 a1 30 31 33 35 37 39 41 43 45 47 49 51 53 P3 57 56
GND 32 X
GND 55 54
VCCINT
VCCIO P4
Color key:
Power
Ground
Not Attached
Assigned
Available
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

15. Topic 2.2.1.1: Boolean Algebra
Just the Essentials
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M. Frank, EEL3705 Digital Logic, Spring 2007

16. M. Frank, EEL3705 Digital Logic, Spring 2007
Breakdown of Topic
Topic 2. Combinational Digital Logic
Subtopic 2.2. Design of combinational logic circuits
Analytical combinational design
Boolean algebra
Syntax, defining axioms, and basic identities
Hand-derivation of Boolean algebra equivalences
DNF and CNF expansions
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

17. What is Boolean Algebra?
A minor generalization of propositional logic.
In general, an algebra is any mathematical structure satisfying certain standard algebraic axioms.
Such as associative/commutative/distributed laws, etc.
General theorems that are proved about an algebra then apply to any mathematical structure satisfying these axioms.
Boolean algebra just generalizes the rules of propositional logic to sets other than {T,F}.
E.g., to the set {0,1} of base-2 digits, or the set {VL, VH} of low and high voltage levels in a circuit.
We will see that this algebraic perspective is useful for the analysis and synthesis of digital logic circuits.
Claude Shannon’s Master’s thesis!
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M. Frank, EEL3705 Digital Logic, Spring 2007

18. Boolean Complement, Sum, Product
Correspond to logical NOT, OR, and AND.
We denote the two logic values as 0:≡F and 1:≡T, instead of False and True.
Using numbers encourages algebraic thinking.
New, more algebraic-looking notation for the most common Boolean operators:
In order of decreasing precedence →
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M. Frank, EEL3705 Digital Logic, Spring 2007

19. M. Frank, EEL3705 Digital Logic, Spring 2007
Boolean Functions
Let B = {0, 1}, the set of Boolean values.
For all nZ+, any function f:Bn→B is called a Boolean function of degree n.
There are 22ⁿ (wow!) distinct Boolean functions of degree n.
Because there are 2n rows in truth table; each containing either a 0 or a 1.
Degree How many Degree How many
, ,294,967, ,446,744,073,709,551,616.
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M. Frank, EEL3705 Digital Logic, Spring 2007

20. M. Frank, EEL3705 Digital Logic, Spring 2007
Boolean Expressions
Let x1, …, xn be n different Boolean variables.
n may be as large as desired.
A Boolean expression or formula (recursive definition) is a string of one of the following forms:
Base cases: 0, 1, x1, …, or xn.
Recursive cases: E1, (E1E2), or (E1+E2), where E1 and E2 are Boolean expressions.
A Boolean expression represents a Boolean function.
Furthermore, every Boolean function (of a given degree) can be represented by a Boolean expression.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

21. Boolean equivalents, operations on Boolean expressions
Two Boolean expressions e1 and e2 that represent the exact same function f are called equivalent.
We write e1e2, or just e1=e2.
This means that the two expressions have the same value for all possible combinations of values of all of the free variables appearing in e1 and e2.
The operators ¯, +, and · can be extended from just operating on expressions to operating on the functions that they represent, in the obvious way.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

22. Some popular Boolean identities
Note: The laws circled in red depart from ordinary numerical algebra!
Double complement:
x = x
Idempotent laws:
x + x = x, x · x = x
Identity laws:
x + 0 = x, x · 1 = x
Domination laws:
x + 1 = 1, x · 0 = 0
Commutative laws:
x + y = y + x, x · y = y · x
Associative laws:
x + (y + z) = (x + y) + z
x · (y · z) = (x · y) · z
Distributive laws:
x + y·z = (x + y)·(x + z)
x · (y + z) = x·y + x·z
De Morgan’s laws:
(x · y) = x + y, (x + y) = x · y
Absorption laws:
x + x·y = x, x · (x + y) = x
also, the Unit Property: x + x = 1 and Zero Property: x · x = 0
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

23. Methods for Determining whether Two Boolean Formulas are Equivalent
Write out their truth tables & compare them
Carry out an analytic, symbolic derivation by hand using the basic identities & theorems
Much like you do in ordinary algebra…
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M. Frank, EEL3705 Digital Logic, Spring 2007

24. M. Frank, EEL3705 Digital Logic, Spring 2007
Duality
The dual ed of a Boolean expression e representing function f is obtained by exchanging + with ·, and 0 with 1 in e.
The function represented by ed is denoted fd.
Duality principle: If e1e2 then e1de2d.
Example: The equivalence x(x+y) = x implies (and is implied by) x + xy = x.
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M. Frank, EEL3705 Digital Logic, Spring 2007

25. Topic 2.2.1.1.3: DNF and CNF representations
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M. Frank, EEL3705 Digital Logic, Spring 2007

26. Representing Boolean Functions
Sum-of-products Expansions
A.k.a. Disjunctive Normal Form (DNF)
Product-of-sums Expansions
A.k.a. Conjunctive Normal Form (CNF)
Functional Completeness
Minimal functionally complete sets of operators.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

27. Sum-of-Products Expansions
Theorem: Any Boolean function can be represented as a sum of products of variables and their complements.
Proof: By construction from the function’s truth table. For each row that is 1, include a term in the sum that is a product representing the condition that the variables have the values given for that row.
Show an example on the board.
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M. Frank, EEL3705 Digital Logic, Spring 2007

28. M. Frank, EEL3705 Digital Logic, Spring 2007
Literals, Minterms, DNF
A literal is a Boolean variable or its complement.
A minterm of Boolean variables x1,…,xn is a Boolean product of n literals y1…yn, where yi is either the literal xi or its complement xi.
Note that at most one minterm can have the value 1.
The disjunctive normal form (DNF) of a degree-n Boolean function f is the unique sum of minterms of the variables x1,…,xn that represents f.
A.k.a. the sum-of-products expansion of f.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

29. Conjunctive Normal Form
A maxterm is a sum of literals.
CNF is a product-of-maxterms representation.
Or, product-of-sums.
To find the CNF representation for f,
take the DNF representation for complement f,
f = ∑i∏j yi,j
and then complement both sides & apply DeMorgan’s laws to get:
f = ∏i∑j yi,j
Can also get CNF more directly, using the 0 rows of the truth table.
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

30. Functional Completeness
Since every Boolean function can be expressed in terms of ·,+,¯, we say that the set of operators {·,+,¯} is functionally complete.
There are smaller sets of operators that are also functionally complete.
We can eliminate either · or + using DeMorgan’s law.
NAND | and NOR ↓ are also functionally complete, each by itself (as a singleton set).
E.g., x = x|x, and xy = (x|y)|(x|y).
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M. Frank, EEL3705 Digital Logic, Spring 2007

31. Reversible Boolean Logic
A reversible Boolean function of degree n is a bijective function f:Bn↔Bn.
Also corresponds to a permutation of Bn.
Reversible unary and binary Boolean operators are bijective operators on B and B2, respectively.
Unary f:B↔B, binary f:B2↔B2.
It turns out that no set of reversible unary and binary Boolean operators is functionally complete!
However, there are many ternary reversible operators that are functionally complete, even as singletons.
One reason that reversible logic is interesting is that these operations theoretically require no energy to carry out!
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

32. M. Frank, EEL3705 Digital Logic, Spring 2007
A little Quantum Logic
A quantum Boolean function is a bijective and linear function f:C2ⁿ↔C2ⁿ.
That is, it maps vectors of 2n complex numbers (one for each n-bit string of Boolean values) reversibly and linearly.
Any reversible Boolean function corresponds to a quantum Boolean function where a string in Bn is represented by c=1 for that string, c=0 for all others.
Any quantum Boolean function can be built out of quantum operators operating on just C and C2.
Quantization removes the need for ternary gates!
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007