1. TPC electronics design - GdSP
Status

2. GdSP design effort
Reminder: synergy between CMS muon chambers readout (VFAT3) and TPC AIDA pad readout (SALTRO+AFTER) -> GdSP, under Paul Aspell’s leadership.
First design meetings at CERN: July 2011, 2 in October Team being set up. « olders » passing their experience, newcomers start. Jan Kaplon (130 nm expert), Marek Idzik (ADC expert), Eric Delagnes, Fabrice (low-noise amplifiers, TPC experts).
Well motivated team. Clear synergies, but to which extent? (VFAT3:discriminator, TPC: ADC)

3. GdSP IBM CMOS 130 nm technology, power 1.2 V
Work on power consumption (PASA16 consums too much)
Multiple power domains
Use SRAM and the CELLS standard from CERN to make the IP blocks (AIDA WG3)
Use GBT to interface FE to concentrator
Optimize for 100 ns shaping
Note limit on dynamics: 1.2 V supply, 10mV/fC -> less than 10 bits. (study in mM case shows this is OK)

4. Future Make a limited amount of silicon in about 2 years.
Watch differences between the muon chamber application and the TPC application.
Bring input on real time data processing, self-triggering, etc…