1. Details .L and .S units
TMS320C6000

2. Details .L and .S units .S .L OPERANDI OPERAZIONI ARITMETICO LOGICHE
Data Memory .D .M .L A0 A1 A2 A3
A15
Register File A
. . . a x
prod
32-bits Y .S
OPERAZIONI
ARITMETICO LOGICHE
General Purpose
OPERANDI
CO .U <? >, <?> , <?>

3. OPERANDS 32/40-bits Register, 5-bits Constant
OPERANDS can be:
5-bit constants (or 16bit for MVKL and MVKH)
32-bit registers
40-bit Registers
However, we have seen that registers are only 32-bit.
So where do the 40-bit registers come from?

4. OPERANDS 40-bits Register
A 40-bit register can be obtained by concatenating two registers
There are 3 conditions that need to be respected:
The registers must be from the same side.
The first register must be even and the second odd.
The registers must be consecutive.

5. OPERANDS 40-bits Register
All combinations of 40-bit registers are shown below:
A1:A0
A3:A2
A5:A4
A7:A6
A9:A8
A11:A10
A13:A12
A15:A14
odd
even : 32 8
40-bit Reg
B1:B0
B3:B2
B5:B4
B7:B6
B9:B8
B11:B10
B13:B12
B15:B14
odd
even : 32 8
40-bit Reg

6. OPERANDS 32/40-bits Register, 5-bits Constant
instr .unit < SRC >, < SRC >, < DST >
32-bit Reg
5-bit Const
32-bit Reg
40-bit Reg
< src >
< dst >
.L or .S
32-bit Reg
40-bit Reg

7. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S

8. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S
OR .L1 A0, A1, A2

9. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S
OR .L1 A0, A1, A2
ADD .L2 -5, B3, B4

10. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S
OR .L1 A0, A1, A2
ADD .L2 -5, B3, B4
ADD .L1 A2, A3, A5:A4

11. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S
OR.L1 A0, A1, A2
ADD.L2 -5, B3, B4
ADD.L1 A2, A3, A5:A4
SUB.L1 A2, A5:A4, A5:A4

12. Operands 32/40-bits Register, 5-bits Constant
instr .L < SRC >, < SRC >, < DST >
32-bit Reg
40-bit Reg
< src >
5-bit Const
< dst >
.L or .S
OR.L1 A0, A1, A2
ADD.L2 -5, B3, B4
ADD.L1 A2, A3, A5:A4
SUB.L1 A2, A5:A4, A5:A4
ADD.L2 3, B9:B8, B9:B8

13. Register to Register Data Transfer
To move the content of a Register (A or B) to another register (B or A) use the move MV Instruction, e.g.:
MV A0 , B or MV B6 , B7
To move the content of a Control Register to another register (A or B) or vice-versa use the MVC instruction, e.g.:
MVC IFR , A0 or MVC A0 , IRP

14. Increasing the processing power
TMS320C6000

15. Code Review (using side A only)40
an xn
n = 1 *
Code Review (using side A only)
MVK .S1 40, A2 ; A2 = 40, loop count
loop: LDH .D1 *A5++, A0 ; A0 = a(n)
LDH .D1 *A6++, A1 ; A1 = x(n)
MPY .M1 A0, A1, A3 ; A3 = a(n) * x(n)
ADD .L1 A4, A3, A4 ; Y = Y + A3
SUB .L1 A2, 1, A2 ; decrement loop count
[A2] B .S1 loop ; if A2  0, branch
STH .D1 A4, *A7 ; *A7 = Y
Note: Assume that A4 was previously cleared and the pointers are initialised.
Assume that A2 is B0

16. How can we add more processing power to this processor?
Increasing the processing power!
Data Memory .D .M .L A0 A1 A2 A3
A15
Register File A
. . .
32-bits .S
How can we add more processing power to this processor?

17. Increase the clock frequency
Increasing the processing power!
Data Memory .D .M .L A0 A1 A2 A3
A15
Register File A
. . .
32-bits .S
Increase the clock frequency
Increase the number of Processing units

18. To increase the Processing Power, this processor has Two Sides
Increasing the processing power!
To increase the Processing Power, this processor has Two Sides
Register File A
.S1
.M1
.L1
.D1 A0 A1 A2 A3 A4
. . .
A15
32-bits
Register File B
.S2
.M2
.L2
.D2 B0 B1 B2 B3 B4
. . .
B15
32-bits
Scambio di operandi
Scambio di operandi
Data Memory

19. Increasing the processing power!
To exchange operands between the two sides, some CROSS PATH or LINKS are required
What is a CROSS PATH?
A Cross Path links one side of the CPU to the other
There are two types of Cross Paths:
DATA CROSS PATH
ADDRESS CROSS PATH

20. Data Cross Paths
Data cross paths can also be referred to as register file cross paths
These cross paths allow operands from one side to be used by the other side
There are only two cross paths:
one path which conveys data from side B to side A, 1X
one path which conveys data from side A to side B, 2X

21. TMS320C67x Data-Path
DATA cross paths only apply to the .L, .S and .M units
The data cross paths are very useful, however there are some limitations in their use.

22. Data Cross Path - Limitations2x
.L1
.M1
.S1 B 1x
<src>
<dst>
(1) The Destination register must be on same side as unit
(2) Source registers - up to ONE Cross Data Path per execute packet per Side.
Execute packet: group of instructions that execute simultaneously.

23. Data Cross Path - Limitations2x
.L1
.M1
.S1 B 1x
<src>
<dst>
ADD .L2x A0 , A1 , B2
MPY .M1x A0 , B6 , A9
SUB .S1x A8 , B2 , A8
|| ADD .L1x A0 , B0 , A2
||  Means that the SUB and ADD belong to the same fetch packet, therefore execute simultaneously.
Not Valid !

24. Data Cross Path - Limitations2x
.L1
.M1
.S1 B 1x
<src>
<dst>
.L2
.M2
.S2
SUB .S1x A8 , B2 , A8
|| ADD .L2x A0 , A0 , B5

25. The pointer must be on the same side of the unit
Address paths
.D1 A
Addr
Data
LDW .D1T1 *A0, A5
STW .D1T1 A5, *A0
The pointer must be on the same side of the unit

26. A B Address Cross Paths .D1 .D2 Data1 A5 DA1 = T1 *A0 LDW .D1T1 *A0,A5
LDW .D1T2 *A0,B5 B
DA2 = T2
.D2
Data2 B5

27. Standard Parallel Loads
Data1 A5 A
.D1
DA1 = T1
*A0
.D2 B
DA2 = T2
*B0
LDW .D1T1 *A0,A5
|| LDW .D2T2 *B0,B5 B5

28. Parallel Load/Store using Address Cross Paths
Data1 A5
.D1
DA1 = T1
*A0
.D2 B
DA2 = T2
*B0
LDW .D1T2 *A0,B5
|| STW .D2T1 A5,*B0 B5

29. Fill the blanks ... Does this work?
Data1
.D1
DA1 = T1
*A0
.D2 B
DA2 = T2
*B0
LDW .D1__ *A0,B5
|| STW .D2__ B6,*B0

30. Not Allowed! Parallel accesses: both cross or neither cross
Data1
.D1
*A0
.D2 B
DA2 = T2
*B0 B5 B6
LDW .D1T2 *A0,B5
|| STW .D2T2 B6,*B0

31. Conditions Don’t Use Cross Paths
If a conditional register comes from the opposite side, it does NOT use a data or address cross-path.
Examples: [B2] ADD .L1 A2,A0,A4 [A1] LDW .D2 *B0,B5

32. ‘C6x Data-Path - Summary
CPU
Ref Guide
Full CPU Datapath (Pg 2-2)
‘C67x

33. Cross Paths - Summary Data Address Conditionals Don’t Use Cross Paths.
Destination register on same side as unit.
Source registers - up to one cross path per execute packet per side.
Use “x” to indicate cross-path.
Address
Pointer must be on same side as unit.
Data can be transferred to/from either side.
Parallel accesses: both cross or neither cross.
Conditionals Don’t Use Cross Paths.