CNET 315 Microprocessor & Assembly Language

CNET 315 Microprocessor & Assembly Language
Phiros Mansur Nalakath Course Coordinator College of Computer Science & Information Systems Jazan University, Jazan

Chapter 2 Computers, Microcomputers & Microprocessors
Microprocessors & Assembly Language - Chapter 2

Microprocessors & Assembly Language - Chapter 2
Objectives To understand:- Types of different Computers Evolution of Microprocessors Internal Architecture of 8086 Register and Memory Organizations in 8086 Minimum mode and Maximum mode operations Microprocessors & Assembly Language - Chapter 2

Types of Computers Mainframe Super Computer Mini Computer Micro Computer Microprocessors & Assembly Language - Chapter 2

Mainframe: The largest and most powerful computer They are designed to work at very high speed Large data words, typically 64 bits or greater They have massive amount of memory Used in military defense control, business data processing, computer graphic display. Example: IBM 4381 Microprocessors & Assembly Language - Chapter 2

Super Computer: The fastest and more powerful mainframes are called Super Computer Example: Cray Y-MP/ 832 Used by largest firms, government agencies and universities Microprocessors & Assembly Language - Chapter 2

Mini Computer: Scaled-down versions of mainframe Computer Runs slowly, works with smaller data word Does not have as much memory as mainframe Used in scientific research and industrial control Microprocessors & Assembly Language - Chapter 2

Micro Computer: Small computer CPU is usually a single microprocessor Example: Desk top, Lap top, Pam top Microprocessors & Assembly Language - Chapter 2

Microprocessor Age Classification of Microprocessor: Microprocessors are classified according to the length of data handled by its ALU at a time Example: 4 – bit, 8 – bit, 16 – bit and 32 – bit microprocessor. Microprocessors & Assembly Language - Chapter 2

4 bit microprocessor 4004: 4 bit microprocessor Able to address bit wide memory Instruction set contained only 45 instructions It was fabricated using a PMOS technology Instruction execution rate was 50 KIPs Microprocessors & Assembly Language - Chapter 2

4040: Updated version of 4004. Use: microwave ovens, small control system and calculator. Microprocessors & Assembly Language - Chapter 2

8 bit microprocessor 8008: 8 bit microprocessor, 16 K bytes memory, 48 instructions. 8080: 500,000 IPS, 64 K bytes memory, 8085: In 1977, Intel Corporation introduced the last 8 bit microprocessor. Execution rate 769,230 per second. Main advantage was internal clock and higher clock frequency. Microprocessors & Assembly Language - Chapter 2

16 bit microprocessor 8086/8088: 2.5 MIPs, 1 M byte memory 6 byte instruction cache or queue that prefetch a few instructions before execution 80286: 4 MIPs, 16 M byte memory Almost identical to 8086. Microprocessors & Assembly Language - Chapter 2

32 bit microprocessor 80386: First 32 bit microprocessor. 32 bit data and 32 bit memory address. 4 G bytes memory It included hardware circuitry for memory management. Microprocessors & Assembly Language - Chapter 2

80486 8 K byte cache memory Half cycle instruction execution. Microprocessors & Assembly Language - Chapter 2

Pentium: 4 G byte memory, 8 K byte data cache and 8 K byte instruction cache Data bus 64 bit Multimedia execution instructions or MMX Dual integer processors The Pentium simultaneously executes two independent instructions using superscalar technology Jump prediction technology of Pentium, speeds the execution of programs that include loops. Floating point processor processes floating point data Microprocessors & Assembly Language - Chapter 2

Pentium Pro: 21 million transistors, 3 integer units, one floating point unit 16 K byte level 1 cache (8 K byte for data and 8 K byte for instructions) and 256 K level 2 caches 3 execution engines can be configured for 64 G byte memory and it is used with Windows NT operating system for server applications. Microprocessors & Assembly Language - Chapter 2

Microprocessor Data Type:
Bit Byte Word Unsigned And Signed Binary Integers BCD (Binary Coded Decimal) Numbers ASCII Floating Point Numbers Microprocessors & Assembly Language - Chapter 2

Microprocessor data type
Bit: smallest unit of information It represents either 1 or 0 Byte: 8 – bits of data Word: Data that is handled by a microprocessor at a time Ex: 8 bit, 16 bit, 32 bit word Microprocessors & Assembly Language - Chapter 2

Overview of Microcomputer Structure and Operation
CPU I/O Ports Memory ROM RAM Input Device Output device Address Bus Data Bus Microprocessors & Assembly Language - Chapter 2

Major Parts: CPU Memory Input / Output Buses: Address bus Data bus Control bus Microprocessors & Assembly Language - Chapter 2

Memory It stores the binary codes for the sequences of instructions It stores binary coded data Example: ROM, RAM, magnetic / optical disks Microprocessors & Assembly Language - Chapter 2

Input / Output: They are used to take in data from outside world or send data to the outside world I/O devices are connected with microprocessor through I/O ports Example: Keyboards, video display terminals, printers, modems Microprocessors & Assembly Language - Chapter 2

Central Processing Unit:
It controls the operation of computer The CPU fetches binary-coded instructions from memory Decodes the instructions into a series of simple actions Carries out these actions in a sequence of steps Important components: IP, General purpose register and control bus signal generating circuits Microprocessors & Assembly Language - Chapter 2

Address Bus: It consists of 16, 20, 24, 32 or 36 parallel unidirectional signal lines On these lines the CPU sends out the address of the memory location or I/O port that is to be written to or read from The number of locations that the CPU can address is determined by the number of address lines Microprocessors & Assembly Language - Chapter 2

Data Bus: Data bus consists of 8, 16, 32 parallel bidirectional signal lines Many devices in the system will have their output connected to data bus, but only one device at a time will have its output enabled Microprocessors & Assembly Language - Chapter 2

Control Bus: The control bus consists of 4 to 10 parallel signal lines The CPU sends out signals on the control bus to enable the outputs of addressed memory devices or port devices Example of control signals: Memory read, Memory write Microprocessors & Assembly Language - Chapter 2

Hardware The name given to the physical devices and circuitry of the computer. Example: Keyboard, Monitor, Mouse etc Microprocessors & Assembly Language - Chapter 2

Hardware Examples Microprocessors & Assembly Language - Chapter 2

Software Refers to he programs written for the computer Example: Operating System (WNDOWS) Application Programs (like WORD) Microprocessors & Assembly Language - Chapter 2

Examples of Software Microprocessors & Assembly Language - Chapter 2

Firmware The term given to the programs stored in ROMs or in other devices which permanently keep their stored information. Example: BIOS programs Microprocessors & Assembly Language - Chapter 2

8086 Microprocessor

It is a 16 bit μp. 8086 has a 20 bit address bus can access upto 220 memory locations ( 1 MB) . It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19. Microprocessors & Assembly Language - Chapter 2

8086 Microprocessor (cont..)
It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. Microprocessors & Assembly Language - Chapter 2

8086 Microprocessor Architecture & Signals

8086 Architecture / Block Diagram Microprocessors & Assembly Language - Chapter 2

Functional Units of 8086 8086 CPU is divided into two functional Units, Bus Interface Unit (BIU) and Execution Unit (EU) The major reason for this separation is to increase the processing speed of the processor BIU has to interact with memory and input/output devices in fetching the instructions and data required by the EU. EU is responsible for executing the instructions of the programs and to carry out the required processing. Microprocessors & Assembly Language - Chapter 2

Execution Unit Control Circuitry Instruction Decoder Arithmetic and Logical Unit (ALU) Flag Register General Purpose Registers Pointer and Index Register Microprocessors & Assembly Language - Chapter 2

Execution Unit Cont… Control Unit: Directs Internal Operation. Instruction Decoder: It translates the instruction fetched from memory into a series of action which the EU carries out ALU: This 16 bit ALU can add, subtract, AND, OR, XOR, INC, DEC, complement or shift binary numbers i.e it is responsible for all arithmetic and logical operation. Microprocessors & Assembly Language - Chapter 2

Bus Interface Unit Instruction Queue Segment Registers Instruction Pointer Microprocessors & Assembly Language - Chapter 2

Internal Registers of 8086 The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. Microprocessors & Assembly Language - Chapter 2

Internal Registers of 8086 (cont..)
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment Stack segment Data segment Extra segment Microprocessors & Assembly Language - Chapter 2

Code segment (CS) Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Microprocessors & Assembly Language - Chapter 2

Stack segment (SS) Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Microprocessors & Assembly Language - Chapter 2

Data segment (DS) Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Microprocessors & Assembly Language - Chapter 2

Extra segment (ES) Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. Microprocessors & Assembly Language - Chapter 2

Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. Microprocessors & Assembly Language - Chapter 2

The following registers are both general and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Microprocessors & Assembly Language - Chapter 2

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: Instruction Pointer (IP) is a 16-bit register. Flags is a 16-bit register containing 9 one bit flags. Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand. Microprocessors & Assembly Language - Chapter 2

Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts. Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction. Sign Flag (SF) - set if the most significant bit of the result is set. Zero Flag (ZF) - set if the result is zero Microprocessors & Assembly Language - Chapter 2

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation. Microprocessors & Assembly Language - Chapter 2

Minimum and Maximum Modes
The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration. Microprocessors & Assembly Language - Chapter 2

Minimum Mode 8086 System In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. Microprocessors & Assembly Language - Chapter 2

Maximum Mode 8086 System In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. • In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information . • In the maximum mode, there may be more than one microprocessor in the system configuration. • The components in the system are same as in the minimum mode system Microprocessors & Assembly Language - Chapter 2

Reference Books: 1. Douglas V. Hall, “Microprocessors and Interfacing ” 2. Barry B. Brey, “The Intel Microprocessors” Microprocessors & Assembly Language - Chapter 2

Thanks… Microprocessors & Assembly Language - Chapter 2

CNET 315 Microprocessor & Assembly Language

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