1. RX 8-Bit Timer (TMR) 4/20/2011 Rev. 1.00
Hello and welcome to this Renesas Interactive course that covers RX the 8-Bit Timer
4/20/2011
Rev. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.
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2. Agenda
This course contains a description of specific features of the RX 8-Bit Timer (TMR) including a description of timer types, number of channels, supported modes, and other specific items.
Contained in this Module:
Block Diagram
Operation Modes
Interrupt Generation
Usage Notes
This course covers specific features of the 8-Bit Timer, or TMR, found on RX MCUs.
In this course, we’ll cover the TMR’s block diagram, operation modes, interrupts generation, and some helpful usage notes.
© 2011 Renesas Electronics America Inc. All rights reserved.

3. Block Diagram
Peripheral Bus
This figure shows a block diagram of a typical TMR unit on an RX MCU. A given MCU might have multiple TMR units.
Note that a single TMR unit contains two 8-bit TMR timer channels.
These two 8-bit channels can be cascaded into a single 16-bit timer channel based on the operation mode.
At the right we see that the TMR sits on the peripheral bus
And that the clock used for driving the timer is generated from a prescaled peripheral clock ranging from PCLK to PCLK divided by 8192.
Additionally, the TMR clocking can be driven from rising, falling or both rising and falling edges of the external TMCI pins.
The clock selection is determined by a bit-field within the Timer Counter Control Register.
The timing of the interrupts and output pins are controlled by the A and B compare match registers and the value of the count register.
The behavior of the output pins and A to D conversion start request are controlled by bit-fields in the Timer Control Status Registers.
The Timer Control Register determines which interrupts are generated by the timer and also how the counter register is reset.
In addition to be counter register able to being cleared on compare match events, it can be cleared based on the edge or level of the external timer input pins.
Next we’ll describe the different operating modes of this timer unit.
© 2011 Renesas Electronics America Inc. All rights reserved.

4. Pulse Output Mode
Based on configuration of the TMR control registers (TCR, TCCR, and TCSR) we can set the TMR channel to output a continuous pulse stream.
Here we’ll discuss a single configuration selection, but other selections are possible which can vary some of the details such as polarity and channel usage.
In this figure you can see that the timer output pin is going low when the timer count value matches the TCORB value and high when the timer count value matches the TCORA value
Also note that the timer count value is reset when this match occurs.
The effect of this configuration is a pulse width modulated (PWM) whose period is controlled by TCORA and duty cycle is controlled by TCORB.
To establish this configuration, counter clear bits of the TCR are set to “clear on compare match A”…this is why the counter resets to zero at the TCORA match.
In the TCSR register, Channel A Output Select bits are set to “High on Match” and the Channel B Output Select bits are set to “Low on Match”…causing the transitions that can be seen in the output waveform.
Once these registers are configured and the timer is started, no software intervention is required to keep the pulse output continuously running.
© 2011 Renesas Electronics America Inc. All rights reserved.

5. Reset Input Mode
Similar to the Pulse Mode, this Reset Input Mode uses the TMR control registers (TCR, TCCR, and TCSR) to set the reset mode behavior and details can be varied based on application need.
The behavior in this mode is that TMRin input pin is used to gate the timing and operation of the output pin.
So long as the TMRin pin is held high , the counter is held to a zero value, once the TMRin pin is set low , the counter starts and when it counts to TCORA the timer output goes high and when it matches TCORB the output goes low.
To establish this configuration, counter clear bits of the TCR are set to “Clearing By the External Reset Input” and the TMRIS bit of the TCCR register set to “Cleared when the external reset is high”… this is why the counter is kept to zero while TMRin is high.
In the TCSR register, Channel A Output Select bits are set to “High on Match” and the Channel B Output Select bits are set to “Low on Match”…causing the transitions that can be seen in the output waveform.
A useful variation of this configuration can be used to monitor the activity on a TMRin pin.
By setting the TMRIS bit to “reset on rising edge”, if the TMRin stops toggling long enough to allow the TCORA match to occur, an interrupt can be generated to the processor to notify of lack of activity.
© 2011 Renesas Electronics America Inc. All rights reserved.

6. 16-Bit Operation
Peripheral Bus
By setting the Clock Source select bits in the Channel 0 TCCR register to 011b, the two 8 bit channels function as a single 16 bit channel.
In this mode, the TCNT, TCORA and TCORB registers of channels 0 and 1 function as a single 16-bit register, with channel 0 being the high 8-bits and channel 1 being the low 8-bits.
When accessing these registers in 16-bit mode, they should be read and written as 16 bit values.
The IODEFINE file associated with the MCU allows access to these registers as either 8 or 16 bits values…the proper data structure should be chosen based on operation mode.
In this mode, the pins associated with channel 0 act as the pins for the combined 16-bit unit.
© 2011 Renesas Electronics America Inc. All rights reserved.

7. Interrupt Generation
To understand the detailed timing of the interrupt generation, the operation of the counter TCNT needs to be explained.
When using the external clock, the clock edge is synchronized to the PCLK and this clock generates a TCNT input clock for one peripheral clock period .
Note that when using the external clock, when counting on a single edge the pulse width must be at least 1.5 PCLK cycles wide and for counting both edges the pulse width must be at least 2.5 PCLK cycles wide.
When using the internal prescaled clock, the rising edges of the pre-scaled clock generates a TCNT input clock for one peripheral clock period.
It is these TCNT input clocks that causes the TCNT to increment.
The compare match signal is generated when counter TCNT is incremented by the TCNT input clock after it has already matched the compare match TCORA or TCORB register.
The period of the of the interrupt signal is therefore one more than the value in the compare match register.
On the peripheral clock edge after the compare match signal is generated the compare match interrupt signal is sent to the ICU.
These compare match interrupts can be used to interrupt the microprocessor, activate the data transfer controller, or in the case of TCORA, trigger an A/D conversion.
The timer can also generate an interrupt on a timer overflow from 0xFF to 0x00 .
© 2011 Renesas Electronics America Inc. All rights reserved.

8. Writing to the TCNT Count Register
Usage Notes
Enable the TMR Unit
Writing to the TCNT Count Register
Conflict between Compare match event and TCORx Writing
Simultaneous A/B match event
Switching clock source while running
On this slide we will cover some usage notes for the TMR peripheral…more detail may be found in the MCU hardware manual.
First, the user should always remember to bring each unit of TMR that they are using out of the module stop state. This is done by clearing the bit in the module stop control registers that corresponds to the TMR unit you are using. Please refer to the Low Power Consumption section of your hardware manual to see which bits should be cleared. If this bit is not cleared then the TMR peripheral will be disabled and its registers will not writable.
The second note has to do with writing to the count register TCNT. When the timer is running, writing the count register at the instant of a compare match clear event will be ignored and the count will still be cleared to zero. If writing to the count register occurs at the same time as a TCNT input clock is present, the newly written TCNT value will be used and clock increment will be ignored.
The third item to consider is that when writing either of the TCOR compare registers at the same instant of an compare match event causes the compare match event to be discarded and the new compare match value to become active.
The fourth item clarifies the behavior when both A and B match events are set to the same value. In this case both event actions are considered and the action with the higher priority is performed. The priorities from high to low are “Toggle Output”, “Set Output High”, “Set Output Low”, and “No Change”.
Finally, It is not normally recommended to switch clock sources while the timer is running. But if it becomes necessary, bare in mind that an extra clock edge may be generated and counted.
© 2011 Renesas Electronics America Inc. All rights reserved.

9. Summary Block Diagram Operation Modes Interrupt Generation Usage Notes
Thanks for Viewing!
In summary, in this module we covered:
the block diagram of the Renesas TMR peripheral,
Information on operation modes that this timer can provide
Detailed information on the interrupt generation,
And usage notes to be aware of when using the TMR peripheral.
We would like to thank for viewing this course. You may consider viewing the RX Family Overview Course for more information on RX MCUs.
© 2011 Renesas Electronics America Inc. All rights reserved.

10. © 2011 Renesas Electronics America Inc. All rights reserved.
Thank You
© 2011 Renesas Electronics America Inc. All rights reserved.