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Decompression After The Cache For Compressed Code Execution

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Presentation on theme: "Decompression After The Cache For Compressed Code Execution"— Presentation transcript:

1 Decompression After The Cache For Compressed Code Execution
By Yujia Jin Rong Chen

2 Overall Picture compression Instruction ROM I $ cpu LAT CLB Cache line
decomp LAT CLB

3 Overall Picture compression Instruction ROM I $ cpu LAT CLB
decomp decomp CLB LAT

4 Pipeline CLB Decompress IF IF ID IE MEM WB regular address 
compressed address Cache(compressed address) compressed instruction Compressed instruction original instruction CLB Decompress IF IF ID IE MEM WB

5 Traditional Compression Algorithm
Break program into n instructions blocks, compress each block serially at byte level. Problems 8 byte instruction  8 cycle to decompress a single instruction. IF ID IE MEM WB CLB Decomp IF ID IE MEM WB CLB D0 D1 D2 D3 D4 D5 D6 D7 Not true random access. Jump from block x to the nth instruction in block y will require the first n-1 instruction be decompressed.

6 Compression Algorithm
256 entry table0 16 bit wide table1 table2 table3 16 bits 64 bits instruction 8 bit ptr 8 bit ptr 32 bit compressed instruction Only if all 4parts are compressed *Use LAT to keep track if the instruction is compressed IF ID IE MEM WB CLB Decomp

7 Result

8 Result ijpeg in spec95

9 Branch Compensation Cache
Problems of branch instructions Whenever encounter a branch instruction, the pipeline has to waste 3 stages Find out it’s a jump, has to wait here IF DEC ID IE MEM CLB WB CLB IF DEC BUB BUB BUB BUB CLB IF BUB BUB BUB BUB BUB CLB BUB BUB BUB BUB BUB BUB Restart a new pipeline and proceed until IF DEC ID IE MEM CLB WB IF DEC ID IE MEM CLB WB

10 Branch Compensation Cache
Solutions Add a branch compensation cache (BCC), try to pre-store the target instructions. When encounter a PC jump, go to check if the target instruction is there. I $ Is target instr. in BCC? ID jump no CPU addr CLB addr’ DEC I $ CLB addr’ ID DEC yes IE BCC

11 Branch Compensation Cache
Results The branch compensation cache behaves like the ordinary cache. ijpeg in spec95

12 Result ijpeg in spec95

13 Conclusion + Our approach can increase instruction cache hit rate. This may translate to instruction cache area saving. - Our current compression algorithm provides true random access at the cost of lower compression rate. possible improvements provide optimal table entries. provide multiple levels of tables.


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