1. ECE 3430 – Intro to Microcomputer Systems
ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs
Lecture #7
Agenda Today
Logical Instructions (AND, OR, exclusive OR, …)
Other Arithmetic Instructions (addition, subtraction)
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

2. Bit-Wise Manipulation of Memory
The MSP432 is a byte-addressable architecture.
This means that each address targets a byte
stored in memory. So what if you want to
change one bit in memory (without effecting
the other bits in that byte)?
Apply boolean logic:
AND: Force a bit to zero or no change.
OR (ORR): Force a bit to one or no change.
Exclusive OR (EOR): Toggle a bit to opposite state or no change.
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

3. Bit-Wise Manipulation of Memory
BIC = bit clear
BIS = bit set
There is no explicit BIS instruction in the instruction set.
Reason: It is the same as ORR.
BIC does exist and is ALMOST the same as AND—except that
the mask argument is inverted first.
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

4. Bit-Wise Manipulation of Memory
The AND, ORR, BIC, and EOR instructions conceptually form
a logic gate between each corresponding pair of bits of the two
sources to the ALU.
These bit-wise instructions can use any of the addressing modes supported
by MOV.
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

5. Bit-Wise Manipulation of Memory
Examples
(each perform 32, bit-wise logic operations at the same time):
AND R0,#0x12  bitwise AND …
31…
x … x x x x x x x x
ORR R0, R1, #0x55  bitwise OR
EOR R2, R3, R4  bitwise exclusive OR
BIC R0, #0x12  bit clear (invert mask and apply AND operation)
Logic Gate
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

6. Bit-Wise Manipulation of Memory
These logical instructions are useful for setting, clearing, or toggling bits within a byte: ORR w/ 1 to set LDR R0, =P1OUT LDRB R1, [R0]
ORR R1, #0x STRB R1, [R0]
 will force P1.1 to ‘1’ AND w/ 0 to clear AND R1, #0xFFFFFFFD
(or BIC R1, #0x2)
 will force P1.1 to ‘0’
EOR w/ 1 to toggle EOR R1, #0x2
 will toggle the state of P1.1
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

7. Bit-Wise Manipulation of Memory
AND operation also useful for bit masking. For example, compare the state of only the least-significant 4 bits of a byte  mask off the upper 4 bits.
XOR is useful for a quick, efficient comparison for equality. A single XOR gate is a 1-bit digital comparator.
 EOR R4,R5 (R4 will be zero if the contents of R4 and R5 are the same)
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

8. ECE 3430 – Intro to Microcomputer Systems
Carry Flag in ARM
The carry flag (C-flag) in the PSR always represents a carry condition in
this architecture.
During addition, it represents whether or not an unsigned overflow condition has
occurred.
During subtraction, it represents whether or not a larger value has
been subtracted from a smaller value when the two values (of equal
precision) as both considered unsigned.
A “carry” and “borrow” condition are always inverses.
When the carry flag is 0 following a subtraction, a “borrow” has occurred
(smaller – larger).
When the carry flag is 1 following a subtraction, a “borrow” has not occurred
(larger - smaller).
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

9. Other Arithmetic Instructions
ADD – binary add instruction.
ADC – binary add instruction with carry.
SUB – binary subtract instruction.
SBC – binary subtract instruction with carry (borrow).
Can natively do 8,16, and 32-bit binary addition/subtraction.
Greater than 32-bit requires multi-precision arithmetic by chaining ADC and
SBC instructions in sequence.
There are several other flavors of add and subtract instructions. Useful in more
specialized applications (like DSP)…
Signed/unsigned ADD/SUB (SADD8/16, UADD8/16, SSUB8/16, USUB8/16)
Signed/unsigned halving add/subtract (SHADD8/16, UHADD8/16, SHSUB8/16, UHSUB8/16)
Saturating add/subtract instructions (QADD, QSUB, …)
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

10. Arithmetic Instructions: The SUB/CMP Instruction
What happens if the result is negative?  The “N” bit in the SR is set.
What happens if two’s compliment overflow occurs?  The “V” bit in the SR is set.
What happens if the result is zero?
 The “Z” bit in the SR is set.
What happens if a larger unsigned value is subtracted from a smaller unsigned value?
 The “C” bit is cleared. It is set on larger – smaller.
Lecture #7
ECE 3430 – Intro to Microcomputer Systems
Fall 2015