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I2C Synchronous Serial Two wire communications (plus ground)

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Presentation on theme: "I2C Synchronous Serial Two wire communications (plus ground)"— Presentation transcript:

1 I2C Synchronous Serial Two wire communications (plus ground)
SCL – clock line SDA – bi-directional data line Message length: unrestricted Master – Slave Network Master Controls the information flow Source of SCL Slave Can synchronize data transfer by introducing wait states 9/12/2018 ECE 340 Lecture 24

2 I2C Synchronous Serial Multi-drop communications:
Multiple transmitters and receivers on a common communications conductor Broadcast communications is possible One sender – many listeners Collision arbitration is required for multiple masters 9/12/2018 ECE 340 Lecture 24

3 I2C Definitions TERM DESCRIPTION
Transmitter: The device which sends data to the bus Receiver: The device which receives data from the bus Master: The device which initiates a transfer, generates clock signals and terminates a transfer Slave: The device addressed by a master Multi-master: More than one master can attempt to control the bus at the same time without corrupting the message Arbitration: Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Synchronization: Procedure to synchronize the clock signals of two or more devices 9/12/2018 ECE 340 Lecture 24

4 I2C Physical Layer 9/12/2018 ECE 340 Lecture 24

5 I2C Framing 9/12/2018 ECE 340 Lecture 24

6 I2C Bit Transfer 9/12/2018 ECE 340 Lecture 24

7 I2C Byte Transfer Bit States Recessive (high == 1) Dominate (low == 0)
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8 I2C Acknowledge 9/12/2018 ECE 340 Lecture 24

9 I2C Address 9/12/2018 ECE 340 Lecture 24

10 I2C Packet 9/12/2018 ECE 340 Lecture 24

11 Master Write Packet NACK – “Not ACKnowldege” can be used by slave to terminate packet 9/12/2018 ECE 340 Lecture 24

12 Master Read Packet Specification calls for Master to terminate with a NACK and a Stop bit 9/12/2018 ECE 340 Lecture 24

13 Master Write / Read Packet
If changing direction of data transfer, then the master must resend the address in order to change the value of the R/W bit 9/12/2018 ECE 340 Lecture 24

14 “Mystery Code” int ReadIOXPort(unsigned char port) { #define IOX0 0x76
#define I2C_READ 0x01 // R/W bit char data_byte; int err; if(!port) // Assign I2C Address to Port Number port = IOX0; else port = IOX1; if (err=i2c_start_tx()) { // Start bit i2c_stop_tx(); return 0xff00 | err; } // Stretching error if (err=i2c_write_char(port + I2C_READ)) { // Send Address i2c_stop_tx(); return 0xfe00 | err; } // Stretching error If (err=i2c_read_char(&data_byte)) { // Read data i2c_stop_tx(); return 0xfc00 | err; } // Stretching error i2c_send_ack(); // Acknowledge data i2c_stop_tx(); // Stop bit return (unsigned int) data_byte; } // end ReadIOXPort “Mystery Code” 9/12/2018 ECE 340 Lecture 24

15 “Bit Banging” // Define these to change basic bit handling
#define i2c_SCL_H() BitWrPortI(PDDDR,&PDDDRShadow,0,I2CSCLBit) #define i2c_SCL_L() BitWrPortI(PDDDR,&PDDDRShadow,1,I2CSCLBit) #define i2c_SDA_H() BitWrPortI(PDDDR,&PDDDRShadow,0,I2CSDABit) #define i2c_SDA_L() BitWrPortI(PDDDR,&PDDDRShadow,1,I2CSDABit) #define i2c_SCL() BitRdPortI(PDDR,I2CSCLBit) // read SCL #define i2c_SDA() BitRdPortI(PDDR,I2CSDABit) // read SDA 9/12/2018 ECE 340 Lecture 24

16 Clock Stretching int i2c_wSCL_H(){ // Tries to set SCL high & waits
// Returns -1 if SCL stretch too long auto int delay_cnt; i2c_SCL_H(); cWAIT_5_us; // Set SCL HI delay_cnt = 0; while(i2c_SCL()==0 && delay_cnt < i2cClockStretchDelay) { cWAIT_5_us; delcnt++; } // end while if (i2c_SCL()==0) return -1; // Clock stretch too long return 0; } // end i2c_wSCL_H() 9/12/2018 ECE 340 Lecture 24

17 Start, Stop, & Ack int i2c_start_tx(){ // Try to send start pulse.
// If clock stretch exceeded, return -1 else 0 if (i2c_wSCL_H()) return -1; // Try to set SCL HI i2c_SDA_H(); cWAIT_5_us; // Set SDA HI i2c_SDA_L(); cWAIT_5_us; // Set SDA LO i2c_SCL_L(); return 0; // Set SCL LO } // end i2c_start_tx void i2c_stop_tx() { i2c_SDA_L(); cWAIT_5_us; i2c_SCL_H(); cWAIT_5_us; i2c_SDA_H(); } // end i2c_stop_tx int i2c_send_ack() { i2c_SDA_L(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; cWAIT_5_us; i2c_SCL_L(); cWAIT_5_us; i2c_SDA_H(); return 0; } // end i2c_send_ack 9/12/2018 ECE 340 Lecture 24

18 Write Char int i2c_write_char(char d){
// Writes char; returns -1 if no ACK from remote auto char i; for (i=0; I < 8; i++) { if (d & 0x80) i2c_SDA_H(); // send bit else i2c_SDA_L(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; // Set SCL HI i2c_SCL_L(); cWAIT_5_us; // Set SCL LO d = d << 1; } // end for return i2c_check_ack(); } // end i2c_write_char() 9/12/2018 ECE 340 Lecture 24

19 Do you see any opportunities for improvement?
Read char int i2c_read_char(char *ch) { auto char res,cnt; for ( cnt=0,res=0; cnt<8; cnt++ ) { i2c_SDA_H(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; res <<= 1; if (i2c_SDA()) res |= 0x01; i2c_SCL_L(); cWAIT_5_us; } // end for *ch=res; return 0; } // end i2c_read_char Do you see any opportunities for improvement? 9/12/2018 ECE 340 Lecture 24

20 I2C on UI Project PCB 9/12/2018 ECE 340 Lecture 24

21 PCF8574 I2C Expander Can accommodate up to 8 devices on one I2C network 9/12/2018 ECE 340 Lecture 24

22 PCF8574 I2C Expander 9/12/2018 ECE 340 Lecture 24

23 Multi-Master I2C Network
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24 I2C Arbitration 9/12/2018 ECE 340 Lecture 24

25 I2C Arbitration for 2 Masters
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26 I2C References Specification: Tutorials
Tutorials Introduction to I2C ( 9/12/2018 ECE 340 Lecture 24

27 Quiz List, and briefly describe, differences between RS232 and I2C communication in the Rabbit environment. Do see anything wrong with this? If (err=i2c_read_char(&data_byte)) { // Read data i2c_stop_tx(); return 0xfc00 | err; } // Stretching error 9/12/2018 ECE 340 Lecture 24


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