1. ESD issue in FEI4_B
A. Mekkaoui

2. General comment
This is not an absolute or rigorous evaluation of FEI4_B ESD tolerance performance.
It is an attempt to relatively assess the consequences of the 2 issues that were introduced in FEI4_B compared to FEI4_A.

3. Simplified REG2_IN connections
Other ESD devices
clamp
LDO 2
REG2_IN PAD

4. Simplified REG1_IN connections
Other ESD devices
NO clamp!
REG1_IN PAD

5. ESD effect on REG1 and REG2

6. ESD event (4A, 100ns current pulse)
REG2 handles event much better than REG1 (thanks to its clamp)
Not safe for both !

7. ESD event (2A, 100ns current pulse)
Safe for REG2 and NOT safe for REG1.

8. ESD event (1A, 100ns current pulse)
Safe for REG2 and NOT safe for REG1.

9. ESD event (0.5A, 100ns current pulse)
Safe for REG2 and almost safe for REG1 (Few SOA 1.6V limit)

10. ESD event, REG1,2 connected to A2,D2 [2. 2uF output cap and 2
ESD event, REG1,2 connected to A2,D2 [2.2uF output cap and 2.2uF input
ESD charge dumped into input cap mainly!

11. ESD event, REG1,2 connected to A2,D2 [2.2uF output cap @100mOHms]
ESD charge dumped into diverse sources (cap, clamp, VDDA2/VDDD clamp)

12. ESD event on 1, REG1,2 connected to A2,D2 [2
ESD event on 1, REG1,2 connected to A2,D2 [2.2uF output 100Mohms and 4nH]. REG1_IN and REG2_IN connected
ESD charge dumped into clamp2 and output cap mainly!

13. ESD event on 1, REG1,2 connected to A2,D2 [2
ESD event on 1, REG1,2 connected to A2,D2 [2.2uF output and input 100Mohms and 4nH]. REG1_IN and REG2_IN connected
ESD charge dumped into input caps mainly!

14. Simplified REG2_IN connections
Other ESD devices
clamp
LDO 2
REG2_IN PAD

15. Simplified REG2_IN connections (2)
VREG2_IN
N P
N P
N P
N P
N P
N P
Other ESD devices
vddshunt2
Rext2
Vref2
Vbbp2
Vref2
clamp
REG2_IN PAD
As protected as can be! But …

16. Vref2 protection (100mA*100nS)
As protected as can be! But ESD safe procedures are required

17. Simplified REG1_IN connections
Other ESD devices
NO clamp!
REG1_IN PAD

18. Simplified REG1_IN connections (2)
OPEN
VREG2_IN
N P
N P
N P
N P
N P
N P
Other ESD devices
vddshunt1
BgVrefDg
Rext1
Vref1
Vbbp1
NO clamp!

19. BgVrefDg Parasitic diode (large) FLOATING! VREG2_IN N P N P N P N P
vddshunt1
BgVrefDg
Rext1
Vref1
Vbbp1
GND
Not vulnerable!

20. Vbbp1 VREG1_IN FLOATING! Parasitic diodes N P N P N P N P N P N P
vddshunt1
BgVrefDg
Rext1
Vref1
Vbbp1
Poorly protected in general, but does not need to be connected.
Some protection will be provided if REG1_IN and REG2_IN are connected.
“complete” protection if floating node is connected to REG1_IN and REG1_IN is connected to
REG2_IN.
GND

21. Vbbp1 (25 mA*100ns ESD)
With floating high side!

22. Vbbp1 (100 mA/100ns ESD)
Without floating high side!

23. VddShunt1 FLOATING! N P N P N P N P N P N P vddshunt1 BgVrefDg Rext1
Vbbp1
GND
Poorly protected in general, but does not connect directly to a gate.
Don’t wire-bond or connect to VREG_IN1. (could be connected to VREG_In2)

24. VddShunt1 (100mA*100ns ESD)
Without floating high side!

25. Rext1 FLOATING! N P N P N P N P N P N P vddshunt1 BgVrefDg Rext1 Vref1
Vbbp1
Vulnerable. Connects to a gate Not necessary to wire-bond.
Affects shunt operation only. Don’t wire-bond.
GND

26. Rext1 (25mA*100ns ESD)
With floating high side!

27. Rext1 (100mA*100ns ESD)
Without floating high side!

28. VREF1 FLOATING! N P N P N P N P N P N P vddshunt1 BgVrefDg Rext1 Vref1
Vbbp1
Vulnerable. Necessary for the LDO to function
Only protected after connection to a chip generated VREF
=> Safe wire-bonding
Wire-bond after the intended vref is wire-bonded (left to right wire bonding after REG2_IN ,
REG1_IN and their grounds are bonded !
GND

29. VREf1 (25mA*100ns ESD)
With floating high side!

30. VREf1 (100mA*100ns ESD)
Without floating high side!

31. VREf1 RECOMMENDATION
Connect to Vref2 AND/OR BgVrefdg Even if you want to override it. (strongly suggest AND)
This will provide protection against ESD and also against misdialing the wrong voltage (externally).
Less than +/- 10uA is required to override this voltage.

32. REG1 and REG2 Normal operation

33. Normal operation, REG1,2 connected to A2,D2 [1uF output cap with 0 Ohm ESR]
Not stable!

34. Normal operation, REG1,2 connected to A2,D2 [1uF output cap with 100 mOhm ESR, without shunt]
Stable!

35. Normal operation, REG1,2 connected to A2,D2 [1uF output cap with 100 mOhm ESR, with shunt]
Not stable!

36. Normal operation, REG1,2 connected to A2,D2 [4uF output cap with 100 mOhm ESR]
Not stable!

37. Normal operation, REG1,2 connected to A2,D2. 5us rise time
Normal operation, REG1,2 connected to A2,D2. 5us rise time. 1Ohm source+cable resistance
Too fast!

38. Normal operation, REG1,2 connected to A2,D2. 10us rise time
Normal operation, REG1,2 connected to A2,D2. 10us rise time. 1Ohm source+cable resistance
Too fast!

39. Normal operation, REG1,2 connected to A2,D2. 10us rise time
Normal operation, REG1,2 connected to A2,D2. 10us rise time. 1Ohm source+cable resistance
Keep REG_IN rise time >100uS

40. ESD related mortality can be minimized by proper and safe wire-bonding
Conclusions
Error in FEI4_B introduced weakness in ESD performance for pads related to one LDO
ESD related mortality can be minimized by proper and safe wire-bonding
Once properly wire-bonded FEI4_B will be almost as protected as if the error did not exist.
Input caps are part of the ESD mitigation
No protection scheme is perfect. All ESD safety procedures must be observed.
Suggest wire bonding REG2_GND and REG2_IN first, then REG1_GND and REG1_IN then all power and gnd pads (left to right) then the rest of the chip from left to right. I suppose the board is preloaded with the necessary caps and REG2_IN and REG1_IN are also pre-connected (even if through a small resistance).
Or REG2_GND and REG2_IN first, then REG1_GND and REG1_IN then the rest of the chip from left to right.
Board to chip or chip to board ?????
Establish an FEI4_B wire-bonding procedure.
Must insure proper ramping of input power
New wafers with the “floating “ ESD power corrected will be available!