1. ESE532: System-on-a-Chip Architecture
Day 12: February 27, 2017
Real Time Scheduling
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2. Today Real Time Synchronous Reactive Model Interrupts
Polling alternative
Timer?
Resource Scheduling Graphs
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3. Message Scheduling is key to real time Analysis Guarantees
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4. Synchronous Circuit Model
A simple synchronous circuit is a good “model” for real-time task
Run at fixed clock rate
Take input every cycle
Produce output every cycle
Complete computation between input and output
Designed to run at fixed-frequency
Critical path meets frequency requirement
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5. Synchronous Reactive Model
Discipline for Real-Time tasks
Embodies the “synchronous circuit model”
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6. Synchronous Reactive
There is a rate for interaction with external world (like the clock)
Computation scheduled around these clock ticks (or time-slices)
Continuously running threads
Each thread performs action per tick
Inputs and outputs processed at this rate
Computation can “react” to events
Reactions finite and processed before next tick
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7. Thread Form while (1) { tick(); }
tick() -- yields after doing its work
May be state machine
May trigger actions to respond to events (inputs)
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8. Thread Model
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9. Tick Rate Driven by application – demands of external control
Control loop 100 Hz
Robot, airplane, car, manufacturing plant
Video at 33 fps
Game with 20ms response
Router with 1ms packet latency
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10. Tick Rate Multiple rates
May need master tick as least-common multiple of set of interaction rates
…and lower freq. events scheduled less frequently
E.g. 100Hz control loop at 33Hz video
Master at 10ms
Schedule video over 3 10ms time-slots
May force decompose into tasks fit into smaller time window since must schedule events at highest frequency
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11. Synchronous Reactive Ideal model Separate function from compute time
Per tick reaction (task processing) instantaneous
Separate function from compute time
Separate function from technology
Feature size, processor mapped to
Like synchronous circuit
If logic correct, works when run clock slow enough
Works functionally when change technology
Then focus on reducing critical path
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12. Synchronous Reactive Timing
Once functional,
need to guarantee all tasks (in all states)
can complete in tick time-slot
On particular target architecture
Identify WCET
Like critical path in FSM circuit
Time of task on processor target
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13. Preclass 1 Time available to process objects?
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14. Preclass 1 Worst-case object processing time?
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15. Preclass 1 Maximum number of objects on single GHz processor?
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16. Synchronous Reactive Timing
Once functional,
need to guarantee all tasks (in all states) can complete in tick time-slot
On particular target architecture
Identify WCET
Like critical path in FSM circuit
Time of task on processor target
Schedule onto platform
Threads onto processor(s)
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17. Threads Mapped to Processor
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18. Platforms Platform 1: fast processor Platform 2: many slow processors
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19. Synchronous Reactive Model
Discipline for Real-time tasks
Embodies the “synchronous circuit model”
Master clock rate
Computation decomposed per clock
Functionality assuming instantaneous compute
On platform, guarantee runs fast enough to complete critical path at “clock” rate
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20. Midterm
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21. Midterm From Code Forms of Parallelism Analysis
Dataflow, SIMD, hardware pipeline, threads
Map/schedule task graph to (multiple) target substrates
Memory assignment and movement
Area-time points
Analysis
Bottleneck
Amdhal’s Law Speedup
Computational requirements
Resource Bounds
Critical Path
Latency/throughput
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22. Interrupts
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23. Interrupt External event that redirects processor flow of control
Typically forces a thread switch
Common for I/O, Timers
Indicate a need for attention
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24. Interrupts: Good Allow processor to run some other work
Infrequent, irregular task service with low response service latency
Low latency
Low throughput
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25. Interrupts: Bad Time predictability Processor usage
Real-time for computing tasks interrupted
Processor usage
Costs time to switch contexts
Concurrency management
Must deal with tasks executing non-atomically
Interleave of interrupted service tasks
Perhaps interleave of any task
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26. Polling Discipline Alternate to I/O interrupts
Every I/O task is a thread
Budget time and rate it needs to run
E.g. 10,000 cycles every 5ms
Likely tied to
Buffer sizes
Response latency
Schedule I/O threads as real-time tasks
Some can be DMA channels
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27. IO Thread while (1) { process_input(); }
Like tick() -- yields after doing its work
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28. Preclass 2 Input at 100KB/s 30ms time-slot window Size of buffer?
100 cycles/byte, GHz processor – runtime of service routine?
Fraction of processor capacity?
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29. Scheduling I/O Tasks
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30. Timer Interrupts Bounded-time tasks E.g. reactive tasks in real-time
Task has guarantee to release processor within time window
Not need timer interrupts to regain control from task
(Maybe use deadline operations for timer)
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31. Timer Interrupts Best effort tasks
Have no guarantee to finish in bounded time
Timer interrupts necessary
to allow other threads to run
fairness
to switch to real-time service tasks
Need timer interrupts if need to share processor with real-time threads
Easier to segregate real-time and best-effort threads onto different processors
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32. Greedy Strategy Schedule real-time tasks
Scheduled based on worst-case, so may not use all time allocated
Run best-effort tasks at end of time-slice after complete real-time tasks
Timer-interrupt to recover processor in time for start of next scheduling time slot
(adds complexity)
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33. Real-Time Tasks Interrupts less attractive
More disruptive
Scheduled polling better predictability
Fits with Synchronous Reactive Model
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34. Resource Scheduling Graphs
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35. Scheduling Useful to think about scheduling a processor by task usage
Useful to budget and co-schedule required resources
Bus
Memory port
DMA channel
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36. Simple Task Model Task requires Uses resources Data to be transferred
Local storage state
Computational cycles
(Result data to be transferred)
Uses resources
Bus/channel to transfer data
(in and out)
Space in memory on accelerator
Cycles on accelerator
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37. One Task P1 P2
Bus
Mem
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38. Several Tasks Resource 1 2 3 4 5 6 7 8 P1 P2 Bus Mem1 2 3 4 5 6 7 8 P1 P2
Bus
Mem
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39. Resource Schedule Graph
Extend as necessary to capture potentially limiting resources and usage
Regions in memories
Memory ports
I/O channels
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40. Extended Details Resource 1 2 3 4 5 6 7 8 P1 P1 M0 P1 M1 P2 P2 M01 2 3 4 5 6 7 8 P1
P1 M0
P1 M1 P2
P2 M0
P2 M1
Bus1
Bus2
OCM
DRAM
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41. Several Tasks Resource 1 2 3 4 5 6 7 8 P1 P1 M0 P1 M1 P2 P2 M0 P2 M11 2 3 4 5 6 7 8 P1
P1 M0
P1 M1 P2
P2 M0
P2 M1
Bus1
Bus2
OCM
DRAM
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42. Approach Ideal/initial – look at processing requirements
Resource bound on processing
Look for bottlenecks / limits with Resource Bounds independently
Add buses, memories, etc.
Plan/schedule with Resource Schedule Graph
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43. Preclass 3a Resource Bound Data movement over bus?
Compute on 2 processors?
Compute on 2 processors when processor must wait while local memory is written?
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44. Preclass 3b Schedule Processor wait for data load
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45. Double Buffering Common trick to overlap compute and communication
Reserve two buffers input (output)
Alternate buffer use for input
Producer fills one buffer while consumer working from the other
Swap between tasks
Trade memory for concurrency
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46. Preclass 3c Schedule Double Buffer
Minimum local memory space required?
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47. Resource Schedule Graphs
Useful to plan/visualize resource sharing and bottlenecks in SoC
Supports scheduling
Necessary for real-time scheduling
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48. Big Ideas: Scheduling is key to real time Synchronous reactive
Analysis, Guarantees
Synchronous reactive
Scheduling worst-case tasks “reactions” into master time-slice matching rate
Schedule I/O with polling threads
Avoid interrupts
Schedule dependent resources
Buses, memory ports, memory regions…
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49. Admin Exam Wednesday HW6 due Friday <Enjoy Spring Break>
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