1. ESE534 Computer Organization
Day 7: February 17, 2014
Interconnect Introduction
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2. Previously Universal building blocks Computations with gates
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3. Today Universal Spatially Programmable Crossbar
Programmable compute blocks
Start thinking about optimizing interconnect
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4. Spatial Programmable
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5. Spatially Programmable
Program up “any” function
Not sequentialize in time
E.g. Want to build any FSM or any arithmetic operation
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6. Needs? Need a collection of gates. What else will we need?
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7. Needs Need some registers Need way to programmably wire gates together
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8. Multiplexer Interconnect
Use a multiplexer for programmable interconnect
Can select any source to be an input for a gate
How big is an N-input multiplexer?
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9. Sources? What are potential sources? Inputs to circuit -- I
Outputs of gates -- G
Outputs of registers – R
N=I+G+R
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10. Sinks Which things need programmable inputs? (and how many?)
Circuit outputs -- O
Gate – needs one per input -- kG
Assuming k-input gates
Registers – R
M = O+R+kG
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11. N-input, M-output Multiplexing
Area?
Bits to control the multiplexers?
Data input switching
Capacitance Switched?
Delay?
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12. Mux Programmable Interconnect
Area M×N = (I+G+R) × (O+kG+R) = kG2 + …
Scales faster than gates!
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13. Interconnect Costs We can do better than this Even when we do better
Touch on a little later in lecture
Dig into details later in term
Even when we do better
Interconnect can be dominate
Area, delay, energy
Particularly for Spatial Architectures
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14. Dominant Time LUT is the gate. Definition coming soon…
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15. Dominant Power [Energy]
XC4003A data from Eric Kusse (UCB MS 1997)
[Virtex II, Shang et al., FPGA 2002]
[Tuan et al./FPGA 2006]
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16. Crossbar
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17. Crossbar
Allows us to connect any of a set of inputs to any of the outputs.
This is functionality provided with our muxes
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18. Crossbar Structure Can be more efficient
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19. Crossbar Costs Area still goes as M×N Delay proportional to M + N
More realistic even for mux implementation
Energy still goes as M×N
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20. Crossbar Notation
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21. Gates with Crossbar Interconnect
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22. Programmable, Universal
Program to any function of N gates
Limitation we only use nand2 gates?
What can we say about functions of arbitrary 2-input gates?
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23. Universal Computation with Fixed Compute Operator
Being minimalists, this shows:
do not need compute to be programmable
Just use fixed nor2 or nand2
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24. Programmable Functions
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25. Mux can be a programmable gate
bool mux4(bool a, b, c, d, s0, s1) {
return(mux2( mux2(a,b,s0),
mux2(c,d,s0),
s1)); }
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26. Program AND2? How do we program to behave as and2?
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27. Mux as Logic bool and2(bool x, y)
{return (mux4(false,false,false,true,x,y));}
bool or2(bool x, y)
{return (mux4(false,true,true,true,x,y));}
Just by routing “data” into this mux4,
Can select any two input function
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28. LUT – LookUp Table When use a mux as programmable gate
Call it a LookUp Table (LUT)
Implementing the Truth Table for small # of inputs
# of inputs =k (need mux-2k)
Just lookup the output result in the table
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29. Programmable Compute Can use programmable gate in place of nor gate
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30. Programmable Compute
How do we “program” to perform a particular function?
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31. Instructions
Set of bits that tell the programmable units how to behave
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32. Is an Adder Universal? Assuming interconnect: A: 001a What’s c?
(big assumption as we have just seen)
Consider:
What’s c?
A: 001a
B: 000b
S: 00cd
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33. Practically To reduce (some) interconnect,
and to reduce number of operations,
do tend to build a bit more general “universal” computing function
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34. Arithmetic Logic Unit (ALU)
Observe:
with small tweaks can get many functions with basic adder components
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35. Arithmetic and Logic Unit
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36. ALU Functions A+B w/ Carry B-A A xor B (squash carry)
A*B (squash carry) /A
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37. Optimization and Design Space
Interconnect
Optimization and Design Space
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38. Locality Maybe we don’t need to connect everything to everything?
Cluster groups of C things at leaves
CG gates, CR registers
Limit cluster I/O – CI, CO
Crossbar within cluster
Crossbar among clusters
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39. Compare Switches
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40. 8×16=128
8×4+18×4=104
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41. Comparing Full Crossbar needs: kG2 switches
How many switches needed for:
CG gates per cluster
CI inputs to cluster
CO outputs from cluster
(ignore registers and circuit input/output)
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42. Costs Cluster Input Crossbar: Cluster Output Crossbar:
Inputs: CI+CG
Outputs: kCG
Cluster Output Crossbar:
Input: CG
Output: CO
Master Crossbar:
Inputs: (G/CG) × CO
Outputs: (G/CG) × CI
(G/CG)×CO×(G/CG)×CI +(G/CG) ×(k×CG2+k×CG×CI+CG×CO)
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43. Costs Cluster: G2×(CI×CO/CG2)+k×G×(CG+CI+CO) Full Crossbar: kG2
Compare at: CG=8, CI=CO=2, G=256, k=2
Cluster case?
Full crossbar case?
216×(2×2/82)+28×(8+2+2)×2 = ×29= ×211= 5×213
217
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44. More? Can we do it again? Discuss Generalization? Issues?
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45. Optimizing Interconnect
What other interconnect optimizations/structures might we use?
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46. Interconnect Design Space
Large interconnect design space
We will be exploring systematically
Day16—20+25
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47. Big Ideas Interconnect can be programmable
Interconnect area/delay/energy can dominate compute area
Exploiting structure can reduce area
Locality
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48. Admin HW2 HW3 Wednesday Drop date is Friday HW4 out
On-time submissions graded
(late assignments will be graded later)
HW3 Wednesday
Drop date is Friday
HW4 out
Reading for Wed. on Web
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