Design & Verification of Low Power SoCs

Design & Verification of Low Power SoCs
Dr. Gary Delp, LSI Mr. John Biggs, ARM Mr. Srikanth Jadcherla, Synopsys Slide 1 (of 118)

Agenda 13:30-13:35 Introduction
Dr. Gary Delp, Distinguished Engineer, LSI Corp 13:35-13:45 Design Challenges in Automotive, Networking, and Storage with input from: Juergen Karmann, Senior Staff Engineer, Design Methodology, Automotive, Industrial & Multimarket, Infineon Technologies 13:45-14:20 Low Power Flow for Design and Verification With input from: Dr. Ed Huijbregts, Vice President, Design Implementation Products, Magma Design Automation 14:20-14:50 Logical verification challenges and techniques Srikanth Jadcherla, Group Director, Synopsys 14:50-15:20 Requirements and Solutions for Low Power Processor Cores John Biggs, Founder & Consultant Engineer, ARM 15:20-15:30 Roundtable and Wrap-up Slide 2 (of 118)

Power Efficiency: Three Scopes of Activity
3 levels addressed concurrently: - System: System-level issues, e.g., system architecture, software, power supplies, power distribution, data compression , density/real-estate , power monitoring and control - SOC Design: SOC - level issues , e.g., architecture, systems/applications to circuits, design methodologies, design & simulation tools - Silicon & Technology: Device-level issues, e.g., process technologies, libraries, memories, design IP blocks, modeling tools, design flows, packaging Motivation Slide 3 (of 118) 3

The Storage Environment: Tomorrow…
The Storage Environment: Today… Internet JBOD Workstation PCs Ethernet Switch Disk Drive Server Server Server Portable “Pocket” Drives Blade Servers PCI RAID HBA FC Switch Shared DAS Storage System Portable Thumb Drives Slide 13: The Storage Environment Today/Tomorrow So we started by looking at the storage ecosystem today. Look at all the devices here that have storage: PCs, servers, storage arrays, JBODs, blades. They all (click) need encryption Tomorrow we'll have security everywhere, with the data-at-rest problem solved using Full Disk Encryption. So we've talked about storage security and the need for data-at-rest security in particular. I want to now spend some time talking about the broader IT ecosystem, where we see some parallels with the storage ecosystem, and some of the emerging technologies used there for combating evolving security threats. JBOD SAN Storage System Increased Processing No increase in power budget 4 Slide 4 (of 118) 4

Sophisticated Threats Require Complex Responses
Blended Attack Corporate Espionage Identity Theft Keyboard Loggers Image Spam Spyware Text Spam Indecent Content Trojans Worms Viruses Content Processing Anti-X Firedoor Anti-Spyware Cost Anti-Spam Web-Filtering IDS/IPS Content Based No increase in power budget Increased Processing Anti-Virus Intrusions Defacement File Deletion Slide 15: Sophisticated Threats Require Complex Responses: As threats increase in sophistication, the processing power/cost to detect or protect against them increases. Physical barriers are not enough to stop a determined attack. Connection based approaches offer a base level of protection, but cannot detect attacks embedded in “good” network traffic. Heavy handed firewalling limits network effectiveness, resulting in lost productivity/leverage of resources. These approaches only “LOCK” the door to access. So you need to protect against these threats, but... What if the attack gets through the door? You need to be able to "see inside" the content flowing across your network, which is called content inspection, to identify the threat based on the content of the message. Content based approaches are required to protect/detect sophisticated attacks used by criminals today. No longer are the attacks done solely for fame, but are a real concern for law enforcement. Profit, control, and power are the new motivators for attacks. Build: For less-sophisticated attacks, more traditional methods of security are needed, and are effective. As attacks get more sophisticated, you need to deploy content processing. Stateful Firewall VPN Connection Based Firewall Theft Siege Padlock Moat Physical Slide 5 (of 118) 5

LSI Enabling Real-Time High-Bandwidth Services
Advanced Packet Processing Advanced Traffic Management Content Inspection Media/Signal Processing APP/ACP Highly integrated Advanced Communication Processors for IP and TDM Traffic Steady operation Array scalable Rapid Start Large State memory: Configuration structures Control structures Data memory Data integrity is key Power management Early estimation T9000 New Network Requirements Industry Leading Content Processing Acceleration with Tarari acquisition DSP Highest Performance Voice and Video Signal Processors Real Time Quality of Experience, Security and Content Inspection Slide 6 (of 118)

Low Power Challenges in Automotive Applications
Thanks to: Juergen Karmann, Senior Staff Engineer Design Methodology Automotive, Industrial & Multimarket Business Group Infineon Technologies, Munich, Germany Slide 7 (of 118)

Semi-conductor enabled functions of a typical car
Body & Convenience Xenon Light, Seat Position, Climate Control, Dashboard Powertrain Engine Control Transmission Control Battery Management Climate Control Airbag Night Vision Park Distance Control Steering Transmission Hybrid Dashboard Blindspot Detection Engine Cooling FAN Suspension TPMS Mirror Door Brake Battery Management Light Central Lock ABS ESP Adaptive Cruise Control Safety Airbag, ABS Brakes, Adaptive Cruise Control Chassis Active Suspension, Power Steering Slide 8 (of 118)

The Future has arrived …
Powertrain Engine Control Transmission Control Battery Management  More performance  Higher ambient temperature  But low power budgets Body & Convenience Xenon Light, Window Lift, Climate Control, Dashboard  More features at higher complexity  Limited space in the car  CMOS and Smart Power Technology on a single die Safety & Chassis Airbag, ABS Brakes, Adaptive Cruise Control Power Steering  Smaller technology nodes  High variability  But high reliability … with complex low power systems in automotive applications Slide 9 (of 118)

Integration of Low and High Power
Current Product (MCM): µ-Controller Next Step: Power-Chip horizontal integration (based on IFX 130nm node) and the Challenges : 1. New coupling effects (parasitic)  full chip power aware AMS simulation 2. Diverging Current Ranges (µA  some A) 3. Shared power supplies among low power CMOS and ‘Smart Power’ domains 4. Digital / Analogue / High Voltage Co-Design to be addressed by :  Formal Power Intent Specification  Interoperability of EDA Tools Slide 10 (of 118)

Power-aware Design Goals
Accelerate Design with more function Provide “Just the right” voltage for the task Including 0, slow-low power, and High performance Provide Formal specification of Power Intent Early and Accurate Power Prediction Verify and Validate the Design and Implementation Use power efficiently Maintain very responsive designs Train designers – Use a simple abstraction Support tool / vendor portability World peace and prosperity Slide 11 (of 118)

With Thanks to: Yatin Trivedi, Director, All things important, Synopsys 13:35-13:45 Design Challenges in Automotive, Networking, and Storage Dr. Gary Delp, Distinguished Engineer, LSI Corp with input from: Juergen Karmann, Senior Staff Engineer, Design Methodology, Automotive, Industrial & Multimarket, Infineon Technologies 13:45-14:20 Low Power Flow for Design and Verification With input from: Dr. Ed Huijbregts, Vice President, Design Implementation Products, Magma Design Automation 14:20-14:50 Logical verification challenges and techniques Srikanth Jadcherla, Group Director, Synopsys 14:50-15:20 Requirements and Solutions for Low Power Processor Cores John Biggs, Founder & Consultant Engineer, ARM 15:20-15:30 Roundtable and Wrap-up Slide 12 (of 118)

Power Efficiency: Three Scopes of Activity
3 levels addressed concurrently: - System: System-level issues, e.g., system architecture, software, power supplies, power distribution, data compression , density/real-estate , power monitoring and control - SOC Design: SOC - level issues , e.g., architecture, systems/applications to circuits, design methodologies, design & simulation tools - Silicon & Technology: Device-level issues, e.g., process technologies, libraries, memories, design IP blocks, modeling tools, design flows, packaging Design Slide 13 (of 118) 13

A three dimensional view of design closure
schedule Timing optimal Area Power Illustration thanks to: Bob Carver Slide 14 (of 118)

Power Profile Optimization
Dynamic Power Profile Optimized Dynamic Power Profile Static Power Profile Optimized Static Power Profile System Workload Slide 15 (of 118)

Opportunity for Power Utilization Improvements
0% 20% 40% 60% 80% 100% Power Optimization Potential Architectural Synthesis Gate Layout 90% is architectural, the other half is physical (with apologies to Yogi Berra) Any element that you optimize out has ) power usage. Slide 16 (of 118)

The new Abstraction For decades designers have worked with the digital abstraction, signals are either logical true or logical false. As with all good abstractions, this one had great utility it allowed optimizations in analysis, separated two areas of difficult analysis, making the design task achievable. This simple abstraction breaks as parts of digital circuits will be turned off relative to other parts The good news is that there is a simple way to express the relationships, boundaries, activities, and side effects of many power domains without having to give up most of the simplifications that the digital abstraction allow us. Current tools allow us to manipulate: logical constraints and directives – The circuit will do what we want Physical shape reuse and analysis – We can build the design Static timing analysis – the design will run as fast as we want Power Intent Goals Scalable transportable methodology for describing and reasoning from: Power Domains Power Supplies / Switches and Supply Sets Acceptable and forbidden Power Modes or States Isolation, Level shifting, retention Support Reuse and transport of design equity Identification and Constraints – The Platinum Source Refinement and Configuration – The Golden Source Implementation and analysis – The Silicon Source Slide 17 (of 118)

Power Management: Source & Flow
Power Source File(s) The traditional Synthesis flow Is augmented with Power Power source files are part of the design source. Combined with the RTL, the power files are used to describe the intent of the designer. This collection of source files is the input to several tools, e.g., simulation, synthesis, STA, test, formal verification, power consistency checking. Multiple source files may be prepared specifically to enable reuse. The details of the “What” and the “How” are often produced by different parties. Design refinement Equity preservation HDL/ RTL Verilog (Netlist) Synthesis Simulation, Logical Equivalence Checking, … Power Source File(s) Verilog (Netlist) P&R Power Source File(s) Slide 18 (of 118)

Power management Structures: The Data Objects
Power Domain The collection of design objects that share common power attributes Power States Controlled by Switches Memories may require Retention States may require sequencing info States will effect simulation Relations & Connections between Domains Level shifters Isolation logic “Gas Stations” alternate supply Identify elements Manage Implement Analyze Reuse Slide 19 (of 118)

The concept of corruption – supply Off (or Partially On)
Supply Nets Net_State Full_on Partial_on Off Voltage May be specified for Analysis and Time based corruption X 1 Partial On or off Full on 1 X 1 X Slide 20 (of 118)

Protection from corruption Electrical – Level Shifting
Supply Net Net_State Full_on Partial_on Off Voltage May be specified for Analysis and Time based corruption Full on, V1 Full on, V2 1 X 1 1 ? Level Shifter Full on, ground Slide 21 (of 118)

Supply sets – Because a single supply net has no meaning in isolation to the power being supplied to any design element, it would be helpful to have the object type “supply set” which does have meaning. For a domain, the following supply set handles are used: primary, default_retention, and default_isolation. Supply sets collect supply nets together so that they can be treated as a unified (and progressively defined) bundle. This is done for efficiency, clarity, simulation, and brevity. Pg pins may be associated with supply set functions to support automatic connection. Completion of supply set specification determines the “equity” of the verification runs. Slide 22 (of 118)

UPF 2.0 Power States Objects which can be attributed with power states: Supply sets Defined in terms of the state of the supply nets of the set Power domains Defined in terms of the state of supply sets, supply nets and the power state(s) of other domain(s) What is included in definition is relevant to the state of the domain and reducible to the state of supply nets This provides the ability to hierarchically specify power state relationships Can also specify state transitions Slide 23 (of 118)

Defining a Power State Same command for both supply sets and domains
add_power_state object_name -state state_name -supply_expr {boolean_expr} -logic_expr {boolean_expr} [-simstate simstate] -legal | -illegal -update Can be refined (-update) over time as design evolves -supply_expr is the golden specification of the power state – used by synthesis and LEC -logic_expr initial, approximation of the power state definition (in the absence of a –supply_expr) -logic_expr becomes an assertion check when –supply_expr is specified -supply_expr and –logic_expr state definitions can be refined supply_expr’ = old_supply_expr && new_supply_subexpr Legality The default for a user-defined power state is legal Specify –illegal to override default; -legal to be explicit By default, undefined power states are illegal Override default legality of undefined power states for an object: add_power_state my_power_domain -legal Slide 24 (of 118)

Simulation States (simstates) Provide Semantic Behavior
Combinatorial Logic Sequential Logic Corruption Semantics NORMAL Fully functional None CORRUPT Non-functional Wires driven by logic and regs powered by the supply corrupted immediately on entering state CORRUPT_ON_ ACTIVITY Wires driven by logic and regs powered by the supply corrupted when any input to the logic is active CORRUPT_SEQ_ON_CHANGE Regs powered by the supply corrupted when the value of the register is changed CORRUPT_SEQ_ON_ACTIVITY Regs powered by the supply corrupted when any input to the reg is active NOT_NORMAL Deferred By default, same as CORRUPT. Tool may provide an override Simstate Combinatorial Logic Sequential Logic Corruption Semantics NORMAL Fully functional None CORRUPT Non-functional Wires driven by logic and regs powered by the supply corrupted immediately on entering state CORRUPT_ON_ ACTIVITY Wires driven by logic and regs powered by the supply corrupted when any input to the logic is active CORRUPT_SEQ_ON_CHANGE Regs powered by the supply corrupted when the value of the register is changed CORRUPT_SEQ_ON_ACTIVITY Regs powered by the supply corrupted when any input to the reg is active NOT_NORMAL Deferred By default, same as CORRUPT. Tool may provide an override Bias & Combo Modes Slide 25 (of 118)

Simulation Model matching
Default model for Level shifting Any difference in the current values of the supply set will cause corruption Modification: A range may be declared legal Modification: A level shifter may be inserted Dual supply – corruption caused when either supply is not full on Default model for Clamps (isolation) Level shifter model applies X’s may be eliminated with logic if the X has the same supply Modification: ordering may be useful in the boundary specification Default Model for Retention Memory is powered by retention supply, save saves current value, restore restores the saved value, the saved value is corrupted when the retention supply is corrupted. Modification: other models may be introduced, they replace the default Note that implementation may have time dependencies, these must be specified so that corruption can be introduced in simulation. Slide 26 (of 118)

Vice President, Design Implementation Products Magma Design Automation
A UPF Example Thanks to: Dr. Ed Huijbregts Vice President, Design Implementation Products Magma Design Automation Slide 27 (of 118)

UPF by example 45nm TSMC library 4 Domains, 2 Hierarchies
Top Level – 1.0v constant Secondary level SUB0 0.99v switched constant Secondary level SUB1 0.89v constant Secondary level SUB2 Domain1 constant PM ctrl logic Diagram from Andrew ISO VDD GND The design we are going to use today is a DES3 design based upon a TSMC 45nm library. It contains 100k cells, 4 domains, 4 floorplans (top, sub0, sub1 and sub2) If start to look at relationship between the different floorplans, then we can see that SUB0 is specified to be switched – therefore all of its outputs which of other blocks which drive it must be isolated to protect sinks inside of SUB0 in the switched off case. SUB0 takes its constant supply from the top level – hence both top & SUB0 work at the same supply voltage (1V) SUB1 and SUB2 both work at 0.8V. We therefore need to define rules for level shifter insertion for interaction both to and from these blocks. Top level driving SUB2 may be acceptable for example since we may be able to tolerate such a small amount of over-voltage. However, going in the other direction, an “uplift” of voltage from 0.8 to 1.0V via level shifter will be required NB We can support n domains, and n levels of hierarchy. Slide 28 (of 118) 28 28

UPF – domain creation Logical  Electrical  Physical UPF Commands
constant u0 u1 u2 Diagram from Andrew create_power_domain top -include_scope create_power_domain SUB0 -elements {u0} create_power_domain SUB1 -elements {u1} create_power_domain SUB2 -elements {u2} The UPF create_power_domain creates a power domain and assigns cells to these domains. A domain defines the electrical characteristics of a group of cells. The right hand picture shows a logical representation of the demo design. In this example we have a top level, with three children (u0,u1,u2). Four domains are created, all are created in the top level scope, the primary domain is called top (the –include_scope option simply includes the current scope i.e. $m as a member of the domain), the domains SUB0, SUB1 and SUB2 are created and associated with u0, u1 and u2 respectively. The left hand picture represents the physical layout that will be shown in the demo. Slide 29 (of 118)

UPF – supply network creation
UPF Commands #Supply net creation for domain top create_supply_net VDD domain top create_supply_net VDD_SUB domain top create_supply_net VDD_SUB domain top create_supply_net GND domain top #Supply net creation for domain SUB0 create_supply_net VDD domain SUB0 -reuse create_supply_net VDD_SUB0_SW -domain SUB0 create_supply_net GND domain SUB0 -reuse #Supply net creation for domain SUB1 create_supply_net VDD_SUB1 -domain SUB1 -reuse create_supply_net GND domain SUB1 -reuse #Supply net creation for domain SUB2 create_supply_net VDD_SUB2 -domain SUB2 -reuse create_supply_net GND domain SUB2 -reuse Domain1 constant Diagram from Andrew The create_supply_net command creates the supply network. Supply networks have generally been the realm of the physical designer, RTL engineers have had to try shoe horn supply nets into verilog/VHDL, but there are limitations as synthesis languages are inherently NOT power aware. The supply network creation in UPF allows the power intent to be described very early (pre simulation), which allows early verification and simulation of the supply network. Supply nets are created in the logical hierarchy, the domain association provides auto punch though of the supply nets to elements in the power domain that require connecting to the specified net. Slide 30 (of 118)

UPF – supply network creation cont…
UPF Commands create_supply_port VDD domain top create_supply_port VDD_SUB1 -domain top create_supply_port GND domain top create_supply_port VDD_SUB2 -domain top connect supply_net VDD –ports VDD connect supply_net VDD_SUB1 –ports VDD_SUB1 connect supply_net VDD_SUB2 –ports VDD_SUB2 connect supply_net GND –ports GND set_domain_supply_net top \ -primary_power_net VDD \ -primary_ground_net GND set_domain_supply_net SUB0 \ -primary_power_net VDD_SUB0_SW \ set_domain_supply_net SUB1 \ -primary_power_net VDD_SUB1 \ set_domain_supply_net SUB2 \ -primary_power_net VDD_SUB2 \ Domain1 constant Diagram from Andrew Supply ports are created using the create_supply_port command. The supply ports, are connected to the supply network using the connect_supply net command. The set_domain_supply_net command provides auto-connection semantics within the domain . Any RTL inferred logic will be connected to the domain supply net (unless other connection rules are specified). Slide 31 (of 118)

UPF – levelshifter strategy
Level shifter considerations Pick a power domain or a set of elements Select input ports, output ports, or both Tolerate a voltage difference threshold UP shift or down SHIFT rule Location (self, parent, sibling, fanout, auto) Insert or not insert Domain1 constant Diagram from Andrew The levelshifter strategies defines how levelshifter requirements are to be handled for a spcified domain. The strategy defines Slide 32 (of 118)

UPF – levelshifter strategy
UPF Commands set_level_shifter SUB1_to_TOP \ -domain SUB1 \ -applies_to outputs \ -rule low_to_high \ -location parent Domain1 constant set_level_shifter TOP_to_SUB1 \ -domain SUB1 \ -applies_to inputs \ -rule high_to_low \ -location self Diagram from Andrew set_level_shifter SUB2_to_TOP \ -domain SUB2 \ -applies_to outputs \ -rule low_to_high \ -location parent set_level_shifter TOP_to_SUB2 \ -domain SUB2 \ -applies_to inputs \ -rule high_to_low \ -location self The levelshifter strategies defines how levelshifter requirements are to be handled for a spcified domain. The strategy defines Slide 33 (of 118)

UPF – isolation cell strategy
UPF Commands set_isolation ISO_STRAT \ -domain SUB0 \ -isolation_power_net VDD \ -isolation_ground_net GND \ -clamp_value 0 Domain1 constant PM ctrl logic set_isolation_control ISO_STRAT \ -domain SUB0 \ -isolation_signal reg_out[25] \ -isolation_sense high \ -location parent Diagram from Andrew ISO VDD GND Slide 34 (of 118)

UPF - retention cell strategy
UPF Commands set_retention key_desIn \ -domain SUB0 \ -retention_power_net VDD \ -elements {u0/uk/ret_key_sel u0/ret_des_key_r \ u0/ret_desIn_r} Domain1 constant PM ctrl logic set_retention_control key_desIn \ -domain SUB0 \ -save_signal {key_b_r_reg[16][27]/pin:Q high} \ -restore_signal {key_b_r_reg[16][26]/pin:Q low} Diagram from Andrew ISO VDD GND Slide 35 (of 118)

UPF - switch cell creation
UPF Commands create_power_switch SUB0_SW \ -domain SUB0 \ -input_supply_port {TVDD VDD} \ -output_supply_port {VDD VDD_SUB0_SW} \ -control_port {NSLEEPIN1 SE_ME_on_1 } \ -control_port {NSLEEPIN2 SE_ME_on_2 } \ -ack_port {NSLEEPOUT1 SE_ME_on_ack_1} \ -ack_port {NSLEEPOUT2 SE_ME_on_ack_2} \ -on_state {SW_on TVDD {NSLEEPIN2 & NSLEEPIN1} } \ -off_state {SW_off {!NSLEEPIN2 & !NSLEEPIN1}} Domain1 constant PM ctrl logic Diagram from Andrew ISO VDD GND VDD TVDD NSLEEPIN1 NSLEEPOUT1 NSLEEPIN2 NSLEEPINOUT2 VDD VDD_SUB0_SW Slide 36 (of 118)

UPF – power states A power state table defines the legal combinations of states for different domains The create_pst command creates a PST, using a specific order of supply nets during operation of the design Each row defines a valid combination of supply states Power states enable optimization and verification Infer of verify level shifters and isolation gates Domain1 constant PM ctrl logic Diagram from Andrew ISO VDD GND Slide 37 (of 118)

UPF – port state information
UPF Commands add_port_state VDD \ -state {VDD_N 0.99} add_port_state VDD_SUB1 \ -state {SUB1_H 0.89} -state {SUB1_L 0.69} add_port_state VDD_SUB2 \ -state {SUB2_H 0.89} -state {SUB2_L 0.69} add_port_state GND \ -state {default 0} Domain1 constant PM ctrl logic Diagram from Andrew ISO VDD GND The add_port_state commands defines state information. The state information consists of a named state, and voltage information for that state (nom, or min,nom and max). An off state can also be defined (for example when a supply network can be shut down off chip). Slide 38 (of 118)

UPF – power states UPF Commands Diagram from Andrew
create_pst PM_pst –supplies\ { VDD u0/VDD_SUB0_SW VDD_SUB1 VDD_SUB2 } add_pst_state pst0 –pst PM_pst –state \ { VDD_N SW_on SUB1_H SUB2_H} add_pst_state pst1 –pst PM_pst –state \ { VDD_N SW_off SUB1_L SUB2_L} Domain1 constant PM ctrl logic Diagram from Andrew ISO VDD GND VDD VDD_SUB0_SW VDD_SUB1 VDD_SUB2 pst0 VDD_N SW_on SUB1_H ps1 SW_off SUB1_L Slide 39 (of 118)

Attributes Specifiable in HDL
HDL attribute Value Equivalent UPF command UPF_clamp_value <“0” | “1” | “Z” | “latch” | “any” | “value”> set_isolation –clamp_value set_port_attributes –clamp_value UPF_sink_off_clamp_value ditto set_isolation –sink_off_clamp_value set_port_attributes –sink_off_clamp_value UPF_source_off_clamp_value set_isolation –source_off_clamp_value set_port_attributes –source_off_clamp_value UPF_pg_type pg_type_value set_port_attributes –pg_type UPF_related_power_pin port_name set_pin_related_supply –related_power_pin set_port_attributes –related_power_port UPF_related_ground_pin set_pin_related_supply –related_ground_pin set_port_attributes –related_ground_port UPF_related_bias_pin set_port_attributes –related_bias_port UPF_retention <“required” | “optional”> set_retention_elements –retention UPF_simstate_behavior <“ENABLE” | “DISABLE”> set_simstate_behavior UPF_is_leaf_cell <“TRUE” | “FALSE”> set_design_attributes –is_leaf_cell Slide 40 (of 118)

Design/Component Hierarchy
Managing Complexity: Design and Conquer Divide and Conquer Reuse Provide Robust Interfaces Component (hierarchicalRef) Design Component Component C Slide 41 (of 118)

Design/Component Hierarchy
HRef Component HRef The Interface specification is common to: the design of the component and the Reuse of the component. It is the contract made at the boundary between design teams. Top–down and Bottom–up are really just two views of the Component/Interface–based design flow. Slide 42 (of 118)

Power Portion of Robust Interface Designing within a context
UPF Commands: mod_if Create_power_domain mod_PD -include_scope Create_power_domain G Create_power_domain B Set_port_attributes -ports {G1, G2} -supply_set G.primary Set_port_attributes -ports {B1, B2, B3} -supply_set B.primary <Set_port_attributes -ports {M1, M2} -supply_set mod_pd.primary> mod_details: Create_power_domain G -update -elements {Green} Create_power_domain B-update -elements {Blue} G1 G2 B1 B2 B3 M1 M2 mod Green Blue Supply sets and set_port_attributes Slide 43 (of 118)

Use Components in an Design
UPF Commands: top create_power_domain top_PD -include_scope create_power_domain pd_G -elements {Y} create_power_domain pd_B -elements {Z} set base set_scope foreach {el} {I1 I2 I3} { set_scope $base/$el load_upf “mod_if.upf” } set_scope $base create_composite_domain topc_PD –subdomains {top_PD U1/mod_PD U2/mod_PD U3/mod_PD} create_composite_domain pdc_G –subdomains {pd_G U1/G U2/G U3/G} create_composite_domain pdc_B –subdomains {pd_B U1/B U2/B U3/B} mod Green Blue G1 G2 B1 B2 B3 M1 M2 Y Slide 44 (of 118)

Basics about Power Intent Specification
Objects in a power domain to be supplied: Power domain Isolation Level shifter Retention Other Elements Requirements for XML specification of power intent: Identifier for objects to be supplied by power Power supplies Explicit supply net names must be avoided Relation of states for power supplies  Power State Table (PST)  With legality: ok, never, unspecified Transition between power states Slide 45 (of 118)

XML Power Intent Component information
Xtension Power Domain Enumeration (internal: power domain element identification) Supply Set Identification (with port punching of tools, power ports are optional) Ports associated with supply sets (set port related supply) Ports with isolation constraints Named Power states and associated simstates Isolation Control required/provided Retention Control required/provided Explicit Level shifting requirements Slide 46 (of 118)

XML Power Characteristic Component Information
Xtension Power Domain Enumeration Supply Set Identification Named Power states and associated power usage Named Activities and associated power usage Isolation Control Retention Control Slide 47 (of 118)

Power Tasks on both sides of the Abstraction
Front end: Functional specification Checking the specification Corruption recognized Srikanth will provide more detail Specify allowed and forbidden power states and transitions Ensure forbidden states and transitions never present Electrical safety Inserts corruption based on power Specify and validate Isolation Back End: Structural specification Correlation to structural No new corruption Electrical protection (level shifting) for all possible states (or specified requirements) Implementation is conservative compared to specification Logical protection - Isolation Structural checks – all supplies that affect the behavior are accounted for in the front end. Simulate and Implement same the Design Slide 49 (of 118)

Verification of Power Managed Designs
Srikanth Jadcherla Group Director, R&D Low Power Verification Synopsys, Inc. Slide 51 (of 118)

Range of Voltage-Control Techniques
OFF 0.9V 1.0V 1.2V RET Multi-Vdd (MV) MTCMOS power gating (shut down) Power gating with State Retention V PWR CTRL 1.0V 0.9V 0.9V 1.0V 1.2V 0.6V A Z VDDB VSSB Dynamic or Adaptive Voltage Frequency Scaling (DVS, DVFS, AVS, AVFS) Low-VDD Standby Variable VTH (Back Bias – P/N) Slide 52 (of 118)

Power Management increases verification complexity enormously
Display in OFF Mode with Power Switches CPU in Normal Mode CPU in HP Mode CPU in Standby Display in Normal Mode Display in HP Mode Display in Standby Tx/Rx in Standby Tx/Rx in Normal Mode 1.0V V1 Level Shifters Isolation Cells 0.8V V2 Audio in OFF Mode with Power Switches Video in OFF Mode with Power Switches Audio in Normal Mode PMU Video in Normal Mode 1.2V V3 Obviously, all of this is now part of the chip’s functional spec. We need to make sure it all works.. Correct implementation of LP specific design elements must happen Verification must now understand voltage values Multiple power states, transitions and sequences must be verified Phone Call PDA Standby Slide 53 (of 118)

Seriously, What could go wrong? Slide 54 (of 118)

Power Management brings new bug types!
Isolation/Level Shifting Bugs Control Sequencing bugs Retention scheme/control errors Retention selection errors Electrical Problems like memory corruption Power Sequencing/Voltage Scheduling errors Hardware-Software deadlock Power Gating collapse/dysfunction Power On Reset/bring up problems Thermal runaway/ Overheating … These are not traditional functional bugs! Verification Engineers Need Training on these Slide 55 (of 118)

Bug Classification Structural Errors Control Errors
Missing Isolation, Level Shifters Devices in wrong domains Wrong Rail connections Control Errors Mistimed Control signals Incorrect control activation sequence Incorrect gating/ungating in off/low power states Architectural Errors Incorrect partitions, policies Incorrect scheduling of resources Slide 56 (of 118)

Checks protection logic against
Structural Errors Missing cell Redundant cell Incorrect cell type Incorrect power domain Incorrect isolation polarity Incorrect iso-enable Checks protection logic against Domain 1 ON(1.2V)/OFF Domain 3 ON (1.2V) Domain 2 PMIC/PMU ISO-Enable Isolation Level Shifters Checks protection logic against Structure needs to be checked constantly through out the implementation flow Slide 57 (of 118)

Incorrect Isolation Sequence Control Error
Intended Behavior 1. Gate the clk 2. Assert iso to 0 3. Assert sleep to 0 Output HighZ based on sleep signal Actual Behavior 1. Gate the clk 2. Assert sleep to 0 3. Assert iso to 0 Control signal sequence error is discovered due to X propagation X is observed due to incorrect iso timing Registers initialized to X after power restoration Slide 58 (of 118)

Voltage Scheduling Error Control/Architecture Error
Top 1.2V  0.9V 1.1V  0.8V A[63:0] Island 2 Island 1 Logic Simulator cannot distinguish between voltage values - All treated as 1 1.2V 1.1V Need Level Shifter 0.9V 0.8V Verification must be aware of the waveform nature of voltage Slide 59 (of 118)

Power Intent = More code to verify!
How does boolean analysis change? How do we make testbenches for RTL + Power Intent? How do we measure coverage, write assertions etc. to make verification fruitful? Slide 60 (of 118)

Voltage aware booleans
Unlearn traditional booleans! Voltage aware booleans Slide 61 (of 118)

Fundamental Technology Shift : Voltage Aware Boolean Analysis
… 1 V1 V2 V3 A B O … 1 X Traditional Boolean Analysis : Implicit, homogenous, always on voltage Voltage-aware Boolean Analysis: Dynamic, Variable voltages as real numbers Slide 62 (of 118)

Voltage-Aware Simulation is now necessary!
1 0.7 V 1.0 V 0.7 V 1.0 V 1 1 X X Traditional Simulators are not voltage aware Voltage-Aware Simulators are Electrically Accurate Slide 63 (of 118)

Multi-Fanout in DVS Voltage at input is not strong enough Island 2
X Island 2 70% of VDD = 1’b1 Island 1 1’b1 Voltage at input is strong enough 0.8 V 1 Island 3 Slide 64 (of 118)

Accurate Voltage Modeling True Voltage Aware Simulation
Voltage is a ‘real’ value – not a binary logic Accurate power-up and power-down voltage ramps must be modeled for accurate simulations Template behavioral models provided with MVSIM Voltage Aware Modeling Parameterized source code provided Real Voltage Voltage Ramp function real vrm(); Slide 65 (of 118)

Retention is a huge verification challenge
The rise of Retention State loss from Power Shut Off may not be OK Performance hit with cache misses Or Latency impact for ‘Cold Start’ Traditionally, Low Vdd Stby was used to retain state As Vtn, Vtp ->0, Vstby becomes impractical Retention flops: Shadow the main element with high Vt Cut off Vdd, but hold on to Shadow element power Restore from Shadow to main element after powerup Many Flavors of Retention exist Languages don’t model them well! Retention is a huge verification challenge Slide 66 (of 118)

Retention stretches language semantics
Retention : A balloon latch is used to retain state when power is turned off Wait, we lack semantics for shutdown, how do we deal with this? (posedge clk or negedge reset_n or posedge save or posedge restore) if (!vdd) q <= 1’bx; else if (!reset_n) q <= 0; else if (save) q_s <= q; else if (restore) q <= q_s; else q <= d; (posedge clk or negedge reset_n) if (!reset_n) q <= 0; else q <= d; Need to simulate and verify this! Retention is causing a lot of havoc in terms of simulation, coverage, assertions and cell modeling in EDA flows and we still have more to come. Amazingly, there has been a lot of industry/academic work in designing retention elements, but not much in verifying that it works, comprehensively. Retention is a huge verification challenge Slide 67 (of 118)

Verifying Retention Complete power Sequence
CLK Enable Clock CLK -EN Disable Clock SAVE Save Disable Isolation ISO Enable Isolation Enable Power PWR EN Disable Power Ramp Voltage VDD Ramp Voltage Enable Ready PWR RDY Disable Ready RESTORE Restore Slide 68 (of 118)

Verifying Retention Corner Cases Can Be Tricky
PWR GATED DMA PREMATURE RESTORE SIGNAL SAVE ACTUAL RESTORE Z aa REG A X EXPECTED RESTORE Z bb X REG B bb Slide 69 (of 118)

Low power testbenches Slide 70 (of 118)

A typical low power SOC A complex, asynchronous, mixed signal control system
Software CPU SOC Block Power switches Isolation cells Level Shifters Save/restores VR PMU Power switches Isolation cells Level Shifters Save/restores Button Press Battery/ Always On POR Logic Pin Straps OTP Slide 71 (of 118) 71

Elements of a Low Power Testbench
Slide 72 (of 118)

RAL C API : To generate s/w tests
Interrupts or transition requests Unmodified C C SV VCS Firmware C Code Cosim API Low-Power Tests DPI Pure C API ralgen Register Abstraction RTL DUT gcc Spec .o Embedded SW Slide 73 (of 118)

Coding Guidelines 1’b0 and 1’b1 – no single supply1 or supply0
Use tie_hi_<name> or tie_lo_<name> Initial blocks don’t get retriggered again Be careful with readmem and other initializations in on/off Asynch reset doesn’t get activated again Could be design or testbench issue X-detection monitors can go crazy Avoid stopping the test on “x” in an on/off block! Assertions need to account for off state! Don’t use XMR force statements! … Slide 74 (of 118)

Coverage and assertions
Slide 75 (of 118)

Redefining Coverage LP0 LP1 CORE (ON) LP2
AllOff AllOn AllOn LP2 DOMAIN 1 ON/OFF DOMAIN 2 ON/OFF CORE AllOn ON CORE Domain1 Domain2 AllOff OFF LP0 ON LP1 LP2 AllOn Power Intent elements, Power States, Transitions and Sequences need a Coverage strategy Slide 76 (of 118)

Static Verification covers structural errors
Synthesis (DC) Implementation (ICC) Reports/Log Files Power Intent (UPF) RTL Library (.lib) Design Netlist (UPF’) Functional Checks Netlist Handoff MVRC PG Netlist (UPF’’) Final Signoff Slide 77 (of 118) 77

Dynamic Coverage elements
Power Intent entities Isolation device controls Last known good state Retention elements Power Switch structures Changes in Power Intent vs. desired coverage E.g. Adding retention to block A increases coverage needs E.g. Changing a power state may move an island pair from isolation to level shifting Slide 78 (of 118)

Source assertions may not propagate to all leaves
Source vs. Leaf level assertions Power switch Absence of one leaf-level assertion will cause failure of design Source level assertions cannot be relied upon to ensure correct operation of design ON/OFF PS_ENABLE PMU Source Assertion: When PS_ENABLE =1, ISO_ENABLE = 0 ISO_ENABLE Source assertions may not propagate to all leaves RTL Lines Voltage Islands Power States RTL Assertions Gate Level Assertions 6099 4 8 685 1891 Slide 79 (of 118)

A methodology for low power verification
Slide 80 (of 118)

Industry’s First Verification Methodology for Low-Power
VMM - LP Broad participation by LP experts to contribute and review Slide 81 (of 118) 81

VMM-LP - Industry’s First Verification Methodology for Low-Power
Standards Builds on VMM standard Documented, real LP bug examples Education LP planning, assertions and coverage Verification Best-practice rules and guidelines Reuse LP Extensions Base Class Library & Applications Source code available under open-source license Book and pdf are out! Slide 82 (of 118) 82

Basics of Multi-Voltage Low Power Designs Bug types and profiles
VMM-LP Chapters Basics of Multi-Voltage Low Power Designs Bug types and profiles Dedicated chapter on State retention Testbench and coding guidelines Static Verification Test planning and Dynamic Verification Base Classes and Applications Rules and guidelines Slide 83 (of 118)

has Design rules and Verification rules
VMM- LP.. has a dual focus : Problem identification/education Reusable Verification Methodology has Design rules and Verification rules has Static verification components has new classes has extensions to current classes has little source code in the book : code is provided online Slide 84 (of 118)

Low Power design is functionally quite complex
Conclusions Low Power design is functionally quite complex Verification engineers need to adapt to the new bug profiles A rigorous methodology is needed in the flow involving both static and dynamic verification VMM-LP extends VMM for low power designs VMM-LP introduces new as well as enhanced base classes and applications Slide 85 (of 118)

Every Joule Is Sacred… John Biggs ARM R&D James Prescott Joule
Every Joule is sacred. Every Joule is great. If a Joule is wasted, We all get quite irate…. Every Joule Is Sacred… James Prescott Joule John Biggs ARM R&D Slide 87 (of 118)

What Consumers Care About
Users want more features in their mobile devices: MP3, Camera, Video, GPS... But also need long battery life Convenient form factor, affordable price Battery technology is not evolving fast enough! Need to manage power consumption CPU power demands approximately 30% year on year growth Batteries are not keeping pace with this (maybe 5-10% power increase) Regulator conversion is already at the top end, with little room to manoeuvre Key Message: Consumers want it all, we have to strike a balance Slide 88 (of 118)

Process Migration Alone Is No Longer Enough
Faster Lower power Slide 89 (of 118) 89

RISC is a good starting point...
Pure RISC can go too far in reducing the functionality of each instruction More instruction fetches, less efficient cache usage (more external fetches) ARM retains some carefully chosen CISC like features Conditional instruction execution LDM/STM - Load/Store multiple registers LDR/STR - Load/Store Register with base plus offset Flexible “second operand” on ALU (Barrel Shifter) ARM7TDMI - 16 bit “Thumb” Instruction Set High code density for system size/cost/power savings Greater than 20% code size savings over 32-bit ARM code Memory footprint comparable to 8/16-bit microcontrollers The cheapest, fastest, most reliable components of a computer system are those that are not there! --Gordon Bell Slide 90 (of 118)

Low Power Is A System Problem
Operating System with Software Policies Managing the entry and exit to and from system sleep states System Level Control IP Architectural design partitioning, hardware control Sleep transition protocol management Library Level Support Comprehensive low power components (ISO, Switch, Retention) EDA Software Comprehensive automation yielding ultra low power design with optimal QoR Power Supply Management External power supply control, power supply tolerances, etc. Process Technology Trade-off between a high performance and low leakage process Slide 91 (of 118)

Static Power Dissipation Dynamic Power Dissipation
Total Power Dissipation Total Power Dissipation Leakage Power Dissipation Static Power Dissipation Switching Power Dissipation Dynamic Power Dissipation Minimize Iswitch by: Reducing operating voltage Less switching cap Less switching activity Minimize Ileak by: Reducing operating voltage Fewer leaking transistors Reduce transistor leakage Ileak Iswitch Slide 92 (of 118)

Dynamic Power Optimization
Dynamic Frequency Scaling (DFS) Reduce operating frequency if possible Reduces average power (but not task energy) Eliminates NOPs Dynamic Voltage & Frequency Scaling (DVFS) Requires DFS Reduces voltage if frequency is reduced Reduces task energy Based on characterized frequency – voltage pairs (lookup table) Adaptive Voltage Scaling (AVS) Closed loop optimization of VDD at run-time Can save energy even at fixed frequency Power is the rate of doing work. Energy is the amount of ‘oomph’ needed to the work DFS is used on its own It does: Reduces Average power and could reduce power budget It does not reduce the energy: Halving the frequency only makes the task take twice as long DVFS Open loop, ie no feedback A frequency vs Voltage table is created MUST be characterised over parts and temp Reduces task energy (dynamic portion) AVS Closed loop, ie feedback Compensates for temp and propagation delay (slow/fast silicon) Two inputs to AVS Power Source feedback Slack (HPM) sensors feedback Key Message: There several methods to improve Energy efficiency over last slide Slide 93 (of 118)

ARM IEM Principles (static printable version)
Batteries have finite amounts of energy stored in them Running fast and then idling wastes energy Voltage Reduce Voltage Reduce Voltage Energy Energy Saved Reduce Voltage Energy Run Task in Available Time Run Task Slow as Possible Time Task 1 Idle Task 2 Task 3 Only need to run just fast enough to meet the application deadlines Slide 94 (of 118)

ARM IEM Technology Hardware and software solution for energy management Dynamic control of voltage and frequency scaling. OS Apps Required Performance Volts, MHz Intelligent Energy Controller IEM software Policy Policy Evaluation Stack Dynamic Voltage Controller Dynamic Clock Generator IEM software connects to OS kernel and collects data. Multiple policies categorize the software workload. Prediction of future performance requirement is made. Suitable operating point (Voltage and Frequency) is set. Slide 95 (of 118)

ARM IEM System Implementation
Shows support for IEM included in Cores and PrimeXsys Slide 96 (of 118)

Trends In Power Dissipation
Static power dissipation can no longer be ignored It became significant at 90nm and dominant at 65nm Leakage currents are rising fast Must be controlled by circuit design and optimization tools Slide 97 (of 118)

Total Leakage = ISUB + IGATE + IGIDL + IREV
Leakage Currents Transistors are not perfect switches – they always “leak” Especially the high performance (low Vt) ones Currently sub-threshold leakage dominates Multi-threshold and Power Gating most effective However gate leakage is becoming significant Can be mitigated by high K dielectric material N+ Psub Source Gate Drain ISUB IGIDL IGATE IREV ISUB: Sub-threshold Leakage IGATE: Gate Leakage IGIDL: Gate Induce Drain Leakage IREV: Reverse Bias Junction Leakage Total Leakage = ISUB + IGATE + IGIDL + IREV Slide 98 (of 118)

Leakage Mitigation Techniques
Power Gating nSLEEP Virtual VDD Virtual VSS SLEEP Dual Vt A B C Y Critical Path Low Vt High Vt Lower Operating Voltage VDD VSS Cell sizing 3x 1x A Z A Z VDDB VSSB Non minimum size gate lengths VTCMOS Stack Effect Slide 99 (of 118) 99

Coarse Grain Power Gating
PMOS “Header” Switches SLEEP Virtual VDD VDD Power switches shared by many cells Reduced area and performance impact Ring Based Switch Topology Rings of switches encapsulate the power down block Good for legacy IP, non-intrusive for optimized blocks Preferable if no state retention used – no always-on mesh Can add significant area cost to existing IP Distributed Switch Topology Distributed switch cells in power down block – smaller Can be implemented as a sparse array, in rows or columns Seems to provide better QoR and control of IR drop Better trickle charge management during power-up Slide 100 (of 118) 100

Managing Voltage Drop A reduced supply voltage impacts performance
Adding switches to a power network will necessarily induce a voltage drop in that network in addition to the voltage drop due to power distribution across the mesh Must minimize this additional switch induced voltage drop through considered architecture of the switch topology and switch size Voltage drop across switch also causes standard cells to operate slightly reverse biased if well is tied to VDD Distributed switching can help limit voltage drop Provides a finer control resolution on the switch size and placement Increase the switch density and size in power hot spots Can reuse the always-on power networks (for switch control) to power retention registers and additional always-on logic (save & restore signals) Limit the voltage drop across the switch Slide 101 (of 118) 101

State Retention Considerations
Three possible approaches to state retention Software based state save and restore (OS driven) Hardware based state save and restore via scan structures (via AMBA) Hardware based local state retention with retention registers Choice of retention scheme dependant on a number of factors: Area overhead of retention registers and size of state space to be maintained Performance impact of retention registers Energy cost for save and restore when saving state externally Real time cost for save and restore when saving state externally Approach Standby Leakage Area Overhead S/R Energy Cost Power Gating Only Power Switches & AO Logic Complete Reset Required Power Gating with Software Based Retention State Restore via Software Scan Based Hibernation State Restore via Scan Shift From Memory Local State Retention Power Switches, AO Logic, Retention Registers Minimal as state maintained locally Confidential Slide 102 (of 118)

Managing In-Rush Current
_ PWR _ START _ ACK N_PWR_MAIN_ACK[n:0] VDD VDD_SW 340mV VDD_SW N _ PWR _ START N _ PWR _ MAIN To avoid excessive power rail droop/ground bounce which may: Corrupt locally retained state Impact neighbouring blocks Turn on a small number of “weak” switches first Turn on the “main” switches as VDD_SW ~= VDD 230mV Slide 103 (of 118)

SALT: Synopsys ARM Leakage Technology Demonstrator
Joint development with Synopsys to address EDA implementation ARM926EJS based SoC in TSMC90G Leakage mitigation technology demonstrator Based on R&D Library, Synopsys MV tools Performance scaling: 33/67/100/133% of 300MHz CPU supports 3 “depths” of leakage management State Retention Power Gating Scan-Hibernation Shutdown Support for back/forward bias VTCMOS Retention integrity diagnostics Slide 104 (of 118)

SALT Silicon Measured Results
High Vt devices leak more at high temperatures Over 96% savings across normal mobile operating range Gate leakage starts to dominate at low temperatures Graph shows leakage reduction due to power gating over temperature (compared to mission mode with clocks stopped) Excellent thermal leakage profile for hand held mobile devices! Slide 105 (of 118)

In Summary: Manage power in all modes in which a design operates
Dynamic power during device operation including active leakage Static power dissipation during standby Maintain device performance while minimizing power consumption Meet most aggressive performance targets while minimizing power Aggressive power optimization when running at reduced performance levels Minimize impact to performance by employing aggressive low power techniques Employ a number of low power techniques in a single processor implementation Aggressive techniques for power management Dynamic power minimized through OS directed performance scaling Dynamic power minimized through use of Multi-Vt and Multi-L libraries Standby power minimized through power gating with state retention Additional standby power savings through use of threshold scaling (bias) Slide 106 (of 118) 106

Low Power Intent An IP Providers Perspective
Slide 107 (of 118)

Extent of Soft IP Provider’s Low Power Intent
A Soft IP provider need only declare four things: The "atomic" power domains in the design these can be merged but not split during implementation The state that needs to be retained during shutdown with out prescribing how retention is controlled The signals that need isolating high/low with out prescribing how isolation is controlled The legal power states and sequencing between them with out prescribing absolute voltages Slide 108 (of 118)

Successive Refinement of Low Power Intent
IP Creation 1 IP Configuration 2 IP Implementation 3 RTL RTL Constraint UPF RTL Constr’nt UPF Soft IP Constraint UPF + Golden Source Impl’tion UPF Simulation, Logical Equivalence Checking, … Netlist Synthesis P&R Config’n UPF Configuration UPF + Impl’tion UPF + IP Provider: Creates IP source Creates low power implementation constraints IP Licensee/User: Configures IP for context Validates configuration Freezes “Golden Source” Implements configuration Verifies implementation against “Golden Source” Slide 109 (of 118)

Successive Refinement Example
UPF Constraints IP provider needs to "identify" what is to be isolated with out prescribing how: set_isolation my_iso -domain my_pd \ -clamp_value 0 UPF Configuration System Level simulation guy needs to configure the logical power controls with out having to specify the power supplies: set_isolation -update my_iso -domain my_pd \ -isolation_signal CLAMP -isolation_sense high UPF Implementation Finally the details of power supplies are then added during implementation set_isolation -update my_iso -domain my_pd \ -isolation_power_net VDDG -location parent Or specify it all at the same time: set_isolation my_iso -domain my_pd \ -clamp_value 0 \ -isolation_signal CLAMP -isolation_sense high \ -isolation_power_net VDDG -location parent Slide 110 (of 118)

However UPF-1.0 has a limitation…
Unfortunately UPF-1.0 can’t describe power control nets/pins So for a “bottom up” flow power control pins like “SLEEP” have to be in the RTL However, true Soft IP should be technology independent The sense/width of “SLEEP” will depend the implementation Active high for PMOS active low for NMOS switches May be a “thermometer encoded” bus to manage inrush Good news: this has been fixed in IEEE1801 UPF-2.0 See “create_logic_*” commands Slide 111 (of 118)

Non-contiguous power domains
TOP B Multi-element power domains can lead to unexpected “intra-domain” isolation create_power_domain RED –elements A B iso A C TOP B These can often be avoided with a different approach create_power_domain RED include_scope create_power_domain BLUE –elements C D E BLUE TOP B A D C RED Better to align power domains with logic hierarchy if at all possible create_power_domain RED –elements RED create_power_domain BLUE –elements BLUE Again, fixed in UPF-2.0 set_isolation –diff_supply_only TRUE Slide 112 (of 118)

Controlling Clocks, Resets and Power
Power Gating Controller State Machine S y n c h r o i z e s VDD ( “always on” ) “WAKE - UP” REQ CLOCK _ REQ CLAMP N RETAIN RESET START PWR CLOCK ACK ACK “SLEEP” REQ SYSTEM CLOCK VSS nPWR VDD (“always on”) VDD_SW - Power Gated Region “PD” nCLAMP nRESET CLOCK ENABLE Can use UPF inferred clamps to stop clocks and assert reset Needs care to avoid timing issues Better to use handshaking controlled by a simple state machine Facilitates design reuse and technology portability Slide 113 (of 118)

Sequencing Clocks, Resets and Power
Power down sequence: Stop the clocks Apply isolation Optionally save state Assert reset Remove power Power up sequence: Apply power Remove reset Optionally restore state Remove isolation Start the clocks CLOCK N _ CLAMP RESET SAVE RESTORE PWR Slide 114 (of 118)

A Few “Best Practices”…
Top B2 B1 B4 B3 Avoid non-contiguous power domains Can lead to unwanted isolation cells If in doubt, align power domains with logic hierarchy Avoid using clock gating on both edges of the clock Need for specialised ICGs may limit choice of implementation libraries Avoid partial retention within a power domain Unless the IP has been explicitly designed to support it. User defined partial state retention will require complete re-verification No support for “set_retention –no retention” in UPF-1.0 Ensure that every power domain’s clocks and resets can be controlled externally Slide 115 (of 118)

In Conclusion: Power dissipation is the #1 limiter of design performance Can be mitigated with advanced circuit design and optimization tools Power management is a system problem Power management strategy must be carefully considered from architecture to silicon Need to ease adoption of advanced low power techniques Develop low power IP, tools & techniques (ARM’s IEM & PMK) UPF enables portability of low power intent Provides ability to to compare and contrast a variety of implemention strategies Portable across EDA tools and supported by commercial low power libraries Low power overlay to existing processor IP from ARM Transistors (and silicon) are free. Power is the only real limiter. Optimizing for frequency and/or area may achieve neither. Pat Gelsinger, Intel (DAC2004 Keynote) Slide 116 (of 118)

Did I mention the book? http://www.lpmm-book.org
49% of surveyed customers* identified power management as major concern “How do I describe my power requirements?” “Which advanced techniques are worth the effort?” “I know the concepts, but I don’t know how to implement them” ARM & Synopsys partnering to develop solutions to address these concerns Many years of joint investment in advanced low power programs Driving technology into products: processors, libraries & EDA tools Capturing best practise in the Low Power Methodology Manual Free PDF download: * Source: 2007, Synopsys LPMM customer survey Slide 117 (of 118)

Gary.Delp@LSI.com John.Biggs@ARM.com Srikanth.Jadcherla@synopsys.com
Thank You! Slide 118 (of 118)

Design & Verification of Low Power SoCs

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