1. PUF-Based Key Generation in FPGAs using Variation-Aware Placement Shrikant Vyas, Naveen Dumpala, Russell Tessier, and Daniel Holcomb University of Massachusetts

2. PUF Implementation
Physically unclonable function (PUF) – provides either 1 or 0 depending on chip and location on chip
Reliability is important – should consistently get 1 or 0
Need error correction for unreliable PUFs
Desirable to select “reliable” locations for PUFs

3. PUF Location Makes a Difference
Question: Is PUF behavior spatially correlated?
Answer: No, it isn’t
Goal: Select locations on each chip with best-performing PUFs

4. Area Utilization of PUFs and Error Correcting Code Hardware
Configuration
PUF
BCH
DES56
Total
Failure rate
Variation Agnostic (127,8,31)
2,286
2,902
251
5,439
99% PUFs < 1E-2
Variation Aware (127,22,23)
889
2,235
249
3,373
99% PUFs < 1E-6
Variation aware placement results in lower error rate and less area for error correcting codes
Use BCH error correction .