1. Electronics, Trigger and DAQ for SuperB
U. Marconi, INFN Bologna
Bologna 18/3/2009

2. Organization Two domains: Electronics, Trigger and DAQ DAQ/Online.
Fast Control and Timing System
Data Links
FEB mezzanines
Hardware Trigger (L1)
ROM Boards
DAQ/Online.
HLT cluster
Event Builder
Configuration and monitoring software

3. SuperB Working Conditions
RF in SuperB: ~ 450MHz
Bunch crossing rate RF/2 = 225 MHz.
450 MHz scenario: evaluate the potential implications on the electronics system (however it shouldn’t affect the architecture described here).
225 MHz is a too high a frequency to be used directly to drive the electronics.
A good compromise would be a system clock running at RF/8 = BX/4 = MHz
It permits operating the electronics effectively without synchronizations issues.
The clock can be multiplied locally to run sub-systems faster if needed.
Hardware trigger rate is expected to be of the order of 150 kHz at the instantaneous luminosity of
The sole Bhabha’s background would be 50 kHz.

4. ETD FCTS FEB ROM Hardware Trigger L1 Detector HLT Throttle Request
Clock
Commands
MEP
Destination
Address
Throttle
Request
Clock
Commands
L1 accept
FEB
ROM
L1 accept
Clock
Commands
L1 primitives
Event fragments
Hardware
Trigger L1
Throttle mechanism:
FCTS command to L1
Detector
HLT

5. FEB ETD FEB mezzanines FCTS FEB Mezzanine Throttle Clock Request
Commands
L1 accept
FEB
FEB Mezzanine
L1 Buffer
Event Fragments
L1 Buffer

6. ETD ROM ROM FCTS FEB Mezzanine Optical Output Input Interface FEE
Throttle
Request
Clock
Commands
L1 accept
ROM
Optical
Input
FEB Mezzanine
Output
Interface
FEE
Processing Unit
Event Fragments

7. ETD main features Synchronous and fully triggered system.
Triggered transfer of the event fragments from the FE boards to the ROM, through optical data links.
Asynchronous event fragments transfer to the HLT.
Transfer of Multi Event Packets form ROMs to the HLT in pull mode: to the idle worker node of the HLT cluster asking for data.
Standard for the whole collaboration on custom electronics:
FEB mezzanines
ROM boards
Data Links
FCTS distribution system and receivers (see FEBs).

8. ETD Items Electronics, Trigger, DAQ FEE Mezzanine Management
Overall System architecture
Fast Control & Timing System
Architecture of the system and simulation
Interface with subsystems
Interface with machine
Interface with triggers
Interface with ROM
Interface with FEE
SERDES for FEE clock & control
Off the shelf chipset
TX and/or Rx on FPGA
Component validation for radiation
System synchronization issues
Data Links
SERDES for data links
Radiation Tolerant Tx (on detector)
TX and Rx on FPGA
FEE Mezzanine
Architecture of the mezzanine board
Fast Control System Receiver
L1 Trigger Buffer
Transmission logics
Hardware Trigger
Architecture of the system and simulation
Electromagnetic Calorimeter Trigger
Drift Chamber Trigger
Vertex Detector Trigger
Combined Trigger System
ROM
Requirements as general purpose device
Architecture on custom board
Optical Rx on FPGA
Network interface technology
Implementation on commodity hardware
Optical Rx PCI express module
Network interface PCI express module

9. R&D Issues, priorities, plans have to be better understood and agreed.
FCTS and Data Link
Architecture, components and validation for radiation.
ROM as general purpose standard board
On custom electronics
On commodity hardware
Is it that feasible?
Does it allow us to save money?

10. Interests FCTS Data Links FEB Mezzanine Hardware Trigger ROM
LAL , Napoli, Padova
Data Links
Bologna, LAL , Napoli, Padova
FEB Mezzanine
LAL
Hardware Trigger ?
ROM
Bologna, LAL, Roma Tor Vergata

11. Man Power for TDR (months)
ITEM
Required
Offered
Missing
Management 6
Overall Architecture
FCTS 36 34 2
Data Links 16 20
FEB mezzanine 18 12
Hardware Trigger 48 11 37
ROM 14 22
Requests for contracts:
1 post doc for a Physicist;
1 Engineer .
To work on Hardware Trigger simulations and ROM board design respectively.

12. Conclusions Hardware Trigger not covered yet.
BaBar solution with reduced latency is the baseline.
Bhabha veto is needed and feasible?
Does the vertex detector trigger really help?
How do they affect the combined trigger architecture?
Design of the architecture and of fundamental building blocks of the system launched.