Chapter 1: Introduction

Chapter 1: Introduction
Digital Design Chapter 1: Introduction Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. Copyright © 2010 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

Why Study Digital Design?
1.1 Why Study Digital Design? Look “under the hood” of computers Solid understanding --> confidence, insight, even better programmer when aware of hardware resource issues Electronic devices becoming digital Enabled by shrinking and more capable chips Enables: Better devices: Sound recorders, cameras, cars, cell phones, medical devices,... New devices: Video games, PDAs, ... Known as “embedded systems” Thousands of new devices every year Designers needed: Potential career direction 1995 Portable music players 1997 Satellites 1999 Cell phones 2001 DVD players Video recorders Musical instruments 2003 Cameras TVs ??? 2005 2007 Years shown above indicate when digital version began to dominate (Not the first year that a digital version appeared)

What Does “Digital” Mean?
1.2 What Does “Digital” Mean? Analog signal Infinite possible values Ex: voltage on a wire created by microphone Digital signal Finite possible values Ex: button pressed on a keypad 3 4 2 1 digital signal analog signal a Possible values: 1.00, 1.01, , ... infinite possibilities Possible values: 0, 1, 2, 3, or 4. That’s it. 4 value value 3 2 1 a time time

Digital Signals with Only Two Values: Binary
Binary digital signal -- only two possible values Typically represented as 0 and 1 One binary digit is a bit We’ll only consider binary digital signals Binary is popular because Transistors, the basic digital electric component, operate using two voltages (more in Chpt. 2) Storing/transmitting one of two values is easier than three or more (e.g., loud beep or quiet beep, reflection or no reflection) value 1 time

Example of Digitization Benefit
Volts 1 2 3 original signal time 1 2 3 received signal How fix -- higher, lower, ? Example of Digitization Benefit 11 11 10 10 lengthy transmission (e.g, cell phone) 01 Analog signal (e.g., audio, video) may lose quality Voltage levels not saved/copied/transmitted perfectly Digitized version enables near-perfect save/cpy/tran. “Sample” voltage at particular rate, save sample using bit encoding Voltage levels still not kept perfectly But we can distinguish 0s from 1s time Volts digitized signal time 1 a2d time Can fix—distinguish 0s/1s, restore 1 a lengthy transmission (e.g, cell phone) same Not a perfect re-creation due to a2d and d2a 01 10 11 10 11 Let bit encoding be: 1 V: “01” 2 V: “10” 3 V: “11” Volts 1 2 3 d2a Higher sampling rate and more bits per encoding improves re-creation

Digitization Benefit: Can Store on Digital Media
Store on CD, USB drive, etc. No deterioration. a

Digitized Audio: Compression Benefit
Digitized audio can be compressed e.g., MP3s A CD can hold about 20 songs uncompressed, but about 200 compressed Compression also done on digitized pictures (jpeg), movies (mpeg), and more Digitization has many other benefits too Example compression scheme: 00 means 01 means 1X means X a 00 00 01

How Do We Encode Data as Binary for Our Digital System?
1 button a sensors and other inputs Digital System actuators and other outputs A2D D2A analog phenomena electric signal digital data Some inputs inherently binary Button: not pressed (0), pressed (1) Some inputs inherently digital Just need encoding in binary e.g., multi-button input: encode red=001, blue=010, ... Some inputs analog Need analog-to-digital conversion As done in earlier slide -- sample and encode with bits g r een black blue ed r ed 1 g een black blue 1 g r een black blue ed temperature sensor air 1 33 degrees

How to Encode Text: ASCII, Unicode
Sample ASCII encodings ASCII: 7- (or 8-) bit encoding of each letter, number, or symbol Unicode: Increasingly popular 16-bit encoding Encodes characters from various world languages Question: What does this ASCII bit sequence represent? R E S T a

How to Encode Numbers: Binary Numbers
Each position represents a quantity; symbol in position means how many of that quantity Base ten (decimal) Ten symbols: 0, 1, 2, ..., 8, and 9 More than 9 -- next position So each position power of 10 Nothing special about base used because we have 10 fingers Base two (binary) Two symbols: 0 and 1 More than 1 -- next position So each position power of 2 10 4 3 2 5 1 Q: How much? 2 4 3 1 + = 4 1 5 a

Using Digital Data in a Digital System
A temperature sensor outputs temperature in binary The system reads the temperature, outputs ASCII code: “F” for freezing (0-32) “B” for boiling (212 or more) “N” for normal A display converts its ASCII input to the corresponding letter temperature sensor 1 "33" Digital System if (input <= " ") // "32" output = " " // "F" else if (input >= " ") // "212" output = " " // "B" else output = " " // "N" a "N" 1 display N

Converting from Binary to Decimal
Just add weights 12 is just 1*20, or 110. 1102 is 1*22 + 1*21 + 0*20, or 610. We might think of this using base ten weights: 1*4 + 1*2 + 0*1, or 6. is 1*16 + 0*8 + 0*4 + 0*2 + 0*1, or 1610. is 1* *4 + 1*2 + 1*1 = Notice this time that we didn’t bother to write the weights having a 0 bit. is the same as 1102 above — the leading 0’s don’t change the value. a 2 4 3 1 9 8 7 6 5 Useful to know powers of 2: 16 8 4 2 1 512 256 128 64 32 a Practice counting up by powers of 2: 512 256 128 64 32 16 8 4 2 1

Converting from Decimal to Binary
Desired decimal Current Binary Put 1 in leftmost place without sum exceeding number Track sum number: 12 sum number 16 > 12, too big; (a) Put 0 in 16’s place 16 8 4 2 1 8 <= 12, so put 1 (b) 1 in 8’s place, 8 16 8 4 2 1 current sum is 8 8+4=12 <= 12, so put a 1 1 (c) 1 in 4’s place, 12 16 8 4 2 1 current sum is 12 Reached desired 12, 1 1 (d) so put 0s in remaining done 16 8 4 2 1 places

Converting from Decimal to Binary
Example using a more compact notation Desired decimal Binary number: 23 number 1 1 1 1 sum: 16 8 4 2 1 16 (a) 16 a (b) 20 (c) 22 (d) 23 (e)

Example: DIP-Switch Controlled Channel
Ceiling fan receiver should be set in factory to respond to channel “73” Convert 73 to binary, set DIP switch accordingly Desired value: 73 a Q: 1 1 1 (a) 128 64 32 16 8 4 2 1 (b) sum: 64 72 73 DIP switch 1 channel receiver "34" 1 1 "73" 1 1 1 InA InB if (InA = InB) Out = 1 else Ceiling fan Out = 0 module Out (c)

Base Sixteen: Another Base Used by Designers
Nice because each position represents four base-two positions Compact way to write binary numbers Known as hexadecimal, or just hex 16 4 3 2 8 A F 1000 1010 1111 1 0000 0001 0010 0011 0100 0101 0110 0111 5 6 7 h e x bina r y 1001 1011 1100 1101 1110 9 B C D E Q: Write in hex F a Q: Convert hex A01 to binary a 1010 0000 0001

Decimal to Hex Easy method: convert to binary first, then binary to hex Convert 99 base 10 to hex First convert to binary: 1 1 1 1 a 4 2 1 16 8 32 64 128 Then binary to hex: 6 3 a (Quick check: 6*16 + 3*1 = 96+3 = 99) a

Hex Example: RFID Tag Batteryless tag powered by radio field
Transmits unique identification number Example: 32 bit id 8-bit province number, 8-bit country number, 16-bit animal number Tag contents are in binary But programmers use hex when writing/reading (b) Pr o vince # City # Animal # (c) Pr o vince : 7 City : 160 Animal : 513 (a) (d) (e) 07 A0 02 01 RFID tag (f) Tag ID in hex: 07A00201

Converting To/From Binary by Hand: Summary

Divide-By-2 Method Common in Automatic Conversion
Repeatedly divide decimal number by 2, place remainder in current binary digit (starting from 1s column) Note: Works for any base N—just divide by N instead

Bytes, Kilobytes, Megabytes, and More
Byte: 8 bits Common metric prefixes: kilo (thousand, or 103), mega (million, or 106), giga (billion, or 109), and tera (trillion, or 1012), e.g., kilobyte, or KByte BUT, metric prefixes also commonly used inaccurately 216 = commonly written as “64 Kbyte” Typical when describing memory sizes Also watch out for “KB” for kilobyte vs. “Kb” for kilobit

1.3 Implementing Digital Systems: Programming Microprocessors Vs. Designing Digital Circuits Programmed microprocessor Custom designed digital circuit Desired motion-at-night detector Microprocessors a common choice to implement a digital system Easy to program Cheap (as low as $1) Readily available I P0 void main() { while (1) { P0 = I0 && !I1; // F = a and !b, } 1 I 1 P1 a I 2 P2 1 I 3 P3 b I 4 P4 I 5 P5 1 I 6 P6 F I 7 P7 6:00 7:05 7:06 9:00 9:01 time

Digital Design: When Microprocessors Aren’t Good Enough
With microprocessors so easy, cheap, and available, why design a digital circuit? Microprocessor may be too slow Or too big, power hungry, or costly Wing controller computation task: 50 ms on microprocessor 5 ms as custom digital circuit If must execute 100 times per second: 100 * 50 ms = 5000 ms = 5 seconds 100 * 5 ms = 500 ms = 0.5 seconds Microprocessor too slow, circuit OK.

Digital Design: When Microprocessors Aren’t Good Enough
Commonly, designers partition a system among a microprocessor and custom digital circuits Q: How long for each implementation option? Micro- processor (Read, Compress, and Store) Memory Image Sensor 5+8+1 =14 sec ( a ) Read circuit Compress Memory Store Image Sensor =1.4 sec Sample digital camera task execution times (in seconds) on a microprocessor versus a digital circuit: ( b ) a Task Microprocessor Custom Digital Circuit Read 5 0.1 Compress 8 0.5 Store 1 0.8 Compress circuit Microprocessor (Store) Memory Image Sensor Read =1.6 sec Good compromise ( c )

Chapter Summary Digital systems surround us
Inside computers Inside many other electronic devices (embedded systems) Digital systems use 0s and 1s Encoding analog signals to digital can provide many benefits e.g., audio—higher-quality storage/transmission, compression, etc. Encoding integers as 0s and 1s: Binary numbers Microprocessors (themselves digital) can implement many digital systems easily and inexpensively But often not good enough—need custom digital circuits

Chapter 2: Combinational Logic Design
Digital Design Chapter 2: Combinational Logic Design Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. Copyright © 2010 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

2.1 Introduction Let’s learn to design digital circuits, starting with a simple form of circuit: Combinational circuit Outputs depend solely on the present combination of the circuit inputs’ values Vs. sequential circuit: Has “memory” that impacts outputs too Digital System b=0 F=0 Motion sensor Digital System Light Lamp a b F if a=0 and b=0, then F=0 if a=0 and b=1, then F=0 if a=1 and b=0, then F=1 if a=1 and b=1, then F=0 (b) Digital System b=0 F=0 Digital System b=1 F=1 Digital System if b=0, then F=0 if b=1, then F=1 b=1 F=1 Digital System b=0 F=1 Cannot dete r mine v alue of F solely from present input value (c) (a) a a Note: Slides with animation are denoted with a small red "a" near the animated items

Switches Electronic switches are the basis of binary digital circuits
2.2 Switches Electronic switches are the basis of binary digital circuits Electrical terminology Voltage: Difference in electric potential between two points (volts, V) Analogous to water pressure Resistance: Tendency of wire to resist current flow (ohms, ) Analogous to water pipe diameter Current: Flow of charged particles (amps, A) Analogous to water flow V = I * R (Ohm’s Law) 9 V = I * 2 ohms I = 4.5 A 4.5 A 4.5 A – + 9 V 2 ohms 9 V V 4.5 A a If a 9V potential difference is applied across a 2 ohm resistor, then 4.5 A of current will flow.

Switches A switch has three parts The amazing shrinking switch
control A switch has three parts Source input, and output Current tries to flow from source input to output Control input Voltage that controls whether that current can flow The amazing shrinking switch 1930s: Relays 1940s: Vacuum tubes 1950s: Discrete transistor 1960s: Integrated circuits (ICs) Initially just a few transistors on IC Then tens, hundreds, thousands... input “off” source output input a control input “on” source output input ( b ) discrete transistor IC relay vacuum tube quarter (to see the relative size)

Moore’s Law IC capacity doubling about every 18 months for several decades Known as “Moore’s Law” after Gordon Moore, co-founder of Intel Predicted in 1965 predicted that components per IC would double roughly every year or so Book cover depicts related phenomena For a particular number of transistors, the IC area shrinks by half every 18 months Consider how much shrinking occurs in just 10 years (try drawing it) Enables incredibly powerful computation in incredibly tiny devices Today’s ICs hold billions of transistors The first Pentium processor (early 1990s) needed only 3 million An Intel Pentium processor IC having millions of transistors

The CMOS Transistor CMOS transistor Basic switch in modern ICs 2.3
A positive voltage here... ...attracts electrons here, turning the channel between the source and drain into a conductor conducts does not conduct gate nMOS 1 gate o xide IC pa c kage sou r ce drain does not conduct 1 gate pMOS conducts ( a ) IC Silicon -- not quite a conductor or insulator: Semiconductor

CMOS Transistor Analogy

2.4 Boolean Logic Gates Building Blocks for Digital Circuits (Because Switches are Hard to Work With) “Logic gates” are better digital circuit building blocks than switches (transistors) Why?...

Boolean Algebra and its Relation to Digital Circuits
To understand the benefits of “logic gates” vs. switches, we should first understand Boolean algebra “Traditional” algebra Variables represent real numbers (x, y) Operators operate on variables, return real numbers (2.5*x + y - 3) Boolean Algebra Variables represent 0 or 1 only Operators return 0 or 1 only Basic operators AND: a AND b returns 1 only when both a=1 and b=1 OR: a OR b returns 1 if either (or both) a=1 or b=1 NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1) a 1 b AND a a 1 b OR a 1 NOT

Boolean Algebra and its Relation to Digital Circuits
Developed mid-1800’s by George Boole to formalize human thought Ex: “I’ll go to lunch if Mary goes OR John goes, AND Sally does not go.” Let F represent my going to lunch (1 means I go, 0 I don’t go) Likewise, m for Mary going, j for John, and s for Sally Then F = (m OR j) AND NOT(s) Nice features Formally evaluate m=1, j=0, s=1 --> F = (1 OR 0) AND NOT(1) = 1 AND 0 = 0 Formally transform F = (m and NOT(s)) OR (j and NOT(s)) Looks different, but same function We’ll show transformation techniques soon Formally prove Prove that if Sally goes to lunch (s=1), then I don’t go (F=0) F = (m OR j) AND NOT(1) = (m OR j) AND 0 = 0 a 1 b AND a 1 b OR a 1 NOT

Evaluating Boolean Equations
Evaluate the Boolean equation F = (a AND b) OR (c AND d) for the given values of variables a, b, c, and d: Q1: a=1, b=1, c=1, d=0. Answer: F = (1 AND 1) OR (1 AND 0) = 1 OR 0 = 1. Q2: a=0, b=1, c=0, d=1. Answer: F = (0 AND 1) OR (0 AND 1) = 0 OR 0 = 0. Q3: a=1, b=1, c=1, d=1. Answer: F = (1 AND 1) OR (1 AND 1) = 1 OR 1 = 1. a a 1 b AND a 1 b OR a 1 NOT

Converting to Boolean Equations
Convert the following English statements to a Boolean equation Q1. a is 1 and b is 1. Answer: F = a AND b Q2. either of a or b is 1. Answer: F = a OR b Q3. a is 1 and b is 0. Answer: F = a AND NOT(b) Q4. a is not 0. Answer: (a) Option 1: F = NOT(NOT(a)) (b) Option 2: F = a a

Converting to Boolean Equations
Q1. A fire sprinkler system should spray water if high heat is sensed and the system is set to enabled. Answer: Let Boolean variable h represent “high heat is sensed,” e represent “enabled,” and F represent “spraying water.” Then an equation is: F = h AND e. Q2. A car alarm should sound if the alarm is enabled, and either the car is shaken or the door is opened. Answer: Let a represent “alarm is enabled,” s represent “car is shaken,” d represent “door is opened,” and F represent “alarm sounds.” Then an equation is: F = a AND (s OR d). (a) Alternatively, assuming that our door sensor d represents “door is closed” instead of open (meaning d=1 when the door is closed, 0 when open), we obtain the following equation: F = a AND (s OR NOT(d)). a

Relating Boolean Algebra to Digital Design
(mid-1800s) Boole’s intent: formalize human thought Switches (1930s) Shannon (1938) Digital design Showed application of Boolean algebra to design of switch- based circuits For telephone switching and other electronic uses N O T x y F OR F x y AND Symbol x F x F x y F x y F Truth table 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 y x F 1 x y F Transistor circuit x F Implement Boolean operators using transistors Call those implementations logic gates. Lets us build circuits by doing math -- powerful concept Next slides show how these circuits work. Note: The above OR/AND implementations are inefficient; we’ll show why, and show better ones, later. 1 and 0 each actually corresponds to a voltage range

NOT gate When the input is 0 When the input is 1 1 1 x F ( a ) 1 1 x F
1 F 1 1 x F x F a a ( a ) ( b ) When the input is 0 When the input is 1

OR gate When an input is 1 When both inputs are 0 1 y y x 1 x F F 1 x
x 1 y F 1 y y x 1 x F F 1 x y x y a a 1 1 ( a ) ( b ) When an input is 1 When both inputs are 0

AND gate When both inputs are 1 When an input is 0 1 1 1 x y x y F F 1
x 1 y F 1 1 1 x y x y F F 1 1 y y 1 1 x x a a 1 1 ( b ) ( a ) When both inputs are 1 When an input is 0

Building Circuits Using Gates
Recall Chapter 1 motion-in-dark example Turn on lamp (F=1) when motion sensed (a=1) and no light (b=0) F = a AND NOT(b) Build using logic gates, AND and NOT, as shown We just built our first digital circuit!

Example: Converting a Boolean Equation to a Circuit of Logic Gates
Start from the output, work back towards the inputs Q: Convert the following equation to logic gates: F = a AND NOT( b OR NOT(c) ) a a b F c

More examples Start from the output, work back towards the inputs a F
F = (a AND NOT(b)) OR (b AND NOT(c)) 2 1 3 F = a AND (s OR d) 1 2 a a b s F F d c ( a ) a a ( b ) Start from the output, work back towards the inputs

Using gates with more than 2 inputs
Can think of as AND(a,b,c)

Example: Seat Belt Warning Light System
Design circuit for warning light Sensors s=1: seat belt fastened k=1: key inserted Capture Boolean equation seat belt not fastened, and key inserted Convert equation to circuit Timing diagram illustrates circuit behavior We set inputs to any values Output set according to circuit w = NOT(s) AND k a Inputs 1 k 1 s a Outputs 1 w time

Gates vs. switches Notice w = NOT(s) AND k
Boolean algebra enables easy capture as equation and conversion to circuit How design with switches? Of course, logic gates are built from switches, but we think at level of logic gates, not switches w = NOT(s) AND k a

More examples: Seat belt warning light extensions
Only illuminate warning light if person is in the seat (p=1), and seat belt not fastened and key inserted w = p AND NOT(s) AND k k p s w Belt W a r n a Given t=1 for 5 seconds after key inserted. Turn on warning light when t=1 (to check that warning lights are working) w = (p AND NOT(s) AND k) OR t a

Some Gate-Based Circuit Drawing Conventions
x y F no es no y es a not ok ok a

2.5 Boolean Algebra By defining logic gates based on Boolean algebra, we can use algebraic methods to manipulate circuits Notation: Writing a AND b, a OR b, NOT(a) is cumbersome Use symbols: a * b (or just ab), a + b, and a’ Original: w = (p AND NOT(s) AND k) OR t New: w = ps’k + t Spoken as “w equals p and s prime and k, or t” Or just “w equals p s prime k, or t” s’ known as “complement of s” While symbols come from regular algebra, don’t say “times” or “plus” "product" and "sum" are OK and commonly used Boolean algebra precedence, highest precedence first. Symbol Name Description ( ) Parentheses Evaluate expressions nested in parentheses first ’ NOT Evaluate from left to right * AND Evaluate from left to right + OR Evaluate from left to right

Boolean Algebra Operator Precedence
Evaluate the following Boolean equations, assuming a=1, b=1, c=0, d=1. Q1. F = a * b + c. Answer: * has precedence over +, so we evaluate the equation as F = (1 *1) + 0 = (1) + 0 = = 1. Q2. F = ab + c. Answer: the problem is identical to the previous problem, using the shorthand notation for *. Q3. F = ab’. Answer: we first evaluate b’ because NOT has precedence over AND, resulting in F = 1 * (1’) = 1 * (0) = 1 * 0 = 0. Q4. F = (ac)’. Answer: we first evaluate what is inside the parentheses, then we NOT the result, yielding (1*0)’ = (0)’ = 0’ = 1. Q5. F = (a + b’) * c + d’. Answer: Inside left parentheses: (1 + (1’)) = (1 + (0)) = (1 + 0) = 1. Next, * has precedence over +, yielding (1 * 0) + 1’ = (0) + 1’. The NOT has precedence over the OR, giving (0) + (1’) = (0) + (0) = = 0. a Boolean algebra precedence, highest precedence first. Symbol Name Description ( ) Parentheses Evaluate expressions nested in parentheses first ’ NOT Evaluate from left to right * AND Evaluate from left to right + OR Evaluate from left to right

Boolean Algebra Terminology
Example equation: F(a,b,c) = a’bc + abc’ + ab + c Variable Represents a value (0 or 1) Three variables: a, b, and c Literal Appearance of a variable, in true or complemented form Nine literals: a’, b, c, a, b, c’, a, b, and c Product term Product of literals Four product terms: a’bc, abc’, ab, c Sum-of-products Equation written as OR of product terms only Above equation is in sum-of-products form. “F = (a+b)c + d” is not.

Boolean Algebra Properties
Example uses of the properties Commutative a + b = b + a a * b = b * a Distributive a * (b + c) = a * b + a * c Can write as: a(b+c) = ab + ac a + (b * c) = (a + b) * (a + c) (This second one is tricky!) Can write as: a+(bc) = (ab)(ac) Associative (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) Identity 0 + a = a + 0 = a 1 * a = a * 1 = a Complement a + a’ = 1 a * a’ = 0 To prove, just evaluate all possibilities Show abc’ equivalent to c’ba. Use commutative property: a*b*c’ = a*c’*b = c’*a*b = c’*b*a Show abc + abc’ = ab. Use first distributive property abc + abc’ = ab(c+c’). Complement property Replace c+c’ by 1: ab(c+c’) = ab(1). Identity property ab(1) = ab*1 = ab. Show x + x’z equivalent to x + z. Second distributive property Replace x+x’z by (x+x’)*(x+z). Replace (x+x’) by 1, replace 1*(x+z) by x+z. a

Example that Applies Boolean Algebra Properties
Want automatic door opener circuit (e.g., for grocery store) Output: f=1 opens door Inputs: p=1: person detected h=1: switch forcing hold open c=1: key forcing closed Want open door when h=1 and c=0, or h=0 and p=1 and c=0 Equation: f = hc’ + h’pc’ Can the circuit be simplified? f = hc' + h'pc‘ f = c'h + c'h'p (by the commutative property) f = c'(h + h'p) (by the first distrib. property) f = c'((h+h')*(h+p)) (2nd distrib. prop.; tricky one) f = c'((1)*(h + p)) (by the complement property) f = c'(h+p) (by the identity property) a a DoorOpener h Simplified circuit f c p Simplification of circuits is covered in Sec / Sec 6.2.

Example that Applies Boolean Algebra Properties
Found inexpensive chip that computes: f = c’hp + c’hp’ + c’h’p Can we use it for the door opener? Is it the same as f = hc’ + h’pc’? Apply Boolean algebra: f h c p DoorOpener Commutative a + b = b + a a * b = b * a Distributive a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c) Associative (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) Identity 0 + a = a + 0 = a 1 * a = a * 1 = a Complement a + a’ = 1 a * a’ = 0 f = c’hp + c’hp’ + c’h’p f = c’h(p + p’) + c’h’p (by the distributive property) f = c’h(1) + c’h’p (by the complement property) f = c’h + c’h’p (by the identity property) f = hc’ + h’pc’ (by the commutative property) Same! Yes, we can use it. a

Boolean Algebra: Additional Properties
Null elements a + 1 = 1 a * 0 = 0 Idempotent Law a + a = a a * a = a Involution Law (a’)’ = a DeMorgan’s Law (a + b)’ = a’b’ (ab)’ = a’ + b’ Very useful! To prove, just evaluate all possibilities

Example Applying DeMorgan’s Law
(a + b)’ = a’b’ (ab)’ = a’ + b’ Aircraft lavatory sign example Behavior Three lavatories, each with sensor (a, b, c), equals 1 if door locked Light “Available” sign (S) if any lavatory available Equation and circuit S = a’ + b’ + c’ Transform (abc)’ = a’+b’+c’ (by DeMorgan’s Law) S = (abc)’ New circuit Alternative: Instead of lighting “Available,” light “Occupied” Opposite of “Available” function S = a’ + b’ + c’ So S’ = (a’ + b’ + c’)’ S’ = (a’)’ * (b’)’ * (c’)’ (by DeMorgan’s Law) S’ = a * b * c (by Involution Law) Makes intuitive sense Occupied if all doors are locked Circuit a b c S Circuit S a b c

Example Applying Properties
Commutative a + b = b + a a * b = b * a Distributive a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c) Associative (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) Identity 0 + a = a + 0 = a 1 * a = a * 1 = a Complement a + a’ = 1 a * a’ = 0 For door opener f = c'(h+p) , prove door stays closed (f=0) when c=1 f = c'(h+p) Let c = (door forced closed) f = 1'(h+p) f = 0(h+p) f = 0h + 0p (by the distributive property) f = (by the null elements property) f = 0 Null elements a + 1 = 1 a * 0 = 0 Idempotent Law a + a = a a * a = a Involution Law (a’)’ = a DeMorgan’s Law (a + b)’ = a’b’ (ab)’ = a’ + b’

Complement of a Function
Commonly want to find complement (inverse) of function F 0 when F is 1; 1 when F is 0 Use DeMorgan’s Law repeatedly Note: DeMorgan’s Law defined for more than two variables, e.g.: (a + b + c)' = (abc)' (abc)' = (a' + b' + c') Complement of f = w'xy + wx'y'z' f ' = (w'xy + wx'y'z')' f ' = (w'xy)'(wx'y'z')' (by DeMorgan’s Law) f ' = (w+x'+y')(w'+x+y+z) (by DeMorgan’s Law) Can then expand into sum-of-products form

Representations of Boolean Functions
2.6 Representations of Boolean Functions English 1: F outputs 1 when a is 0 and b is 0, or when a is 0 and b is 1. English 2: F outputs 1 when a is 0, regardless of b’s value ( a ) a b F Circuit 1 ( c ) a b F 1 Equation 1: F(a,b) = a’b’ + a’b 1 1 Equation 2: F(a,b) = a’ 1 ( b ) 1 1 a Truth table a F Circuit 2 ( d ) T he function F A function can be represented in different ways Above shows seven representations of the same functions F(a,b), using four different methods: English, Equation, Circuit, and Truth Table

Truth Table Representation of Boolean Functions
Define value of F for each possible combination of input values 2-input function: 4 rows 3-input function: 8 rows 4-input function: 16 rows Q: Use truth table to define function F(a,b,c) that is 1 when abc is 5 or greater in binary a b F c 1 a b F ( ) c 1 d a b F ( ) 1 1 1 1 ( a ) c 1 a b F a 1

Converting among Representations
Can convert from any representation to another Common conversions Equation to circuit (we did this earlier) Circuit to equation Start at inputs, write expression of each gate output c c' h F = c'(h+p) p h+p

Converting among Representations
More common conversions Truth table to equation (which we can then convert to circuit) Easy–just OR each input term that should output 1 Equation to truth table Easy—just evaluate equation for each input combination (row) Creating intermediate columns helps Inputs Outputs Term a b F F = sum of 1 a’b’ 1 1 a’b 1 1 1 F = a’b’ + a’b Q: Convert to equation c 1 a b F Q: Convert to truth table: F = a’b’ + a’b a 1 b F Inputs Output ' ' b ab’c a 1 1 1 abc’ abc a F = ab’c + abc’ + abc

Example: Converting from Truth Table to Equation
Parity bit: Extra bit added to data, intended to enable detection of error (a bit changed unintentionally) e.g., errors can occur on wires due to electrical interference Even parity: Set parity bit so total number of 1s (data + parity) is even e.g., if data is 001, parity bit is 1  0011 has even number of 1s Want equation, but easiest to start from truth table for this example a b c P Convert to eqn. P = a'b'c + a'bc' + ab'c' + abc

Example: Converting from Circuit to Truth Table
First convert to circuit to equation, then equation to table a ab (ab)' b c' F c (ab)'c' Inputs Outputs a b c ab (ab)' c' F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Standard Representation: Truth Table
How can we determine if two functions are the same? Recall automatic door example Same as f = hc’ + h’pc’? Used algebraic methods But if we failed, does that prove not equal? No. Solution: Convert to truth tables Only ONE truth table representation of a given function Standard representation—for given function, only one version in standard form exists f = c’hp + c’hp’ + c’h’ f = c’h(p + p’) + c’h’p f = c’h(1) + c’h’p f = c’h + c’h’p (what if we stopped here?) f = hc’ + h’pc’ Q: Determine if F=ab+a’ is same function as F=a’b’+a’b+ab, by converting each to truth table first a 1 b F F = ab + a' a 1 b F F = a’b’ + a’b + ab a Same

Truth Table Canonical Form
Q: Determine via truth tables whether ab+a' and (a+b)' are equivalent a 1 b F F = ab + a ' a 1 b F F = (a+b) ' Not equivalent a

Canonical Form – Sum of Minterms
Truth tables too big for numerous inputs Use standard form of equation instead Known as canonical form Regular algebra: group terms of polynomial by power ax2 + bx + c (3x2 + 4x + 2x > 5x2 + 4x + 4) Boolean algebra: create sum of minterms Minterm: product term with every function literal appearing exactly once, in true or complemented form Just multiply-out equation until sum of product terms Then expand each term until all terms are minterms Q: Determine if F(a,b)=ab+a’ is equivalent to F(a,b)=a’b’+a’b+ab, by converting first equation to canonical form (second already is) F = ab+a’ (already sum of products) F = ab + a’(b+b’) (expanding term) F = ab + a’b + a’b’ (Equivalent – same three terms as other equation) a

Canonical Form – Sum of Minterms
Q: Determine whether the functions G(a,b,c,d,e) = abcd + a'bcde and H(a,b,c,d,e) = abcde + abcde' + a'bcde + a'bcde(a' + c) are equivalent. G = abcd + a'bcde G = abcd(e+e') + a'bcde G = abcde + abcde' + a'bcde G = a'bcde + abcde' + abcde (sum of minterms form) H = abcde + abcde' + a'bcde + a'bcde(a' + c) H = abcde + abcde' + a'bcde + a'bcdea' + a'bcdec H = abcde + abcde' + a'bcde + a'bcde + a'bcde H = abcde + abcde' + a'bcde H = a'bcde + abcde' + abcde Equivalent a

Compact Sum of Minterms Representation
List each minterm as a number Number determined from the binary representation of its variables’ values a'bcde corresponds to 01111, or 15 abcde' corresponds to 11110, or 30 abcde corresponds to 11111, or 31 Thus, H = a'bcde + abcde' + abcde can be written as: H = ∑m(15,30,31) "H is the sum of minterms 15, 30, and 31"

Multiple-Output Circuits
Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c’, G = ab + bc a b c F G ( ) Option 1: Separate circuits a b c F G ( ) a a Option 2: Shared gates

Multiple-Output Example: BCD to 7-Segment Converter

Multiple-Output Example: BCD to 7-Segment Converter
f b g e c d a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z ... a

Combinational Logic Design Process
2.7 Combinational Logic Design Process Step Description Step 1: Capture behavior Create a truth table or equations, whichever is most natural for the given problem, to describe the desired behavior of each output of the combinational logic. Capture the function This substep is only necessary if you captured the function using a truth table instead of equations. Create an equation for each output by ORing all the minterms for that output. Simplify the equations if desired. 2A: Create equations Step 2: Convert to circuit 2B: Implement as a gate-based circuit For each output, create a circuit corresponding to the output’s equation. (Sharing gates among multiple outputs is OK optionally.)

Example: Three 1s Pattern Detector
Problem: Detect three consecutive 1s in 8-bit input: abcdefgh  1  0  1 Step 1: Capture the function Truth table or equation? Truth table too big: 2^8=256 rows Equation: create terms for each possible case of three consecutive 1s y = abc + bcd + cde + def + efg + fgh Step 2a: Create equation -- already done Step 2b: Implement as a gate-based circuit a a bcd def fgh abc cde efg y a b c d e f g h

Example: Number of 1s Counter
Problem: Output in binary on two outputs yz the # of 1s on three inputs 010  01 101  10 000  00 Step 1: Capture the function Truth table or equation? Truth table is straightforward Step 2a: Create equations y = a’bc + ab’c + abc’ + abc z = a’b’c + a’bc’ + ab’c’ + abc Optional: Let's simplify y: y = a'bc + ab'c + ab(c' + c) = a'bc + ab'c + ab Step 2b: Implement as a gate-based circuit a a b c z a a b c y

Simplifying Notations
Used in previous circuit a b c (a) a b c b' (b) a List inputs multiple times  Less wiring in drawing Draw inversion bubble rather than inverter. Or list input as complemented.

Example: Keypad Converter
Keypad has 7 outputs One per row One per column Key press sets one row and one column output to 1 Press "5"  r2=1, c2=1 Goal: Convert keypad outputs into 4-bit binary number 0-9  0000 to 1001 *  1010, #  1011 nothing pressed: 1111

Example: Keypad Converter
Step 1: Capture behavior Truth table too big (2^7 rows); equations not clear either Informal table can help a Step 2b: Implement as circuit (note sharable gates) ... a w = r3c2 + r3c3 + r4c1 + r4c3 + r1'r2'r3'r4'c1'c2'c3' x = r2c1 + r2c2 + r2c3 + r3c1 + r1'r2'r3'r4’c1'c2'c3' y = r1c2 + r1c3 + r2c3 + r3c1 + r4c1 + r4c3 + r1'r2'r3'r4'c1'c2'c3' z = r1c1 + r1c3 + r2c2 + r3c1 + r3c3 + r4c3 + r1'r2'r3'r4'c1'c2'c3' a

Example: Sprinkler Controller
Microprocessor outputs which zone to water (e.g., cba=110 means zone 6) and enables watering (e=1) Decoder should set appropriate valve to 1 Step 1: Capture behavior d0 = a'b'c'e a d1 = a'b'ce d2 = a'bc'e d3 = a'bce d4 = ab'c'e d5 = ab'ce d6 = abc'e d7 = abce Equations seem like a natural fit

Example: Sprinkler Controller
Step 2b: Implement as circuit d0 = a'b'c'e d1 = a'b'ce d2 = a'bc'e d3 = a'bce d4 = ab'c'e d5 = ab'ce d6 = abc'e d7 = abce

More Gates 2.8 NAND: Opposite of AND (“NOT AND”)
1 x y F 1 x y F NAND x 1 y F NOR x 1 y F XOR x 1 y F XNOR NAND NOR x F y a x y F 1 1 1 1 1 1 1 NAND: Opposite of AND (“NOT AND”) NOR: Opposite of OR (“NOT OR”) XOR: Exactly 1 input is 1, for 2-input XOR. (For more inputs -- odd number of 1s) XNOR: Opposite of XOR (“NOT XOR”) NAND same as AND with power & ground switched nMOS conducts 0s well, but not 1s (reasons beyond our scope) – so NAND is more efficient Likewise, NOR same as OR with power/ground switched NAND/NOR more common AND in CMOS: NAND with NOT OR in CMOS: NOR with NOT

More Gates: Example Uses
Aircraft lavatory sign example S = (abc)’ Detecting all 0s Use NOR Detecting equality Use XNOR Detecting odd # of 1s Use XOR Useful for generating “parity” bit common for detecting errors Circuit a b S c 1 a0 b0 a1 b1 a2 b2 A=B

Completeness of NAND Any Boolean function can be implemented using just NAND gates. Why? Need AND, OR, and NOT NOT: 1-input NAND (or 2-input NAND with inputs tied together) AND: NAND followed by NOT OR: NAND preceded by NOTs Thus, NAND is a universal gate Can implement any circuit using just NAND gates Likewise for NOR

Number of Possible Boolean Functions
How many possible functions of 2 variables? 22 rows in truth table, 2 choices for each 2(22) = 24 = 16 possible functions N variables 2N rows 2(2N) possible functions a 1 b 0 or choices F 24 = 16 possible functions a b f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a b b’ a’ 1 a OR b a AND b a XOR b a NOR b a XNOR b a NAND b

2.9 Decoders and Muxes Decoder: Popular combinational logic building block, in addition to logic gates Converts input binary number to one high output 2-input decoder: four possible input binary numbers So has four outputs, one for each possible input binary number Internal design AND gate for each output to detect input combination Decoder with enable e Outputs all 0 if e=0 Regular behavior if e=1 n-input decoder: 2n outputs i0 i1 d0 d1 d2 d3 1 i0 d0 d1 d2 d3 i1 i1’i0’ i1’i0 i1i0’ i1i0 i0 i1 d0 d1 d2 d3 e 1 a a

Decoder Example New Year’s Eve Countdown Display 1 2
Microprocessor counts from 59 down to 0 in binary on 6-bit output Want illuminate one of 60 lights for each binary number Use 6x64 decoder 4 outputs unused 1 2 1 1 Happy New Year i0 d0 i1 d1 1 i2 d2 2 Processor i3 d3 3 a i4 i5 d58 e d59 d60 d61 58 6x64 d62 59 dcd d63

Multiplexor (Mux) Mux: Another popular combinational building block
Routes one of its N data inputs to its one output, based on binary value of select inputs 4 input mux  needs 2 select inputs to indicate which input to route through 8 input mux  3 select inputs N inputs  log2(N) selects Like a rail yard switch

Mux Internal Design 2x1 mux 4x1 mux i0 (1*i0=i0) 1 i0 (0+i0=i0) s0 d
× 1 2 × 1 2 × 1 i1 i0 s0 d 1 i0 (0+i0=i0) i0 i0 d d i1 i1 s0 s0 a 2x1 mux i0 4 × 1 i2 i1 i3 s1 s0 d 4x1 mux

Mux Example City mayor can set four switches up or down, representing his/her vote on each of four proposals, numbered 0, 1, 2, 3 City manager can display any such vote on large green/red LED (light) by setting two switches to represent binary 0, 1, 2, or 3 Use 4x1 mux Mayor’s switches a 1 i0 4x1 i2 i1 i3 s1 s0 d on/off 2 Proposal Green/ Red LED 3 4 manager's switches

Muxes Commonly Together – N-bit Mux
1 a3 i0 Simplifying notation: d b3 i1 s0 4 4-bit 2x 1 4 C a2 i0 2x1 d A I 4 b2 i1 s0 4 D C is short B I 1 f or 2x 1 a1 i0 s0 d b1 i1 c3 s0 s0 c2 2x 1 a0 i0 d c1 b0 i1 s0 s0 c0 Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0) 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B

From the car's central computer
N-bit Mux Example From the car's central computer I0 8-bit 4x1 I2 I1 I3 s1 s0 D a 8 T A 8 To the above-mirror display 8 D I 8 M 8 x y W e'll design this later b utton Four possible display items Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) – each is 8-bits wide Choose which to display on D using two inputs x and y Pushing button sequences to the next item Use 8-bit 4x1 mux

Additional Considerations Non-Ideal Gate Behavior -- Delay
2.10 Additional Considerations Non-Ideal Gate Behavior -- Delay 1 1 1 x x x x F y 1 1 1 y y y (1.8 V) 1 1 1 F F F (0 V) time time time ( a ) ( b ) ( c ) ideal a more realistic a with delay but otherwise ideal a Real gates have some delay Outputs don’t change immediately after inputs change

Circuit Delay and Critical Path
Belt W a r n k 1 ns p 1 ns 1 ns 1 ns w a s 1 ns = 5 ns 1 ns 1 ns 1 ns = 6.5 ns 0.5 ns t 1 ns 1+1+1 = 3 ns C r itical path del a y = 6.5 ns Henc e , circuit ’ s del a y is 6.5 ns Wires also have delay Assume gates and wires have delays as shown Path delay – time for input to affect output Critical path – path with longest path delay Circuit delay – delay of critical path

Active Low Inputs Data inputs: flow through component (e.g., mux data input) Control input: influence component behavior Normally active high – 1 causes input to carry out its purpose Active low – Instead, 0 causes input to carry out its purpose Example: 2x4 decoder with active low enable 1 disables decoder, 0 enables Drawn using inversion bubble i0 i1 d0 d1 d2 d3 e 1 ( a ) b

Schematic Capture and Simulation
Inputs Inputs a i0 i0 i1 i1 Simulate Simulate Outputs Outputs d3 d3 d2 d2 d1 d1 d0 d0 Schematic capture Computer tool for user to capture logic circuit graphically Simulator Computer tool to show what circuit outputs would be for given inputs Outputs commonly displayed as waveform

Chapter Summary Combinational circuits
Circuit whose outputs are function of present inputs No “state” Switches: Basic component in digital circuits Boolean logic gates: AND, OR, NOT – Better building block than switches Enables use of Boolean algebra to design circuits Boolean algebra: Uses true/false variables/operators Representations of Boolean functions: Can translate among Combinational design process: Translate from equation (or table) to circuit through well-defined steps More gates: NAND, NOR, XOR, XNOR also useful Muxes and decoders: Additional useful combinational building blocks

Chapter 3: Sequential Logic Design -- Controllers
Digital Design Chapter 3: Sequential Logic Design -- Controllers Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. Copyright © 2010 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

Must know sequence of past inputs to know output
3.1 Introduction 1 a 1 Sequential circuit Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs Stores bits, also known as having “state” Simple example: a circuit that counts up in binary This chapter will: Design a new building block, a flip-flop, to store one bit Combine flip-flops to build multi-bit storage – register Describe sequential behavior with finite state machines Convert a finite state machine to a controller –sequential circuit with a register and combinational logic Combinational digital circuit F b 1 a ? Sequential digital circuit F b Must know sequence of past inputs to know output Note: Slides with animation are denoted with a small red "a" near the animated items

Storing One Bit – Flip-Flops Example Requiring Bit Storage
3.2 Storing One Bit – Flip-Flops Example Requiring Bit Storage Bit Storage Blue light Call button Cancel 1 Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Stays off after button released Logic gate circuit to implement this? 1. Call button pressed – light turns on Bit Storage Blue light Call button Cancel 2. Call button released – light stays on 1 a Q Call Cancel Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Need some form of “feedback” in the circuit Bit Storage Blue light Call button Cancel 3. Cancel button pressed – light turns off a

First attempt at Bit Storage
Need some sort of feedback Does circuit on the right do what we want? No: Once Q becomes 1 (when S=1), Q stays 1 forever – no value of S can bring Q back to 0 S Q t t 1 Q S t 1 Q S 1 t Q S 1 t Q S a 1 Q t S

Bit Storage Using an SR Latch
Q S (set) SR latch R (reset) Does the circuit to the right, with cross-coupled NOR gates, do what we want? Yes! How did someone come up with that circuit? Maybe just trial and error, a bit of insight... R=1 S=0 t Q 1 R S t Q S=0 R=0 t Q S=1 R=0 t Q R=0 S=0 Recall NOR… 1 1 1 1 1 1 1 1 1 1 X a

Example Using SR Latch for Bit Storage
SR latch can serve as bit storage in previous example of flight-attendant call button Call=1 : sets Q to 1 Q stays 1 even after Call=0 Cancel=1 : resets Q to 0 But, there’s a problem... Bit S t o r age Blue lig h C all but on an c el 1 C all S button a Blue lig h t Q C an c el 1 button R

Problem with SR Latch Problem
If S=1 and R=1 simultaneously, we don’t know what value Q will take a Q may oscillate. Then, because one path will be slightly longer than the other, Q will eventually settle to 1 or 0 – but we don’t know which. Known as a race condition. a

Problem with SR Latch Designer might try to avoid problem using external circuit Circuit should prevent SR from ever being 11 But 11 can occur due to different path delays 1 Call 1 Cncl 1 S Assume 1 ns delay per gate. The longer path from Call to R than from Call to S causes SR=11 for short time – could be long enough to cause oscillation SR = 11 1 R 2 ns

Problem with SR Latch Glitch can also cause undesired set or reset
Suppose this wire has 4 ns delay

Solution: Level-Sensitive SR Latch
Add enable input “C” Only let S and R change when C=0 Ensure circuit in front of SR never sets SR=11, except briefly due to path delays Set C=1 after time for S and R to be stable When C becomes 1, the stable S and R value passes through the two AND gates to the SR latch’s S1 R1 inputs. R1 S1 S C R Level-sensitive SR latch Q 1 S1 R1 Correct v alues when ena b led Call Cncl S R C S C Q ’ R Level-sensitive SR latch S Call S1 Level-sensitive SR latch symbol C Clk Q Glitch on R (or S) doesn’t affect R1 (or (S1) R R1 Cncl a

Level-Sensitive D Latch
SR latch requires careful design to ensure SR=11 never occurs D latch relieves designer of that burden Inserted inverter ensures R always opposite of S a D Q ’ C D latch symbol a

Problem with Level-Sensitive D Latch
D latch still has problem (as does SR latch) When C=1, through how many latches will a signal travel? Depends on how long C=1 Clk_A – signal may travel through multiple latches Clk_B – signal may travel through fewer latches 1 1? 1? 1?

Problem with Level-Sensitive D Latch
0–>1 D2 D1 S1 S2 0–>1 0–>1 0–>1 C2 C1 D3 Q3 D4 Q4 C3 C4 Q1 R2 Q2 R1 1–>0 0–>1 0–>1 1–>0 Clk ( a ) Short clock Long clock Clk ( c ) Clk D1 Q1/D2 S2 R2 Q2 D1 Q1/D2 Q1 doesn't change a a S2 R2 Q2 2nd latch set ( b )

D Flip-Flop Flip-flop: Bit storage that stores on clock edge
Can we design bit storage that only stores a value on the rising edge of a clock signal? Flip-flop: Bit storage that stores on clock edge One design – master-servant Clk = 0 – master enabled, loads D, appears at Qm. Servant disabled. Clk = 1 – Master disabled, Qm stays same. Servant latch enabled, loads Qm, appears at Qs. Thus, value at D (and hence at Qm) when Clk changes from 0 to 1 gets stored into servant rising edges a Clk Clk D/Dm Qm/Ds Cm Cs Qs D latch master se r v ant D Dm Ds Cs Qm Qs Q Cm Clk D flip-flop Note: Hundreds of different flip-flop designs exist

D Flip-Flop Solves problem of not knowing through how many latches a signal travels when C=1 In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously – then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1. D1 Q1 D2 Q2 D3 Q3 D4 Q4 Y Clk Clk_A Clk_B 1 1 Two latches inside each flip-flop

D Flip-Flop Q ’ D D Q ’ Q Symbol for rising-edge triggered D flip-flop
Internal design: Just invert servant clock rather than master The triangle means edge-triggered clock input Q Symbol for rising-edge triggered D flip-flop Symbol for falling-edge triggered D flip-flop Clk rising edges falling edges Clk

D Latch vs. D Flip-Flop Latch is level-sensitive
Stores D when C=1 Flip-flop is edge triggered Stores D when C changes from 0 to 1 Saying “level-sensitive latch” or “edge-triggered flip-flop” is redundant Comparing behavior of latch and flip-flop: Clk 1 2 a D 3 4 5 6 Latch follows D while Clk is 1 Q (D latch) 7 8 Flip-flop only loads D during Clk rising edge Q (D flip-flop) 9 10

Clock Signal Flip-flop Clk inputs typically connect to one clock signal Coming from an oscillator component Generates periodic pulsing signal Below: "Period" = 20 ns, "Frequency" = 1/20 ns = 50 MHz "Cycle" is duration of 1 period (20 ns); below shows 3.5 cycles 0 ns Time : Clk 10 ns 20 ns 30 ns 40 ns 1 50 ns 60 ns Period/Freq shortcut: Remember 1 ns  1 GHz

Flight-Attendant Call Button Using D Flip-Flop
D flip-flop will store bit Inputs are Call, Cancel, and present value of D flip-flop, Q Truth table shown below D Q Clk Call b utton Cancel Blue light Comb. Circuit Cncl L a Preserve value: if Q=0, make D=0; if Q=1, make D=1 Cancel -- make D=0 D Q’ Q Clk C all but t on an c el Blue light Call Cancel Call -- make D=1 Let’s give priority to Call -- make D=1 Circuit derived from truth table, using Chapter 2 combinational logic design process

Bit Storage Summary We considered increasingly better bit storage until we arrived at the robust D flip-flop bit storage

Basic Register Typically, we store multi-bit items
e.g., storing a 4-bit binary number Register: multiple flip-flops sharing clock signal From this point, we’ll use registers for bit storage No need to think of latches or flip-flops But now you know what’s inside a register

Example Using Registers: Temperature Display
Temperature history display Sensor outputs temperature as 5-bit binary number Timer pulses C every hour Record temperature on each pulse, display last three recorded values Present 1 hour ago 2 hours ago Display Display Display Temperature sensor 24 x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 21 x3 18 x2 a TemperatureHistoryStorage x1 x0 timer C

Example Using Registers: Temperature Display
Use three 5-bit registers Q4 C x4 x3 x2 x1 x0 Q3 Q2 Q1 Q0 R a b I 4 3 2 1 a4 a3 a2 a1 a0 c b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 TemperatureHistoryStorage 24 21 18 a x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27 C a R a 18 21 24 25 26 27 Note that registers only loaded on rising clock edges R b 18 21 24 25 26 R c 18 21 24 25

Finite-State Machines (FSMs) and Controllers
3.3 Finite-State Machines (FSMs) and Controllers Want sequential circuit with particular behavior over time Example: Laser timer Pushing button causes x=1 for exactly 3 clock cycles Precisely-timed laser pulse How? Let’s try three flip-flops b=1 gets stored in first D flip-flop Then 2nd flip-flop on next cycle, then 3rd flip-flop on next OR the three flip-flop outputs, so x should be 1 for three cycles Controller x b clk laser patient 1 a 1 Bad job – what if button pressed a second time during those 3 cycles? a

Need a Better Way to Design Sequential Circuits
Also bad because of ad hoc design process How create other sequential circuits? Need A way to capture desired sequential behavior A way to convert such behavior to a sequential circuit Like we had for designing combinational circuits

Capturing Sequential Circuit Behavior as FSM
Outputs : x Hi Lo x=0 x=1 clk ^ Finite-State Machine (FSM) Describes desired behavior of sequential circuit Akin to Boolean equations for combinational behavior List states, and transitions among states Example: Toggle x every clock cycle Two states: “Lo” (x=0), and “Hi” (x=1) Transition from Lo to Hi, or Hi to Lo, on rising clock edge (clk^) Arrow points to initial state (when circuit first starts) Lo Hi Lo Hi Lo Hi Lo Hi cycle 1 cycle 2 cycle 3 cycle 4 clk Lo Hi state x Outputs : Depicting multi-bit or other info in a timing diagram a

FSM Example: Three Cycles High System
Want 0, 1, 1, 1, 0, 1, 1, 1, ... For one clock cycle each Capture as FSM Four states: 0, first 1, second 1, third 1 Transition on rising clock edge to next state Outputs : x x=0 clk ^ x=1 clk ^ x=1 clk ^ x=1 Off On1 On2 On3 clk ^ a Off On1 On2 On3 clk x State Outputs : a

Three-Cycles High System with Button Input
Four states Wait in “Off” while b is 0 (b’*clk^) When b is 1 (b*clk^), transition to On1 Sets x=1 Next two clock edges, transition to On2, then On3 So x=1 for three cycles after button pressed Inputs: b Outputs: x x=0 clk ^ Off b'*clk ^ b*clk ^ x=1 clk ^ x=1 clk ^ x=1 On1 On2 On3 Off On1 On2 On3 clk State Outputs : Inputs x b

FSM Simplification: Rising Clock Edges Implicit
ff x=1 x=0 b’ clk ^ *clk b Inputs: b; Outputs: x Every edge ANDed with rising clock edge What if we wanted a transition without a rising edge We don’t consider such asynchronous FSMs – less common, and advanced topic Only consider synchronous FSMs – rising edge on every transition On2 On1 On3 Off x=1 x=0 b ’ Inputs: b; Outputs: x a Note: Transition with no associated condition thus transistions to next state on next clock cycle

FSM Definition FSM consists of Set of states
Ex: {Off, On1, On2, On3} Set of inputs, set of outputs Ex: Inputs: {b}, Outputs: {x} Initial state Ex: “Off” Set of transitions Each with condition Describes next states Ex: Has 5 transitions Set of actions Sets outputs in each state Ex: x=0, x=1, x=1, and x=1 Inputs: b; Outputs: x On2 On1 On3 Off x=1 x=0 b ’ We often draw FSM graphically, known as state diagram Can also use table (state table), or textual languages

FSM Example: Secure Car Key
Many new car keys include tiny computer chip When key turned, car’s computer (under engine hood) requests identifier from key Key transmits identifier Else, computer doesn’t start car FSM Wait until computer requests ID (a=1) Transmit ID (in this case, ) K1 K2 K3 K4 r=1 r=0 Wait Inputs: a; Outputs: r a ’

FSM Example: Secure Car Key (cont.)
Nice feature of FSM Can evaluate output behavior for different input sequence Timing diagrams show states and output values for different input waveforms K1 K2 K3 K4 r=1 r=0 W ait I nputs: a ; O utputs: r ’ Q: Determine states and r value for given input waveform: W ait K1 K2 K3 K4 clk I nputs O utputs S t a e r clk I nputs a W ait K1 K2 K3 K4 Output State r a

Ex: Earlier Flight-Attendant Call Button
Previously built using SR latch, then D flip-flop Capture desired bit storage behavior using FSM instead Clear and precise description of desired behavior We’ll later convert to a circuit Bit Storage Blue light Call button Cancel

How To Capture Desired Behavior as FSM
List states Give meaningful names, show initial state Optionally add some transitions if they help Create transitions For each state, define all possible transitions leaving that state. Refine the FSM Execute the FSM mentally and make any needed improvements.

FSM Capture Example: Code Detector
Unlock door (u=1) only when buttons pressed in sequence: start, then red, blue, green, red Input from each button: s, r, g, b Also, output a indicates that some colored button pressed Capture as FSM List states Some transitions included s 1 Start u r Door Red Code g lock Green detector b Blue a a W ait s' u=0 s f or sta r t b utton Inputs: s , r ,g, b ,a Outputs: u Sta r t u=0 W ait f or first colored b utton a ar ab ag Red1 u=0 Blue u=0 Green u=0 ar Red2 u=1

Capture as FSM List states Create transitions s Start u r Door Red Code g lock a Green detector b Blue a Inputs: s , r ,g, b ,a Outputs: u W ait a u=0 s s' ar' Sta r t a' u=0 ar ab ag ar Red1 Blue Green Red2 u=0 u=0 u=0 u=1

Capture as FSM List states Create transitions Repeat for remaining states Refine FSM Mentally execute Works for normal sequence Check unusual cases All colored buttons pressed Door opens! Change conditions: other buttons NOT pressed also s Start u r Door Red Code g lock a Green detector b Blue a Inputs: s , r ,g, b ,a Outputs: u W ait u=0 s s' ar' ab' ag' ar' Sta r t a' u=0 ar ab ag ar Red1 Blue Green Red2 a' a' a' u=0 u=0 u=0 u=1

Start u r Door Red Code g lock a Green detector b Blue a

Controller Design Laser timer FSM Converting FSM to sequential circuit
3.4 Controller Design Laser timer FSM Inputs: b; Outputs: x On2 On1 On3 Off x=1 x=0 b ’ Converting FSM to sequential circuit Circuit called controller Standard controller architecture State register stores encoding of current state e.g., Off:00, On1:01, On2:10, On3:11 Combinational logic computes outputs and next state from inputs and current state Rising clock edge takes controller to next state Controller for laser timer FSM General form a

Controller Design Process
Step Description Step 1: Capture behavior Capture the FSM Create an FSM that describes the desired behavior of the controller. Use state register of appropriate width and combinational logic. The logic’s inputs are the state register bits and the FSM inputs; outputs are next state bits and the FSM outputs. 2A: Set up architecture Assign unique binary number (encoding) to each state. Usually use fewest bits, assign encoding to each state by counting up in binary. 2B: Encode the states Step 2: Convert to circuit Translate FSM to truth table for combinational logic such that the logic will generate the outputs and next state signals for the given FSM. Ordering the inputs with state bits first makes the correspondence between the table and the FSM clear. 2C: Fill in the truth table 2D: Implement combinational logic Implement the combinational logic using any method.

Controller Design: Laser Timer Example
Step 1: Capture the FSM Already done Step 2A: Set up architecture 2-bit state register (for 4 states) Input b, output x Next state signals n1, n0 Step 2B: Encode the states Any encoding with each state unique will work Inputs: b; Outputs: x x=0 00 b ’ O ff a b x=1 x=1 x=1 01 On1 10 On2 11 On3 Combinational logic State register s1 s0 n1 n0 x b clk FSM inputs outputs a

Controller Design: Laser Timer Example (cont)
Step 2C: Fill in truth table Inputs: b; Outputs: x x=0 00 b ’ O ff a b x=1 x=1 x=1 01 On1 10 On2 11 On3

Step 2D: Implement combinational logic a x = s1 + s0 (note that x=1 if s1=1 or s0=1) n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b n1 = s1’s0 + s1s0’ n0 = s1’s0’b + s1s0’b’ + s1s0’b n0 = s1’s0’b + s1s0’

Step 2D: Implement combinational logic (cont) s0 s1 clk Combinational Logic State register b x n0 n1 a x = s1 + s0 n1 = s1’s0 + s1s0’ n0 = s1’s0’b + s1s0’

Understanding the Controller’s Behavior
x=0 x=0 s0 s1 b x n1 n0 x=1 x=0 ’ 01 00 10 11 On2 On1 O ff On3 1 clk st a t e=01 00 00 s0 s1 b x n1 n0 x=1 ’ 01 10 11 On2 On1 O ff On3 clk b ’ O ff b b 1 x=1 x=1 x=1 01 On1 10 On2 11 On3 b x n1 1 a n0 s1 s0 clk 1 clk st a t e=00 st a t e=00 I nputs: b O utputs: x

Controller Example: Button Press Synchronizer
bi bo Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button was actually pressed We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller

Controller Example: Button Press Synchronizer (cont)
Step 2A: Set up architecture Combinational logic n0 s1 s0 n1 bo bi clk State register FSM inputs outputs Step 1: Capture FSM A B C bo=1 bo=0 bi b i ’ FSM inputs: bi; FSM outputs: bo Step 2D: Implement combinational logic clk State register bo bi s1 s0 n1 n0 Combinational logic n1 = s1’s0bi + s1s0bi n0 = s1’s0’bi bo = s1’s0bi’ + s1’s0bi = s1s0 a Step 2C: Fill in truth table Step 2B: Encode states 00 01 10 bo=1 bo=0 bi ’ FSM inputs: bi; FSM outputs: bo

Controller Example: Sequence Generator
Want generate sequence 0001, 0011, 1100, 1000, (repeat) Each value for one clock cycle Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” Step 2A: Set up architecture Combinational logic n0 s1 s0 n1 clk State register w x y z Step 1: Create FSM A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 2B: Encode states 00 01 10 11 clk State register w x y z n0 s0 s1 n1 Step 2C: Fill in truth table w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 2D: Implement combinational logic

Controller Example: Secure Car Key
(from earlier example) K1 K2 K3 K4 r=1 r=0 Wait Inputs: a; Outputs: r a ’ Step 1 Step 2C a Combinational logic s2 s1 s0 n2 r a n1 n0 clk State register Step 2A a ’ r=0 r=1 000 001 010 011 100 I nputs: ; O utputs: r Step 2B We’ll omit Step 2D

Converting a Circuit to FSM (Reverse Engineering)
2D: Circuit to eqns y=s1’ z = s1s0’ n1=(s1 xor s0)x n0=(s1’*s0’)x 2C: Truth table Step 1: FSM (get from table) What does this circuit do? a states 2B: (Un)encode states Pick any state names you want clk State register y z n0 n1 s0 s1 x states with outputs states with outputs and transitions Work backwards 2A: Set up arch – already done

Reverse Engin. the D-flip-flop Flight Atten. Call Button
2C: Truth table L 2B: (Un)encode states 2D: Circuit to eqns L = Q D = Cncl'Q + Call (next state) Don’t let the way the circuit is drawn confuse you; the combinational logic is everything outside the register 2A: Set up arch (nothing to do) Inputs : Call, Cncl Outputs L LightOn LightOff L=0 L=1 Call'*Cncl Call Call' Cncl'+Call Step 1: FSM (get from table)

Common Mistakes when Capturing FSMs
Non-exclusive transitions Incomplete transitions a

Verifying Correct Transition Properties
Can verify using Boolean algebra Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0  proves pair can never simultaneously be true One condition true: OR of all conditions of transitions leaving a state) should equal 1  proves at least one condition must be true Example a * a’b = (a * a’) * b = 0 * b = 0 OK! Answer: a a + a’b = a*(1+b) + a’b = a + ab + a’b = a + (a+a’)b = a + b Fails! Might not be 1 (i.e., a=0, b=0) Q: For shown transitions, prove whether: * Only one condition true (AND of each pair is always 0) * One condition true (OR of all transitions is always 1)

Mathematical Formalisms
Two formalisms to capture behavior thus far Boolean equations for combinational circuit design FSMs for sequential circuit design Not necessary But tremendously beneficial Structured methodology Correct circuits Automated design, automated verification, many more advantages

More on Flip-Flops and Controllers
3.5 More on Flip-Flops and Controllers Non-ideal flip-flop behavior Can’t change flip-flop input too close to clock edge Setup time: time D must be stable before edge Else, stable value not present at internal latch Hold time: time D must be held stable after edge Else, new value doesn’t have time to loop around and stabilize in internal latch clk D setup time clk Setup time violation D D latch C D S D 1 hold time Q S C 2 u 3 4 Q R u R 7 Q Leads to oscillation! Q 5 6

Initial State of a Controller
All our FSMs had initial state But our sequential circuits did not Can accomplish using flip-flops with reset/set inputs Shown circuit initializes flip-flops to 01 Designer must ensure reset-controller input is 1 during power up of circuit By electronic circuit design Inputs: x; Outputs: b x=0 Off b ’ b x=1 x=1 x=1 On1 On2 On3 b x Combinational logic n1 n0 s1 s0 State register clk D Q ’ D Q ’ Controller with reset to initial state 01 (assuming state Off was encoded as 01). Q Q R S reset controller

Glitching Glitch: Temporary values on outputs that appear soon after input changes, before stable new output values Designer must determine whether glitching outputs may pose a problem If so, may consider adding flip-flops to outputs Delays output by one clock cycle, but may be OK Called registered output Combinational logic State register s1 s0 n1 n0 x b D flip-flop xr Laser timer controller with flip-flop to prevent glitches on x from unintentionally turning on laser

Product Profile: Pacemaker

Inputs : s , z Osc Outputs : t, p r a la t=1 , p=0 s s z Controller r v lv ResetTimer p W ait t z s z s Timer t=0 (counts d o wn p=0 P ace p=1 from 0.8s) t=0 Basic pacemaker

ight at r ium Inputs : sa, za, s v , zv Osc Outputs : pa, ta, p v , tv left at r ium ta=1 sa sa *za ResetTimerA pa Controller sv W aitA sa *za pv pa=1 ta za tv zv sv P aceV r ight left P aceA sa v ent r icle v ent r icle pv=1 sv *zv W aitV tv=1 TimerA TimerV ResetTimerV sv *zv Atrioventricular pacemaker

Chapter Summary Sequential circuits
Have state Created robust bit-storage device: D flip-flop Put several together to build register, which we used to store state Defined FSM model to capture sequential behavior Using mathematical models – Boolean equations for combinational circuit, and FSMs for sequential circuits – is important Defined Capture/Convert process for sequential circuit design Converted FSM to standard controller architecture So now we know how to build the class of sequential circuits known as controllers

Chapter 4: Datapath Components
Digital Design Chapter 4: Datapath Components Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. Copyright © 2010 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

4.1 Introduction Chpts 2 & 3: Introduced increasingly complex digital building blocks Gates, multiplexors, decoders, basic registers, and controllers Controllers good for systems with control inputs/outputs Control input: Single bit (or a few), representing environment event or state Ex: 1 bit representing button pressed Data input: Multiple bits representing single entity Ex: 7 bits representing temperature in binary Need appropiate building blocks for data Datapath components (register-transfer-level, or RTL) components: store/transform data Combine datapath components to form a datapath Chpt 4 introduces some datapath components and simple datapaths Next chapter will combine controllers and datapaths into “processors” Appropriate building blocks: Tires, seat, pedals Not: Rubber, glue, metal Note: Slides with animation are denoted with a small red "a" near the animated items

Registers load Basic register loads on every clock cycle
4.2 Registers N-bit register: Stores N bits, N is the width Common widths: 8, 16, 32 Storing data into register: Loading Opposite of storing: Reading (does not alter contents) Basic register of Ch 3: Loaded every cycle Useful for implementing FSM—stores encoded state Combinational logic State register s1 s0 n1 n0 x b clk a load How extend to only load on certain cycles? D Q I 2 3 Q2 Q3 Q1 Q0 1 clk 4-bit register Basic register loads on every clock cycle

Register with Parallel Load
Add 2x1 mux to front of each flip-flop Register’s load input selects mux input to pass load=0: existing flip-flop value; load=1: new input value I 3 I 2 I 1 I 1 2x1 load load I 3 2 1 Q3 Q2 Q1 Q0 block symbol a D D D D Q Q Q Q Q3 Q2 Q1 Q0 1 D Q Q3 I 3 Q2 2 Q1 Q0 load=0 1 D Q Q3 I 3 Q2 2 Q1 Q0 load=1 a

Register Example using the Load Input: Weight Sampler
Scale has two displays Present weight Saved weight Useful to compare present item with previous item Use 4-bit parallel load register to store weight Pressing button loads present weight into register Register contents always displayed as “Saved weight,” even when new present weight appears Scale Weight Sampler 1 1 1 Save b I 3 I 2 I 1 I a 2 pounds 3 pounds load 1 Present weight clk Q3 Q2 Q1 Q0 3 pounds Saved weight

Buses N-bit bus: N wires to carry N-bit data item
Circuit drawings can become cluttered Convention for drawing buses Single bold line and/or small angled line across Scale Saved weight Weight Sampler Present weight clk b Save I 3 2 1 Q3 Q2 Q1 Q0 load 8 a

Register Example: Above-Mirror Display
C Loaded on clock edge 8 d0 load r eg0 T i0 2x4 8 1 1 8-bit Ch2 ex: Four simultaneous values from car’s computer To reduce wires: Computer writes only 1 value at a time, loads into one of four registers Was: = 32 wires Now: = 11 wires d1 load r eg1 A a0 4 × 1 i0 i1 i1 8 a1 d D d2 load r eg2 I 8 i2 8 d3 load r eg3 M e 1 load i3 s1 s0 8 x y

Register Example: Computerized Checkerboard
Each register holds values for one column of LEDs “1” lights LED Microprocessor loads one register at a time Occurs fast enough that user sees entire board change at once LED lit LED 1 1 1 R7 R6 R5 R4 R3 R2 R1 R0 Q R0 I load d7 d6 d5 d4 d3 d2 d1 d0 8 e i2 i1 i0 3x8 decoder from from microprocessor decoder D microprocessor ( a ) ( b )

Register Example: Computerized Checkerboard
LED lit LED a R7 R6 R5 R4 R3 R2 R1 R0 D i2,i1,i0 000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7) e clk

Shift Register Shift right
Register contents Shift right Move each bit one position right Rightmost bit is “dropped” Assume 0 shifted into leftmost bit before shift right Register contents after shift right a Q: Do four right shifts on 1001, showing value after each shift A: 1001 (original) a 0100 shr_in Implementation: Connect flip-flop output to next flip-flop’s input 0010 0001 a 0000

Shift Register To allow register to either shift or retain, use 2x1 muxes shr: “0” means retain, “1” shift shr_in: value to shift in May be 0, or 1 shr_in shr 1 1 1 1 1 1 1 1 shr=1 2x1 2x1 D D D D D D D D Q Q Q Q Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 ( b ) ( a ) shr_in shr Left-shift register also easy to design Q3 Q2 Q1 Q0 ( c )

Rotate Register Register contents before shift right after shift right Rotate right: Like shift right, but leftmost bit comes from rightmost bit

Shift Register Example: Above-Mirror Display
Earlier example: = 11wires from car’s computer to above-mirror display’s four registers Better than 32 wires, but 11 still a lot—want fewer for smaller wire bundles Use shift registers Wires: 1+2+1=4 Computer sends one value at a time, one bit per clock cycle 11 wires Note: this line is 1 wire, rather than 8 like before x y c shr_in d0 shr r eg0 T s1 s0 i0 2x4 8 shr_in 4 × 1 d1 shr r eg1 A a0 i0 i1 a1 i1 8 shr_in d D d2 shr r eg2 I 8 i2 8 shr_in d3 shr e r eg3 M shi f t i3 8

Multifunction Registers
Many registers have multiple functions Load, shift, clear (load all 0s) And retain present value, of course Easily designed using muxes Just connect each mux input to achieve desired function Functions: s1 s0 Operation Maintain present value 1 Parallel load 1 Shift right 1 1 (Clear - load all 0s) shr_in I3 I2 I1 I0 s1 3 2 1 3 2 1 3 2 1 3 2 1 4x1 I 3 I 2 I 1 I s0 shr_in s1 D D D D s0 Q3 Q2 Q1 Q0 Q Q Q Q ( b ) Q3 Q2 Q1 Q0 ( a )

Multifunction Registers
Operation Maintain present value 1 Parallel load 1 Shift right 1 1 Shift left I 3 I 2 I 1 I shr_in shl_in 3 2 1 3 2 1 3 2 1 3 2 1 I 3 I 2 I 1 I shl_in shr_in D D D D s1 s0 Q3 Q2 Q1 Q0 Q Q Q Q Q3 Q2 Q1 Q0 ( a ) ( b )

Multifunction Registers with Separate Control Inputs
Operation Maintain present value Parallel load Shift right Shift left s0 1 s1 Maintain present value Shift left Shift right Shift right – shr has priority over shl Parallel load Parallel load – ld has priority Operation shl shr ld 1 Q2 Q1 Q0 Q3 I 2 1 3 s1 shr_in shr shl ld s0 shl_in c ombi- n a tional ci r cuit ? Maintain value Shift left Shift right Parallel load Note Operation s0 s1 1 Outputs Inputs ld shr shl Truth table for combinational circuit s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl s0 = ld’*shr’*shl + ld a a a

Register Operation Table
Register operations typically shown using compact version of table X means same operation whether value is 0 or 1 One X expands to two rows Two Xs expand to four rows Put highest priority control input on left to make reduced table simple Inputs Outputs No t e ld shr shl s1 s0 Operation ld shr shl Ope r a tion Maintain value M ai n tain v alue 1 1 1 Shift left 1 Shi f t le f t Shift right 1 Shift right X 1 Parallel load X 1 Parallel load 1

Register Design Process
Can design register with desired operations using simple four-step process

Register Design Example
Operation Maintain present value Parallel load Shift left Synchronous clear Synchronous set s0 1 s1 s2 Desired register operations Load, shift left, synchronous clear, synchronous set Want unique control input for each operation Step 1: Determine mux size 5 operations: above, plus maintain present value (don’t forget this one!)  Use 8x1 mux D Q Qn 7 6 3 2 1 In 5 4 s2 s1 s0 from Qn-1 a Step 2: Create mux operation table Step 3: Connect mux inputs Step 4: Map control lines Operation Maintain present value Shift left Parallel load Set to all 1s Clear to all 0s s0 1 s1 s2 shl X ld clr Inputs Outputs set s2 = clr’*set s1 = clr’*set’*ld’*shl + clr s0 = clr’*set’*ld + clr a

Register Design Example
3 I 2 I 1 I shl I 3 I 2 I 1 I s2 s1 shl_in ld combi- shl_in s0 national set circuit Q3 Q2 Q1 Q0 clr Q3 Q2 Q1 Q0 Step 4: Map control lines Operation Maintain present value Shift left Parallel load Set to all 1s Clear to all 0s s0 1 s1 s2 shl X ld clr Inputs Outputs set s2 = clr’*set s1 = clr’*set’*ld’*shl + clr s0 = clr’*set’*ld + clr

Adders Adds two N-bit binary numbers
4.3 Adders Adds two N-bit binary numbers 2-bit adder: adds two 2-bit numbers, outputs 3-bit result e.g., = (1 + 3 = 4) Can design using combinational design process of Ch 2, but doesn’t work well for typical N Why not? Inputs Outputs a1 a0 b1 b0 c s1 s0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Why Adders Aren’t Built Using Standard Combinational Design Process
4.3 Why Adders Aren’t Built Using Standard Combinational Design Process Truth table too big 2-bit adder’s truth table shown Has 2(2+2) = 16 rows 8-bit adder: 2(8+8) = 65,536 rows 16-bit adder: 2(16+16) = ~4 billion rows 32-bit adder: ... Big truth table with numerous 1s/0s yields big logic Plot shows number of transistors for N-bit adders, using state-of-the-art automated combinational design tool 1 s0 s1 c b0 b1 a1 Inputs Outputs a0 10000 8000 6000 4000 2000 1 2 3 4 5 N 6 7 8 Q: Predict number of transistors for 16-bit adder A: 1000 transistors for N=5, doubles for each increase of N. So transistors = 1000*2(N-5). Thus, for N=16, transistors = 1000*2(16-5) = 1000*2048 = 2,048, Way too many! Transistors a Size comes from implementing with two levels of gates. Following approach uses more levels to achieve smaller size. a

Alternative Method to Design an Adder: Imitate Adding by Hand
Alternative adder design: mimic how people do addition by hand One column at a time Compute sum, add carry to next column 1 1 1 A: 1 B: a

Alternative Method to Design an Adder: Imitate Adding by Hand
Create component for each column Adds that column’s bits, generates sum and carry bits 1 1 A: B: a 1 b c o s a ci A: B: + 1 SUM Half-adder Full-adders

Half-Adder Half-adder: Adds 2 bits, generates sum and carry
o s a ci A: B: + 1 SUM Half-adder: Adds 2 bits, generates sum and carry Design using combinational design process from Ch 2 s 1 c o b a I nputs O utputs Step 1: Capture the function co = ab s = a’b + ab’ (same as s = a xor b) Step 2A: Create equations a b co s ( ) Half-adder (HA) a Step 2B: Implement as circuit

Full-Adder Full-adder: Adds 3 bits, generates sum and carry
o s a ci A: B: + 1 SUM Full-adder: Adds 3 bits, generates sum and carry Design using combinational design process from Ch 2 Step 1: Capture the function s 1 c o ci b a I nputs O utputs Step 2B: Implement as circuit c o ci b a s Full adder (FA) Step 2A: Create equations co = a’bc + ab’c + abc’ + abc co = a’bc +abc +ab’c +abc +abc’ +abc co = (a’+a)bc + (b’+b)ac + (c’+c)ab co = bc + ac + ab s = a’b’c + a’bc’ + ab’c’ + abc s = a’(b’c + bc’) + a(b’c’ + bc) s = a’(b xor c)’ + a(b xor c) s = a xor b xor c

Carry-Ripple Adder Using half-adder and full-adders, we can build adder that adds like we would by hand Called a carry-ripple adder 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output 5-bit output can be considered 4-bit “sum” plus 1-bit “carry out” Can easily build any size adder a3 c o s F A b3 a2 b2 s3 s2 s1 ci b a a1 b1 s0 a0 b0 HA ( ) a3 a2 a1 a0 b3 s3 s2 s1 s0 c o b2 b1 b0 ( b ) 4-bit adder

Carry-Ripple Adder Using full-adder instead of half-adder for first bit, we can include a “carry in” bit in the addition Useful later when we connect smaller adders to form bigger adders a3 b3 a2 b2 a1 b1 a0 b0 ci a b ci a b ci a b ci a b ci a3 a2 a1 a0 b3 b2 b1 b0 F A F A F A F A 4-bit adder ci c o s c o s c o s c o s c o s3 s2 s1 s0 c o s3 s2 s1 s0 ( a ) ( b )

Carry-Ripple Adder’s Behavior
c o s F A ci b a Assume all inputs initially 0 1 1 (answer should be 01000) c o s F A o2 o1 o0 ci b a 1 a O utput a f t er 2 ns (1 F A del a y) 1 Wrong answer—is there a problem? No—just need more time for carry to ripple through the chain of full adders.

Carry-Ripple Adder’s Behavior
1 1 1 1 (answer should be 01000) 1 a b ci a b ci a b ci a b ci F A F A F A F A c o s c o s c o s c o s 1 1 c o1 1 Outputs after 4ns (2 FA delays) ( b ) c o s F A 1 o2 ci b a ( ) Outputs after 6ns (3 FA delays) 1 1 a c o s F A 1 ci b a ( d ) Output after 8ns (4 FA delays) 1 1 Correct answer appears after 4 FA delays

Cascading Adders + Block symbol Simplified block symbol a7 a6 a5 a4 b7
b7.. b0 4-bit adder ci 4-bit adder ci 8-bit adder ci + co s3 s2 s1 s0 co s3 s2 s1 s0 co s7.. s0 C co s7 s6 s5 s4 s3 s2 s1 s0 ( a ) ( b ) ( c ) Block symbol Simplified block symbol

Adder Example: DIP-Switch-Based Adding Calculator
Goal: Create calculator that adds two 8-bit binary numbers, specified using DIP switches DIP switch: Dual-inline package switch, move each switch up or down Solution: Use 8-bit adder DIP switches 1 a7..a0 b7..b0 s7..s0 8-bit carry-ripple adder c o ci a C A L C LEDs

Adder Example: DIP-Switch-Based Adding Calculator
To prevent spurious values from appearing at output, can place register at output Actually, the light flickers from spurious values would be too fast for humans to detect—but the principle of registering outputs to avoid spurious values being read by external devices (which normally aren’t humans) applies here. DIP switches 1 a7..a0 b7..b0 8-bit adder ci c o s7..s0 e ld 8-bit register clk C A L C LEDs

Adder Example: Compensating Weight Scale
Weight scale with compensation amount of 0-7 To compensate for inaccurate sensor due to physical wear Use 8-bit adder weight 7 1 Dial, can be set by user sensor 6 2 5 3 4 010 000 a7..a0 b7..b0 s7..s0 8-bit adder c o ci a 1 ld display register Weight clk Adjuster to display

Incrementer Adds 1 to input A
Could design using combinational design process, but smaller design uses carry-ripple, only need half-adders

4.4 Comparators N-bit equality comparator: Outputs 1 if two N-bit numbers are equal 4-bit equality comparator with inputs A and B a3 must equal b3, a2 = b2, a1 = b1, a0 = b0 Two bits are equal if both 1, or both 0 eq = (a3b3 + a3’b3’) * (a2b2 + a2’b2’) * (a1b1 + a1’b1’) * (a0b0 + a0’b0’) Note that function inside parentheses is XNOR eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0) 0110 = 0111 ? a3 b3 a2 b2 a1 b1 a0 b0 eq 1 1 a3 a2 a1 a0 b3 eq b2 b1 b0 4-bit equality comparator = 1 1 1 a a

Magnitude Comparator N-bit magnitude comparator: Two N-bit inputs A and B, outputs whether A>B, A=B, or A<B, for How design? Consider comparing by hand. First compare a3 and b3. If equal, compare a2 and b2. And so on. Stop if comparison not equal (the two bits are 0 and 1, or 1 and 0)—whichever of A or B has the 1 is thus greater. If never see unequal bit pair, then A=B. A=1011 B=1001 1011 1001 Equal 1011 1001 Equal a 1011 1001 Not equal So A > B

Magnitude Comparator > = <
By-hand example leads to idea for design Start at left, compare each bit pair, pass results to the right Each bit pair called a stage Each stage has 3 inputs taking results of higher stage, outputs new results to lower stage in_gt in_eq in_lt out_gt out_eq out_lt Igt Ieq Ilt Stage 3 a3 b3 a b in_gt in_eq in_lt out_gt out_eq out_lt Stage 2 a2 b2 a b in_gt in_eq in_lt out_gt out_eq out_lt Stage 1 a1 b1 a b in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage 0 a0 b0 a b How design each stage? a Igt Ieq Ilt a3 a2 a1 a0 b3 b2 b1 b0 AgtB AeqB AltB 1 4-bit magnitude comparator > = < a

Magnitude Comparator Each stage: out_gt = in_gt + (in_eq * a * b’)
in_lt out_gt out_eq out_lt Igt Ieq Ilt Stage 3 a3 b3 a b Stage 2 a2 b2 Stage 1 a1 b1 AgtB AeqB AltB Stage 0 a0 b0 Each stage: out_gt = in_gt + (in_eq * a * b’) A>B if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0 out_lt = in_lt + (in_eq * a’ * b) A<B if already determined in higher stage, or if higher stages equal but in this stage a=0 and b=1 out_eq = in_eq * (a XNOR b) A=B (so far) if already determined in higher stage and in this stage a=b too Simple circuit inside each stage, just a few gates (not shown) a

Magnitude Comparator How does it work? 1011 = 1001 ?
1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 1 a b a b a b a b 1 Ieq=1 causes this stage to compare Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB I lt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( a ) a 1 1 = 1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 1 a b a b a b a b 1 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB I lt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( b )

Magnitude Comparator 1011 = 1001 ? Final answer appears on the right
1 > 1 1 Final answer appears on the right Takes time for answer to “ripple” from left to right Thus called “carry-ripple style” after the carry-ripple adder Even though there’s no “carry” involved a3 b3 a2 b2 a1 b1 a0 b0 1 a b a b a b a b Igt in_gt out_gt in_gt out_gt 1 in_gt out_gt in_gt out_gt A gtB 1 Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB I lt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( c ) a 1 1 1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 1 a b a b a b a b 1 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB I lt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( d )

Magnitude Comparator Example: Minimum of Two Numbers
Design a combinational component that computes the minimum of two 8-bit numbers Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux If A<B, pass A through mux. Else, pass B. MIN Igt Ieq Ilt AgtB AeqB AltB 1 A B 8-bit magnitude comparator s I 2x1 mux 8-bit C 8 M in ( a ) b a 1

Multiplier – Array Style
4.5 Multiplier – Array Style Can build multiplier that mimics multiplication by hand Notice that multiplying multiplicand by 1 is same as ANDing with 1

Generalized representation of multiplication by hand

Multiplier design – array of AND gates + (5-bit) + (6-bit) + (7-bit) a0 a1 a2 a3 b0 b1 b2 b3 p7..p0 pp1 pp2 A B P * Block symbol pp3 pp4

Subtractors and Signed Numbers
4.6 Subtractors and Signed Numbers Can build subtractor as we built carry-ripple adder Mimic subtraction by hand Compute the borrows from columns on left Use full-subtractor component: wi is borrow by column on right, wo borrow from column on left 1st column 2nd c olumn 3 r d c olumn 4th c olumn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a - 1 1 1 - 1 1 1 - 1 1 1 - 1 1 1 1 1 1 1 1 1 1 w o a3 a b FS wi s b3 s3 a2 b2 s2 a1 b1 s1 a0 b0 s0 ( ) a3 a2 a1 a0 b3 s3 s2 s1 s0 w o wi b2 b1 b0 ( c ) 4-bit subtractor a

Subtractor Example: DIP-Switch Based Adding/Subtracting Calculator
Extend earlier calculator example Switch f indicates whether want to add (f=0) or subtract (f=1) Use subtractor and 2x1 mux DIP switches 1 8-bit register CALC LEDs e f clk ld 8 2 x wi ci A B S co wo 8-bit adder 8-bit subtractor

Subtractor Example: Color Space Converter – RGB to CMYK
Often represented as weights of three colors: red, green, and blue (RGB) Perhaps 8 bits each (0-255), so specific color is 24 bits White: R= (255), G= , B= Black: R= , G= , B= Other colors: values in between, e.g., R= , G= , B= would be a reddish purple Good for computer monitors, which mix red, green, and blue lights to form colors Printers use opposite color scheme Because inks absorb light Use complementary colors of RGB: Cyan (absorbs red), reflects green and blue, Magenta (absorbs green), and Yellow (absorbs blue)

Printers must quickly convert RGB to CMY C=255-R, M=255-G, Y=255-B Use subtractors as shown R G B 255 255 255 8 8 8 8 8 8 — — — 8 8 8 C M Y

Try to save colored inks Expensive Imperfect – mixing C, M, Y doesn’t yield good-looking black Solution: Factor out the black or gray from the color, print that part using black ink e.g., CMY of (250,200,200)= (200,200,200) + (50,0,0). (200,200,200) is a dark gray – use black ink

Call black part K (200,200,200): K=200 (Letter “B” already used for blue) Compute minimum of C, M, Y values Use MIN component designed earlier, using comparator and mux, to compute K Output resulting K value, and subtract K value from C, M, and Y values Ex: Input of (250,200,200) yields output of (50,0,0,200) R G B 8 8 8 R G B RGB to CMY C M Y 8 8 8 8 C M Y MIN 8 MIN 8 K — — — 8 8 8 8 C2 M2 Y2 K

Representing Negative Numbers: Two’s Complement
Negative numbers common How represent in binary? Signed-magnitude Use leftmost bit for sign bit So -5 would be: 1101 using four bits using eight bits Better way: Two’s complement Big advantage: Allows us to perform subtraction using addition Thus, only need adder component, no need for separate subtractor component

Ten’s Complement 9 8 7 6 5 4 3 2 1 Before introducing two’s complement, let’s consider ten’s complement But, be aware that computers DO NOT USE TEN’S COMPLEMENT. Introduced for intuition only. Complements for each base ten number shown to right. Complement is the number that when added results in 10

Ten’s Complement Nice feature of ten’s complement
Instead of subtracting a number, adding its complement results in answer exactly 10 too much So just drop the 1 – results in subtracting using addition only complements 1 9 10 2 8 4 6 3 7 7 4 6 –4 +6 10 20 5 5 3 13 a 6 4 13 7 3 3 8 2 7–4=3 7+6=13 3 9 1 Adding the complement results in an answer that is exactly 10 too much – dropping the tens column gives 10 the right answer.

Two’s Complement is Easy to Compute: Just Invert Bits and Add 1
Hold on! Sure, adding the ten’s complement achieves subtraction using addition only But don’t we have to perform subtraction to have determined the complement in the first place? E.g., we only know that the complement of 4 is 6 by subtracting 10-4=6 in the first place. True. But in binary, it turns out that the two’s complement can be computed easily Two’s complement of 011 is 101, because is 1000 Could compute complement of 011 as 1000 – 011 = 101 Easier method: Just invert all the bits, and add 1 The complement of 011 is = 101. It works! Q: What is the two’s complement of 0101? A: =1011 (check: =10000) a Q: What is the two’s complement of 0011? A: =1101

Two’s Complement Two’s complement can represent negative numbers
Suppose have 4 bits Positive numbers 0 to 7: 0000 to 0111 Negative numbers -1: Take two’s complement of 1:  = 1111 -2:  = … -8:  = 1000 So -1 to -8: 1111 to 1000 Leftmost bit indicates sign of number, known as sign bit. 1 means negative. Signed vs. unsigned N-bit number Unsigned: 0 to 2N-1 Ex. Unsigned 8-bit: 0 to 255 Signed (two’s complement): -2N-1 to 2N-1-1 Ex. Signed 8-bit: -128 to 127 Quick method to determine magnitude of negative number— 4-bit: subtract right 3 bits from 8. Ex. 1110: -(8 – 6) = -2 Or just take two’s complement again: 1110  -(0001+1) = = -2

Two’s Complement Subtractor Built with an Adder
Using two’s complement A – B = A + (-B) = A + (two’s complement of B) = A + invert_bits(B) + 1 So build subtractor using adder by inverting B’s bits, and setting carry in to 1 1 cin B A Adder S N-bit

Adder/Subtractor Adder/subtractor: control input determines whether add or subtract Can use 2x1 mux – sub input passes either B or inverted B Alternatively, can use XOR gates – if sub input is 0, B’s bits pass through; if sub input is 1, XOR inverts B’s bits b7 b6 sub adder s B inputs 1 N-bit 2x1 N-bit A S B Adder cin

Adder/Subtractor Example: Calculator
DIP switches 1 8-bit register 8-bit adder/subtractor sub C A L LEDs e S B f clk ld 8 Previous calculator used separate adder and subtractor Improve by using adder/subtractor, and two’s complement numbers DIP swi t ches 1 8-bit r e g is er C A L LEDs f clk ld 8 2 x wi ci B S c o w 8-bit adder 8-bit subt a or

Overflow Sometimes result can’t be represented with given number of bits Either too large magnitude of positive or negative Ex. 4-bit two’s complement addition of (7+1=8). But 4-bit two’s complement can’t represent number >7 = WRONG answer, 1000 in two’s complement is -8, not +8 Adder/subtractor should indicate when overflow has occurred, so result can be discarded

Detecting Overflow: Method 1
For two’s complement numbers, overflow occurs when the two numbers’ sign bits are the same but differ from the result’s sign bit If the two numbers’ sign bits are initially different, overflow is impossible Adding positive and negative can’t exceed largest magnitude positive or negative Simple overflow detection circuit for 4-bit adder overflow = a3’b3’s3 + a3b3s3’ Include “overflow” output bit on adder/subtractor 1 + sign bits overflow ( a ) b no overflow c If the numbers’ sign bits have the same value, which differs from the result’s sign bit, overflow has occurred.

Detecting Overflow: Method 2
Even simpler method: Detect difference between carry-in to sign bit and carry-out from sign bit Yields simpler circuit: overflow = c3 xor c4 1 + overflow ( a ) b no overflow c If the carry into the sign bit column differs from the carry out of that column, overflow has occurred.

Arithmetic-Logic Unit: ALU
4.7 Arithmetic-Logic Unit: ALU ALU: Component that can perform various arithmetic (add, subtract, increment, etc.) and logic (AND, OR, etc.) operations, based on control inputs

Multifunction Calculator without an ALU
Can build using separate components for each operation, and muxes Too many wires, also wastes power computing operations when only use one result at given time DIP switches 1 8 8 A B Wasted + — +1 AND OR X OR N O T power 8 8 8 8 8 8 8 8 1 A lot of wires 1 2 3 4 5 6 7 x s2 y 8-bit 8x1 s1 z s0 8 e Id 8-bit r e g is t er clk C A L C 8 LEDs

ALU More efficient design uses ALU
ALU design not just separate components multiplexed (same problem as previous slide) Instead, ALU design uses single adder, plus logic in front of adder’s A and B inputs Logic in front is called an arithmetic-logic extender Extender modifies A and B inputs so desired operation appears at output of the adder A B abext cinext AL-extender ia7 ib7 a7 b7 ia6 ib6 a6 b6 ia0 ib0 a0 b0 cin ( b ) x y z x y z AL-extender I A I B Adder cin a I S ALU S ( a )

Arithmetic-Logic Extender in Front of ALU
xyz=000 Want S=A+B : just pass a to ia, b to ib, and set cin=0 xyz=001 Want S=A-B : pass a to ia, b’ to ib and set cin=1 (two’s complement) xyz=010 Want S=A+1 : pass a to ia, set ib=0, and set cin=1 xyz=011 Want S=A : pass a to ia, set ib=0, and set cin=0 xyz=100 Want S=A AND B : set ia=a*b, b=0, and cin=0 Others: likewise Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and create logic for cin(x,y,z), to complete design of the AL-extender component

ALU Example: Multifunction Calculator
DIP swi t ches 1 8-bit r e g is er 8-bit 8 × C A L LEDs z y x clk Id s0 s1 s2 2 3 4 5 6 7 N O T X OR AND +1 Ð + 8 B A lot of wi s . W as ed p o w DIP switches 1 1 8 8 A B Design using ALU is elegant and efficient No mass of wires No big waste of power A B x x y ALU y z z S 8 e ld 8-bit register clk 8 C A L C LEDs

Shifters Shifting (e.g., left shifting 0011 yields 0110) useful for:
4.8 Shifters Shifting (e.g., left shifting 0011 yields 0110) useful for: Manipulating bits Converting serial data to parallel (remember earlier above-mirror display example with shift registers) Multiply/divide by 2 (unsigned numbers only) Shift left once is same as multiplying by 2. Ex: 0011 (3) becomes 0110 (6) Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just be appending 0, i.e., by shifting left (55 becomes 550) Shift right once same as dividing by 2 inL i3 q3 q2 q1 q0 i2 i1 i0 inR 2 s0 s1 shL shR 1 Shifter with left shift, right shift, and no shift 1 in sh i3 q3 q2 q1 q0 i2 i1 i0 Shifter with left shift or no shift i2 q3 q2 q1 q0 in i3 i1 i0 Left shifter <<1 Symbol a

Shifter Example: Temperature Averager
Four registers storing a history of temperatures Want to output the average of those temperatures Add Use three adders Then divide by four Same as shift right by 2 (8) (12) (15) (7) T Ra Rb Rc Rd clk ld ld + a >>2 divide by 4 shift in 0 (42) (10) Note rounding Ravg ld Tavg

Strength Reduction Many multiplications not by power of 2 constants (2, 4, 8, …) E.g., by 5, or 10 Could use multiplier component, but shifters are small and fast Replace multiplication by shifts and adds Operator strength reduction (multiply is “stronger” than shift/add) E.g., 5*C  4*C + C (4*C same as C<<2) Replacing division by shifts and adds slightly harder Approximate fraction using fraction having power of 2 denominator E.g., C/5 = 0.20*C, approx. equals (102/512)*C = 0.199*C (102/512)*C = C*( )/512 = (C*64 + C*32 + C*4+C*2)/512 = ((C<<6) + (C<<5) + (C<<2) + (C<<1)) >> 9

Celsius to Fahrenheit Converter
F = C*9/5 + 32 F = C + C*4/5 + 32 F = C + 4*(C*64+C*32+C*4+C*2)/ (1/5 from prev. slide) F = C + (C*64+C*32+C*4+C*2)/128+32 >>7 C 16 F = C +(C*64+C*32+C*4+C*2)/ + <<6 <<5 <<2 <<1 a Note: Uses wider buses, padded on the left, to avoid losing bits during shifts Determine biggest possible internal values, set width accordingly Do divisions as late as possible to reduce rounding errors

Barrel Shifter A shifter that can shift by any amount
1 in sh i3 q3 q2 q1 q0 i2 i1 i0 Shift by 1 shifter uses 2x1 muxes. 8x1 mux solution for 8-bit barrel shifter: too many wires. A shifter that can shift by any amount 4-bit barrel left shift can shift left by 0, 1, 2, or 3 positions 8-bit barrel left shifter can shift left by 0, 1, 2, 3, 4, 5, 6, or 7 positions (Shifting an 8-bit number by 8 positions is pointless -- you just lose all the bits) Could design using 8x1 muxes Too many wires More elegant design Chain three shifters: 4, 2, and 1 Can achieve any shift of 0..7 by enabling the correct combination of those three shifters, i.e., shifts should sum to desired amount Q: xyz=??? to shift by 5? <<1 in sh x y z 8 Q <<2 <<4 I 1 a Net result: shift by 5:

4.9 Counters and Timers N-bit up-counter: N-bit register that can increment (add 1) to its own value on each clock cycle 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 Count “rolls over” from 1111 to 0000 Terminal (last) count, tc, equals1 during value just before rollover Internal design Register, incrementer, and N-input AND gate to detect terminal count 1 a 0000 0001 1110 0100 0001 0000 0010 0011 0101 1111 1 ... a

Counter Example: Turnstile with Display
Count people passing through a turnstile Assume turnstile generates 1-clock pulse on P Connect count to display Button can reset count Simple solution using up-counter

Up/Down-Counter Can count either up or down
Includes both incrementer and decrementer Use dir input to select, via 2x1 mux: dir=0 means up Likewise, dir selects appropriate terminal count value (all 1s or all 0s) ld 4-bit register C t c 4 n clr dir 4-bit up/down counter –1 +1 1 2 x 4-bit 2

Counter with Load Up-counter that can be loaded with external value
Designed using 2x1 mux. ld input selects incremented value or external value Load the internal register when loading external value or when counting Note that ld has priority over cnt L 4 ld 1 4-bit 2x1 4 cnt Id 4-bit register clr clr 4 4 4 +1 tc C

Counter with Parallel Load
1000 Useful to create pulses at specific multiples of clock Not just at N-bit counter’s natural wrap-around of 2N Example: Pulse every 9 clock cycles Use 4-bit down-counter with parallel load Set parallel load input to 8 (1000) Use terminal count to reload When count reaches 0, next cycle loads 8. Why load 8 and not 9? Because 0 is included in count sequence: 8, 7, 6, 5, 4, 3, 2, 1, 0  9 counts c n t ld C L 1 clk 4 4-bit down-counter

Counter Example: New Year’s Eve Countdown Display
Chapter 2 example previously used microprocessor to count from 59 down to 0 in binary Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59 Happy New 8 d0 c0 i0 Year! 59 L d1 c1 i1 1 d2 c2 i2 2 ld d3 c3 i3 3 c4 i4 Note: Use 8-bit counter, not 60-bit counter clr c5 i5 d58 c6 cnt d59 c7 d60 58 d61 clk 8-bit 59 d62 fireworks 1 Hz down- 6x64 tc d63 counter dcd

Common Counter Use: Clock Divider
Suppose have 512 Hz oscillator, but want 2 Hz pulse Thus, want divide fast clock by 256 Design using 8-bit up-counter, use tc output as pulse Counts from 0 to 255 (256 counts), so pulses tc every 256 cycles 1 cnt 8-bit up-counter tc C osc 512 MHz 8 p (unused) 2 MHz

Clock Division by Amount not Power of 2 Example: 1 Hz Pulse Generator from 60 Hz Clock
Example: U.S. electricity standard uses 60 Hz signal Device may convert that to 1 Hz signal to count seconds Use 6-bit up-counter Up counter: Detected count of 59 clears counter to 0; tc thus pulses every 60 cycles Note: Detect 59, not 60 (because the first number, 0, is included) Down counter approach also possible: When count reaches 0, load 59 C tc p 1 osc 60 Hz 1 Hz ld cnt 6-bit down-counter unused C tc p 1 osc 60 Hz 1 Hz clr cnt 6-bit up-counter

Measuring Time Between Events using an Up-Counter
Initially clear to st event: Set cnt= nd event: Set cnt=0. Then, multiply counted clock cycles by clock period to determine time Ex: Highway speed measurement system Two sensors “a” and “b” in road Use FSM to detect “a” becoming 1, set cnt=1. Set cnt=0 when “b” 1 If clock is 1 kHz (period is 1 ms), then time is C * 0.001s If a and b separated by 0.01 miles, then vehicle speed in mph is: miles / (time * (1 hour / 3600 seconds)) E.g., if C is 500, then speed is 0.01 / ((500*0.001) / 3600) = 72 mph Speed a’ b’ Measurer clr a b vehicle S0 S1 S2 cnt C clr=1 cnt=1 cnt=0 b (compute time 16 Speed s and output Measurer a speed)

Timers Pulses output at user-specified timer interval when enabled
-1 32 Pulses output at user-specified timer interval when enabled “Ticks” like a clock Interval specified as multiple of base time unit If base is 1 microsec and user wants pulse every 300 ms, loads 300,000 into timer Can design using oscillator, register, and down-counter load ld 32-bit register 1 4-bit 2x1 ld enable 32-bit cnt down-counter 1 microsec tc C oscillator Q unused (a) load enable Q 32-bit 1-microsec timer (c) 32 M (b) Q

Timer Example: Laser Surgery System
b clk laser patient Timer Example: Laser Surgery System Recall Chpt 3 laser surgery example Clock was 10 ns, wanted 30 ns, used 3 states. What if wanted 300 ms? Adding 30 million states is not reasonable. Use timer Controller FSM loads timer, enables, then waits for Q=1 (b) load enable Q 32-bit 1 microsec timer M Controller 300,000 (in binary) b x clk ld en Off On ... Strt clk State Outputs : Inputs x b ld en Q 300 ms 10 ns (d) Inputs: b, Q Outputs: ld, en, x On Off x=1 ld=0 en=1 x=0 ld=1 en=0 b' b Q' Q Strt (c)

begins to have fanout and wire problems
4.10 Register Files Accessing one of several registers is: OK if just a few registers Problematic when many Ex: Earlier above-mirror display, with 16 registers Much fanout (branching of wire): Weakens signal Many wires: Congestion C d0 d15 e i0 i15 load i3-i0 4x 16 32 4 D d s3-s0 32-bit 16x1 r eg0 eg15 9 C d0 d1 d2 d3 e i0 i1 i2 i3 a0 a1 load 2 × 4 8 D d x y s1 s0 8-bit 1 r eg0 eg1 eg2 eg3 T A I M a huge mux too much fanout 9 congestion 9 9 9 9 16*32 = 512 wires 4 32-bit registers tolerable 16 32-bit registers begins to have fanout and wire problems

Register File MxN register file: Efficient design for one-at-a-time write/read of many registers Consider bit registers 32-bit data to write 32 32 4 R_data R_addr R_en 32-bit data that is read W_data 4-bit “address” specifies which register to write 4-bit address to specifies which register to read 4 “read port” Called “write port” W_addr Enable (load) line: Reg written on next clock W_en Enable read 16 × 32 register file a

Register File 9 9 9 Internal design uses drivers and bus 9 9 1 1
32 9 9 W_data 32 bus R_data d0 load reg0 driver d0 Internal design uses drivers and bus 9 32 2x4 9 2x4 d1 load a 1 reg1 d1 9 1 i0 32 q q=d d driver Boosts signal i0 W_addr R_addr 1 i1 9 i1 1 d2 load reg2 d2 32 write read 1 decoder decoder 1 d3 load 9 reg3 d3 e 9 9 e 32 W_en R_en q c=1: q=d c c=0: q= Z d like no connection three-state driver 1 4x32 register file 1 a Internal design of 4x32 RF; 16x32 RF follows similarly Note: Each driver in figure actually represents 32 1-bit drivers

Register File Timing Diagram
Can write one register and read one register each clock cycle May be same register cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk 1 2 3 4 5 6 W_data 9 22 X X 177 555 W_addr 3 1 X X 2 3 W_en R_data Z Z Z 9 Z 22 9 555 R_addr X X 3 X 1 3 R_en 0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 32 2 W_data W_addr W_en R_data R_addr R_en 4x32 register file 1: ? 1: ? 1: 22 1: 22 1: 22 1: 22 1: 22 2: ? 2: ? 2: ? 2: ? 2: ? 2: 177 2: 177 3: ? 3: 9 3: 9 3: 9 3: 9 3: 9 3: 555

Register-File Example: Above-Mirror Display
16 32-bit registers that can be written by car’s computer, and displayed Use 16x32 register file Simple, elegant design Register file hides complexity internally And because only one register needs to be written and/or read at a time, internal design is simple C d0 d15 e i0 i15 load i3-i0 4 × 16 32 D d s3-s0 32-bit x 1 r eg0 eg15 c ongestion t oo much fanout huge mux OLD design a 32 4 1 W_data W_addr W_en R_data R_addr R_en 16x32 register file C D RA WA load

Chapter Summary Need datapath components to store and operate on multi-bit data Also known as register-transfer-level (RTL) components Components introduced Registers Adders Comparators Multipliers Subtractors Arithmetic-Logic Units Shifters Counters and Timers Register Files Next chapter combines knowledge of combinational logic design, sequential logic design, and datapath components, to build digital circuits that can perform general and powerful computations

Chapter 5: Register-Transfer Level (RTL) Design
Digital Design Chapter 5: Register-Transfer Level (RTL) Design Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. Copyright © 2010 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

Levels of digital design abstraction
5.1 Introduction Chpt 2 Capture Comb. behavior: Equations, truth tables Convert to circuit: AND + OR + NOT  Comb. logic Chpt 3 Capture sequential behavior: FSMs Convert to circuit: Register + Comb. logic  Controller Chpt 4 Datapath components, simple datapaths Chpt 5 Capture behavior: High-level state machine Convert to circuit: Controller + Datapath  Processor Known as “RTL” (register-transfer level) design Register- Higher levels t r ans f er l e v el ( R TL) Logic l e v el T r ansistor l e v el Levels of digital design abstraction Processors: Programmable (microprocessor) Custom Note: Slides with animation are denoted with a small red "a" near the animated items

High-Level State Machines (HLSMs)
5.2 High-Level State Machines (HLSMs) Some behaviors too complex for equations, truth tables, or FSMs Ex: Soda dispenser c: bit input, 1 when coin deposited a: 8-bit input having value of deposited coin s: 8-bit input having cost of a soda d: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda FSM can’t represent… 8-bit input/output Storage of current total Addition (e.g., ) a s c d Soda dispenser processor 25 1 a s c d Soda dispenser processor 25 1 50 tot: 25 tot: 50 a 1

HLSMs High-level state machine (HLSM) extends FSM with:
8 a s c d Soda dispenser processor High-level state machine (HLSM) extends FSM with: Multi-bit input/output Local storage Arithmetic operations Conventions Numbers: Single-bit: '0' (single quotes) Integer: 0 (no quotes) Multi-bit: “0000” (double quotes) == for equal, := for assignment Multi-bit outputs must be registered via local storage // precedes a comment Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '1' dispenses soda Local stor a g e : tot (8 bits) c Init W ait tot:=tot+a a d:='0' c' * ( tot<s ) tot:=0 c’*(tot<s)’ Disp SodaDispenser d:='1'

Ex: Cycles-High Counter
P = total number (in binary) of cycles that m is 1 Capture behavior as HLSM Preg required (multibit outputs must be registered) Use to hold count CountHigh m clk Preg 32 P S_Clr Preg := 0 // Clear Preg to 0s CountHigh Inputs : m (bit) Outputs P (32 bits) Local storage: Preg (a) ? S_Clr S_Wt m' m Preg := 0 // Clear Preg to 0s // Wait for m == '1' CountHigh Inputs : (bit) Outputs P (32 bits) Local storage: Preg (b) ? S_Clr S_Wt m' S_Inc m Preg := 0 Preg := Preg + 1 // Clear Preg to 0s // Wait for m == '1' // Increment Preg CountHigh Inputs : (bit) Outputs P (32 bits) Local storage: Preg (c) a Note: Could have designed directly using an up-counter. But, that methodology is ad hoc, and won't work for more complex examples, like the next one. a

Example: Laser-Based Distance Measurer
T (in seconds) laser D Object of interest a sensor 2D = T sec * 3*108 m/sec Laser-based distance measurement – pulse laser, measure time T to sense reflection Laser light travels at speed of light, 3*108 m/sec Distance is thus D = (T sec * 3*108 m/sec) / 2

T (in seconds) Laser-based distance measurer 16 from button to display S L D B to laser from sensor laser sensor Inputs/outputs B: bit input, from button, to begin measurement L: bit output, activates laser S: bit input, senses laser reflection D: 16-bit output, to display computed distance

16 from button to display S L D B to laser from sensor DistanceMeasurer Inputs : B (bit), S (bit) Outputs L (bit), D (16 bits) Local storage: Dreg(16) (required) S0 ? a (first state usually initializes the system) L := '0' // laser off Dreg := 0 // distance is 0 Declare inputs, outputs, and local storage Dreg required for multi-bit output Create initial state, name it S0 Initialize laser to off (L:='0') Initialize displayed distance to 0 (Dreg:=0) Recall: '0' means single bit, 0 means integer

16 from button to display S L D B to laser from sensor DistanceMeasurer ... S1 ? B' // button not pressed B // button pressed S0 S0 L := '0' Dreg := 0 Add another state, S1, that waits for a button press B' – stay in S1, keep waiting B – go to a new state S2 Q: What should S2 do? A: Turn on the laser a

16 from button to display S L D B to laser from sensor DistanceMeasurer ... B' S2 L := '1' // laser on S3 L := '0' // laser off S0 S1 B L := '0' Dreg := 0 Add a state S2 that turns on the laser (L:='1') Then turn off laser (L:='0') in a state S3 Q: What do next? A: Start timer, wait to sense reflection a

16 f r om button t o display S L D B o laser om sensor DistanceMeasurer Inputs : B (bit), S (bit) Outputs : L (bit), D (16 bits) Local storage: Dreg, Dctr (16 bits) B' S' // no reflection S // reflection ? S0 S1 S2 S3 B L := '0' Dctr := 0 // reset cycle count L := '1' L := '0' Dreg := 0 Dctr := Dctr + 1 // count cycles a Stay in S3 until sense reflection (S) To measure time, count cycles while in S3 To count, declare local storage Dctr Initialize Dctr to 0 in S1. In S2 would have been O.K. too. Don't forget to initialize local storage—common mistake Increment Dctr each cycle in S3

from button Laser-based t o laser DistanceMeasurer Inputs : B (bit), S (bit) Outputs : L (bit), D (16 bits) Local storage: Dreg, Dctr (16 bits) distance D 16 S to display measurer B' from sensor S' S4 S0 S1 S2 S3 B S L := '0' Dctr := 0 L := '1' L := '0' Dreg := Dctr/2 // calculate D Dreg := 0 Dctr := Dctr+1 a Once reflection detected (S), go to new state S4 Calculate distance Assuming clock frequency is 3x108, Dctr holds number of meters, so Dreg:=Dctr/2 After S4, go back to S1 to wait for button again

HLSM Actions: Updates Occur Next Clock Cycle
Dctr := Dctr+1 S' S S' / S / Local storage updated on clock edges only Enter state on clock edge Storage writes in that state occur on next clock edge Can think of as occurring on outgoing transitions Thus, transition conditions use the OLD value, not the newly-written value Example: S0 S1 P := '1' Jreg := Jreg + 1 P := '0' Jreg := 1 B' B Inputs : B (bit) Outputs P (bit) // if B, 2 cycles high Local storage: Jreg (8 bits) !(Jreg<2) Jreg<2 ? 1 2 clk Jreg P 3 ( a ) b

RTL Design Process Capture behavior Convert to circuit
5.3 RTL Design Process Capture behavior Convert to circuit Need target architecture Datapath capable of HLSM's data operations Controller to control datapath External data outputs External control inputs Controller ... Datapath DP

Ctrl/DP Example for Earlier Cycles-High Counter
Preg Q I ld clr A B S add1 P ? Preg_clr Preg_ld m DP CountHigh (c) 32 a Create DP Connect with controller (a) First clear Preg to 0s Then increment Preg for each clock cycle that m is 1 P Preg m CountHigh Derive controller (b) S_Clr S_Wt m' S_Inc m Preg := 0 Preg := Preg + 1 //Clear Preg to 0s //Wait for m=='1' //Increment Preg CountHigh Inputs : (bit) Outputs P (32 bits) LocStr : Preg (32 bits) S_Clr S_Wt m' S_Inc m Preg_clr = 1 Preg_ld = 0 Preg_clr = 0 Preg_ld = 1 (d) //Preg := 0 //Wait for m=1 //Preg:=Preg+1 Controller CountHigh P Preg Q I ld clr A B S add1 Preg_clr Preg_ld DP 32 We created this HLSM earlier a a

RTL Design Process

Example: Soda Dispenser from Earlier
Quick overview example. More details of each step to come. 8 s 8 a 8 ld clr tot tot_ld tot_clr 8 a Inputs : c (bit), a (8 bits), s (8 bits) Outputs d (bit) // '1' dispenses soda Local stor a g e tot (8 bits) W ait Disp Init d:='0' tot:=0 c’*(tot<s)’ c' * ( tot<s ) d:='1' tot:=tot+a SodaDispenser 8-bit < 8-bit adder tot_lt_s Datapath Step 2A a Step 1 Step 2B

Example: Soda Dispenser
Quick overview example. More details of each step to come. Inputs : c (bit), a (8 bits) , s (8 bits) Outputs d (bit) // '1' dispenses soda Local stor a g e tot (8 bits) W ait Disp Init d:='0' tot:=0 c’*(tot<s)’ c' * ( tot<s ) d:='1' tot:=tot+a SodaDispenser Step 2B Inputs : c, tot_lt_s (bit) Outputs d, tot_ld , tot_clr Wait Disp Init d=0 tot_clr=1 c' * tot_lt_s’ c d=1 tot_ld=1 d Controller Add Step 1 Step 2C

Example: Soda Dispenser
Quick overview example. More details of each step to come. Step 2C Inputs : c, tot_lt_s (bit) Outputs d, tot_ld , tot_clr Wait Disp Init d=0 tot_clr=1 c * d=1 tot_ld=1 d Controller Add Use controller design process (Ch3) to complete the design a

RTL Design Process—Step 2A: Create a datapath
Sub-steps HLSM data inputs/outputs  Datapath inputs/outputs. HLSM local storage item  Instantiated register "Instantiate": Add new component ("instance") to design Each HLSM state action and transition condition data computation  Datapath components and connections Also instantiate multiplexors as needed Need component library from which to choose A B S add reg Q I ld clr lt cmp eq gt mux2x1 1 s0 S = A+B (unsigned) A<B: lt=1 A=B: eq=1 A>B: gt=1 s0=0: Q= s0=1: Q= clk^ and clr=1: Q=0 clk^ and ld=1: Q= else Q stays same shift<L/R> shiftL1: <<1 shiftL2: <<2 shiftR1: >>1 ...

Step 2A: Create a Datapath—Simple Examples
Preg Q I ld clr A B S add2 add1 X Y Z (a) Preg = X + Y + Z X + Y X + Y + Z P 1 DP Preg = Preg + X X P Preg Q I ld clr A B S add1 (b) 1 DP Preg=X+Y; regQ=Y+Z X Y Z P Preg Q regQ I ld clr A B S add2 add1 (c) 1 DP k=0: Preg = Y + Z k=1: Preg = X + Y X Y Z P Preg Q I ld clr A B S add2 add1 (d) 1 mux2x1 s0 k DP a

Laser-Based Distance Measurer—Step 2A: Create a Datapath
1 16 Datapath 16 a A B S Add1: add(16) HLSM data I/O  DP I/O HLSM local storage  reg HLSM state action and transition condition data computation  Datapath components and connections Shr1: shiftR1(16) I Q 16 Dreg_clr Dreg_ld 16 Dctr_clr Dctr_ld clr ld Q Dctr: reg(16) I clr ld Q I Dreg: reg(16) 16 D

Laser-Based Distance Measurer—Step 2B: Connecting the Datapath to a Controller
to laser from button Controller from sensor S Dreg_clr Dreg_ld Dctr_clr Dctr_ld Datapath 300 MHz Clock D to display 16 a

Laser-Based Distance Measurer—Step 2C: Derive the Controller FSM
HLSM FSM has same states, transitions, and control I/O Achieve each HLSM data operation using datapath control signals in FSM Controller Inputs : B, S Outputs : L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld B S a B S S0 S1 S2 S3 S4 L = 0 L = 0 L = 1 L = 0 L = 0 Dreg_clr = 1 Dreg_l d = 0 Dctr_cl r Dctr_ld = 0 (laser off ) (clear Dreg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_ld (clear count) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr Dctr_ld = 0 (laser on) Dreg_clr = 0 Dreg_ld Dctr_clr Dctr_ld = 1 (laser off) (count up) Dreg_clr = 0 Dreg_ld = 1 Dctr_clr Dctr_ld = 0 (load Dreg with Dctr/2) (stop counting)

Laser-Based Distance Measurer—Step 2C: Derive the Controller FSM
Same FSM, using convention of unassigned outputs implicitly assigned 0 Some assignments to 0 still shown, due to their importance in understanding desired controller behavior

5.4 More RTL Design Additional datapath components

RTL Design Involving Register File or Memory
HLSM array: Ordered list of items Ex: Local storage: A[4](8-bit) – 4 8-bit items Accessed using notation "A[i]", i is index A[0] := 9; A[1] := 8; A[2] := 7; A[3] := 22 Array contents now: <9, 8, 7, 22> X := A[1] will set X to 8 Note: First element's index is 0 Array can be mapped to instantiated register file or memory

Simple Array Example (a) (b) (c) Init1 Init2 Out1 A[0] := 9
Preg := A[1] ArrayEx Inputs : (none) Outputs P (11 bits) Local storage : A[4](11 bits) A[1] := 12 A[0] == 8 (A[0] == 8)' Preg := 0 Preg (11 bits) Simple Array Example a Preg Q I ld clr P Preg_clr Preg_ld DP (b) 11 A RF[4](11) R_d W_e W_a W_d R_e R_a Amux 1 s0 9 12 A_Wa0 A_Wa1 A_We A_Ra0 A_Ra1 A_Re A_s B lt Acmp eq gt 8 A_eq_8 Controller (c) Init1 Init2 Out1 A_s = 0 A_Wa1=0, A_Wa1=0 A_We = 1 Preg_ld = 1 ArrayEx Inputs : A_eq_8 Outputs A_s, A_Wa0, ... A_s = 1 A_Wa1=0, A_Wa0=1 (A_eq_8)' Preg_clr = 1 A_Ra1=0, A_Ra0=0 A_Re = 1 a

RTL Example: Video Compression – Sum of Absolute Differences
Only difference: ball moving Digitized frame 1 Frame 1 1 Mbyte ( a ) Digitized frame 2 1 Mbyte Frame 2 Digitized frame 1 Frame 1 1 Mbyte ( b ) Difference of 2 from 1 0.01 Mbyte Frame 2 Just send difference a Video is a series of frames (e.g., 30 per second) Most frames similar to previous frame Compression idea: just send difference from previous frame

RTL Example: Video Compression – Sum of Absolute Differences
compare Each is a pixel, assume represented as 1 byte (actually, a color picture might have 3 bytes per pixel, for intensity of red, green, and blue components of pixel) Frame 1 Frame 2 Need to quickly determine whether two frames are similar enough to just send difference for second frame Compare corresponding 16x16 “blocks” Treat 16x16 block as 256-byte array Compute the absolute value of the difference of each array item Sum those differences – if above a threshold, send complete frame for second frame; if below, can use difference method (using another technique, not described)

Array Example: Video Compression—Sum-of-Absolute Differences
SAD !go (i<256)’ S0 S1 S2 S3 S4 go sum := 0 i := 0 i<256 sum:=sum+abs(A[i]-B[i]) i := i + 1 sadreg := sum ( b ) Inputs : A, B [256](8 bits); go (bit) Outputs : sad (32 bits) Local storage : sum, sadreg (32 bits); i (9 bits) RF[256](8) B sad RF[256](8) go a S0: wait for go S1: initialize sum and index S2: check if done ( (i<256)’ ) S3: add difference to sum, increment index S4: done, write to output sad_reg

Array Example: Video Compression—Sum-of-Absolute Differences
i_lt_256 i_inc i_clr sum_ld sum_clr sadreg_ld Datapath sum sadreg sad AB_addr A_data B_data cmp 9 32 8 i – + abs sadreg_clr lt 256 A B S0 S1 S2 S3 S4 go AB_rd sum=0 sum_clr=1 i=0 i_clr=1 i<256 i_lt_256 (i<256)’ (i_lt_256) sum=sum+abs(A[i]-B[i]) sum_ld=1; AB_rd=1 i=i+1 i_inc=1 sad_reg = sum sadreg_ld=1 Controller a

Circuit vs. Microprocessor
Circuit: Two states (S2 & S3) for each i, 256 i’s 512 clock cycles Microprocessor: Loop (for i = 1 to 256), but for each i, must move memory to local registers, subtract, compute absolute value, add to sum, increment i – say 6 cycles per array item  256*6 = 1536 cycles Circuit is about 3 times (300%) faster (assuming equal cycle lengths) Later, we’ll see how to build SAD circuit that is much faster S3 sum:=sum+abs(A[i]-B[i]) i:=i+1 S2 i<256 (i<256)’

Common RTL Design Pitfall Involving Storage Updates
Questions Value of Q after state A? Final state is C or D? Answers Q is NOT 99 after state A Q is 99 in state B, so final state is C Storage update actions in state occur simultaneously on next clock edge Thus, order actions are written is irrelevant A's actions same if: Q:=R R:= or R:=99 Q:=R Local storage : R, Q (8 bits) R<100 C A B (R<100)' R:=99 R:=R+1 D Q:=R ? 99 A 100 B C R<100 clk R Q a

Common RTL Design Pitfall Involving Storage Updates
New HLSM using extra state so read of R occurs after write of R Local storage : R, Q (8 bits) C R<100 A B B2 (R<100)' R:=99 R:=R+1 D Q:=R Q:=R R<100 (R<100)' A B B2 D clk 99 100 R ? 99 100 100 Q ? ? 99 99

RTL Design Involving a Timer
Commonly need explicit time intervals Ex: Repeatedly blink LED on 1 second, off 1 second Pre-instantiate timer that HLSM can then use L Init L:='0' T:= T_en:='0' Timer: T Outputs : L (bit) BlinkLed Off T_en:='1' T_Q' On L:='1' T_Q (b) load enable Q 32-bit 1-microsec timer T 32 M T_ld T_en T_Q T_M BlinkLed L (a) Pre-instantiated timer a a HLSM making use of timer

Button Debouncing Press button
Ideally, output changes to 1 Actually, output bounces Due to mechanical reasons Like ball bouncing when dropped to floor Digital circuit can convert actual signal closer to ideal signal button B B 1 Ideal: B Actual: B bounce a

Data Dominated RTL Design Example
Data dominated design: Extensive DP, simple controller Control dominated design: Complex controller, simple DP Example: Filter Converts digital input stream to new digital output stream Ex: Remove noise 180, 180, 181, 180, 240, 180, 181 240 is probably noise, filter might replace by 181 Simple filter: Output average of last N values Small N: less filtering Large N: more filtering, but less sharp output

Data Dominated RTL Design Example: FIR Filter
“Finite Impulse Response” Simply a configurable weighted sum of past input values y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2) Above known as “3 tap” Tens of taps more common Very general filter – User sets the constants (c0, c1, c2) to define specific filter RTL design Step 1: Create HLSM Very simple states/transitions X Y 12 digital filter 12 clk y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2) Assume constants set to 3, 2, and 2

FIR Filter Step 2A: Create datapath
Step 2B: Connect Ctrlr/DP (as earlier examples) Step 2C: Derive FSM Set clr and ld lines appropriately

Circuit vs. Microprocessor
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2) Comparing the FIR circuit to microprocessor instructions Microprocessor 100-tap filter: 100 multiplications, 100 additions. Say 2 instructions per multiplication, 2 per addition. Say 10 ns per instruction. (100* *2)*10 = 4000 ns Circuit Assume adder has 2 ns delay, multiplier has 20 ns delay Longest path goes through one multiplier and two adders = 24 ns delay 100-tap filter, following design on previous slide, would have about a 34 ns delay: 1 multiplier and 7 adders on longest path Circuit is more than 100 times faster (4000/34). Wow.

Determining Clock Frequency
5.5 Determining Clock Frequency Designers of digital circuits often want fastest performance Means want high clock frequency Frequency limited by longest register-to-register delay Known as critical path If clock is any faster, incorrect data may be stored into register Longest path on right is 2 ns Ignoring wire delays, and register setup and hold times, for simplicity a + b c 2 ns del y clk

Critical Path + Example shows four paths Longest path is thus 7 ns
a to c through +: 2 ns a to d through + and *: 7 ns b to d through + and *: 7 ns b to d through *: 5 ns Longest path is thus 7 ns Fastest frequency 1 / 7 ns = 142 MHz a b 2 ns 7 ns 2 ns 7 ns 2 ns + * 5 ns del a y del a y Max (2,7,7,5) = 7 ns c d a

Critical Path Considering Wire Delays
Real wires have delay too Must include in critical path Example shows two paths Each is = 3 ns Trend 1980s/1990s: Wire delays were tiny compared to logic delays But wire delays not shrinking as fast as logic delays Wire delays may even be greater than logic delays! Must also consider register setup and hold times, also add to path Then add some time to the computed path, just to be safe e.g., if path is 3 ns, say 4 ns instead clk a b 3 ns 3 ns 0.5 ns 0.5 ns + 2 ns a 0.5 ns c

A Circuit May Have Numerous Paths
Paths can exist In the datapath In the controller Between the controller and datapath May be hundreds or thousands of paths Timing analysis tools that evaluate all possible paths automatically very helpful s a Combinational logic 8 8 d ( a ) tot_ld ld tot ( c ) t ot_clr c clr 8 tot_lt_s n1 ( b ) 8-bit 8-bit n0 < adder tot_lt_s 8 Datapath a s1 s0 clk State register

Behavioral Level Design: C to Gates
5.6 Behavioral Level Design: C to Gates Inputs : A, B [256](8 bits); go (bit) i n t SAD (byte A[256], byte B[256]) // not quite C syntax { uint sum; short uint I; sum = 0; i = 0; while (i < 256) { sum = sum + abs(A[i] – B[i]); i = i + 1; } return sum; C code Outputs : sad (32 bits) Local storage : sum, sadreg (32 bits); i (9 bits) S0 !go go sum := 0 S1 i := 0 S2 i<256 (i<256)’ sum:=sum+abs(A[i]-B[i]) S3 i := i + 1 S4 sadreg := sum a Earlier sum-of-absolute-differences example Started with high-level state machine C code is an even better starting point -- easier to understand

Converting from C to High-Level State Machine
Convert each C construct to equivalent states and transitions Assignment statement Becomes one state with assignment If-then statement Becomes state with condition check, transitioning to “then” statements if condition true, otherwise to ending state “then” statements would also be converted to states target := expression a target = expression; cond’ cond (end) if (cond) { // then stmts } a (then stmts)

Converting from C to High-Level State Machine
If-then-else Becomes state with condition check, transitioning to “then” statements if condition true, or to “else” statements if condition false While loop statement Becomes state with condition check, transitioning to while loop’s statements if true, then transitioning back to condition check cond’ cond (end) (then stmts) (else stmts) if (cond) { // then stmts } else { // else stmts a cond’ cond (while stmts) (end) while (cond) { // while stmts } a

Simple Example of Converting from C to High-Level State Machine
(end) (then stmts) (else stmts) (b) X>Y (X>Y)’ (end) (c) X>Y (X>Y)’ (a) Inputs: uint X, Y Outputs: uint Max if (X > Y) { } else { Max = X; Max = Y; Max:=X Max:=Y a a Simple example: Computing the maximum of two numbers Convert if-then-else statement to states (b) Then convert assignment statements to states (c)

Example: SAD C code to HLSM
Inputs : b yte A[256],B[256] ( b ) (go')' go' ( c ) go' go sum:=0 i=0 ( d ) go' go sum:=0 i:=0 bit go ; Output : int sad main() { Convert each construct to states Simplify, e.g., merge states RTL design process to convert to circuit Can thus convert C to circuit using straightforward process Actually, subset of C (not all C constructs easily convertible) Can use language other than C uint sum ; sho r t uint i ; while (1) { while (!go) ; sum = 0 ; i = 0 ; while (i < 256) { sum = sum + abs(A[i] – B[i]) ; i = i + 1 ; ( g ) go' go sum:=0 i:=0 (i<256)' i<256 sadreg := sum sum:=sum + ab s .. . i := i + 1 } } sad = sum ; } go' go ( a ) go' go sum:=0 i:=0 sum:=0 i:=0 (i<256)' i<256 ( e ) while stmts (i<256)' i<256 sum:=sum + ab s .. . i := i + 1 a sadreg := sum ( f )

5.7 Memory Components RTL design instantiates datapath components to create datapath, controlled by a controller Some components are used outside the controller and DP MxN memory M words, N bits wide each Several varieties of memory, which we now introduce M words N-bits wide each M × N memo r y

Random Access Memory (RAM)
RAM – Readable and writable memory “Random access memory” Strange name—Created several decades ago to contrast with sequentially-accessed storage like tape drives Logically same as register file—Memory with address inputs, data inputs/outputs, and control RAM usually one port; RF usually two or more RAM vs. RF RAM typically larger than about 512 or 1024 words RAM typically stores bits using a bit storage approach that is more efficient than a flip-flop RAM typically implemented on a chip in a square rather than rectangular shape—keeps longest wires (hence delay) short 32 4 W_data W_addr W_en R_data R_addr R_en 16 × register file Register file from Chpt. 4 32 data 10 addr 1024 × 32 r w R A M en RAM block symbol

RAM Internal Structure
wdata(N-1) wdata(N-2) wdata0 Let A = log2M 32 10 data addr r w en 1024x32 RAM bit storage block (aka “cell”) w o r d word a0 a1 d0 d1 d(M-1) a(A-1) e AxM decoder enable addr0 addr1 RAM cell word enable r w data cell data addr(A-1) Combining rd and wr data lines clk en r w to all cells rdata(N-1) rdata(N-2) rdata0 Similar internal structure as register file Decoder enables appropriate word based on address inputs rw controls whether cell is written or read rd and wr data lines typically combined Let’s see what’s inside each RAM cell

Static RAM (SRAM) “Static” RAM cell 1 SRAM cell SRAM cell
data data’ cell 32 10 data addr r w en 1024x32 RAM d d’ a word enable SRAM cell data data’ d word enable “Static” RAM cell 6 transistors (recall inverter is 2 transistors) Writing this cell word enable input comes from decoder When 0, value d loops around inverters That loop is where a bit stays stored When 1, the data bit value enters the loop data is the bit to be stored in this cell data’ enters on other side Example shows a “1” being written into cell 1 a data data’ d’ d cell word enable 1 a

Static RAM (SRAM) “Static” RAM cell SRAM cell Reading this cell
32 10 data addr r w en 1024x32 RAM SRAM cell “Static” RAM cell Reading this cell Somewhat trickier When rw set to read, the RAM logic sets both data and data’ to 1 The stored bit d will pull either the left line or the right bit down slightly below 1 “Sense amplifiers” detect which side is slightly pulled down The electrical description of SRAM is really beyond our scope – just general idea here, mainly to contrast with DRAM... data data’ 1 d 1 1 <1 a word enable To sense amplifiers

Dynamic RAM (DRAM) “Dynamic” RAM cell 1 transistor (rather than 6)
32 10 data addr r w en 1024x32 RAM DRAM cell “Dynamic” RAM cell 1 transistor (rather than 6) Relies on large capacitor to store bit Write: Transistor conducts, data voltage level gets stored on top plate of capacitor Read: Just look at value of d Problem: Capacitor discharges over time Must “refresh” regularly, by reading d and then writing it right back data c ell word enable d capacitor slowly discharging ( a ) data enable discharges d ( b )

Comparing Memory Types
Register file Fastest But biggest size SRAM Fast More compact than register file DRAM Slowest And refreshing takes time But very compact Use register file for small items, SRAM for large items, and DRAM for huge items Note: DRAM’s big capacitor requires a special chip design process, so DRAM is often a separate chip MxN Memory implemented as a: register file SRAM DRAM Size comparison for same number of bits (not to scale)

Reading and Writing a RAM
clk clk 1 2 3 addr 9 13 9 addr valid setup time data 500 999 Z 500 data valid hold Z 500 time r w 1 means write r w setup time en access RAM[9] RAM[13] time now equals 500 now equals 999 Writing Put address on addr lines, data on data lines, set rw=1, en=1 Reading Set addr and en lines, but put nothing (Z) on data lines, set rw=0 Data will appear on data lines Don’t forget to obey setup and hold times In short – keep inputs stable before and after a clock edge ( b )

RAM Example: Digital Sound Recorder
data addr rw en wire 16 analog-to- digital-to- digital 12 ad_ b uf Ra Rrw Ren analog wire microphone co n v e r ter co n v e r ter ad_ld processor da_ld Behavior Record: Digitize sound, store as series of bit digital values in RAM We’ll use a 4096x16 RAM (12-bit wide RAM not common) Play back later Common behavior in telephone answering machine, toys, voice recorders To record, processor should read a-to-d, store read values into successive RAM words To play, processor should read successive RAM words and enable d-to-a spea k er

analog-to- digital converter digital-to- analog ad_ld da_ld Rw Ren Ra 12 16 processor ad_buf 4096x16 RAM RTL design of processor Create HLSM Begin with the record behavior Create local storage a Stores current address, ranges from 0 to 4095 (thus need 12 bits) Create state machine that counts from 0 to 4095 using a For each a Read analog-to-digital conv. ad_ld:=‘1’, ad_buf:=‘1’ Write to RAM at address a Rareg:=a, Rrw:=‘1’, Ren:=‘1’ Record behavior S a:=0 a:=a+1 (a<4095)’ a<4095 T U Local register: a, Rareg (12 bits) ad_ld:=‘1’ ad_buf:=‘1’ a Rareg:=a Rrw:=‘1’ Ren:=‘1’

analog-to- digital converter digital-to- analog ad_ld da_ld Rw Ren Ra 12 16 processor ad_buf 4096x16 RAM Now create play behavior Use local register a again, create state machine that counts from 0 to 4095 again For each a Read RAM Write to digital-to-analog conv. Note: Must write d-to-a one cycle after reading RAM, when the read data is available on the data bus The record and play state machines would be parts of a larger state machine controlled by signals that determine when to record or play data bus Play behavior V a:=‘0’ a:=a+1 (a<4095)’ a<4095 W X Local register: a,Rareg (12 bits) a ad_buf:=‘0’ Rareg:=a Rrw=‘0’ Ren=‘1’ da_ld:=‘1’

Read-Only Memory – ROM Memory that can only be read from, not written to Data lines are output only No need for rw input Advantages over RAM Compact: May be smaller Nonvolatile: Saves bits even if power supply is turned off Speed: May be faster (especially than DRAM) Low power: Doesn’t need power supply to save bits, so can extend battery life Choose ROM over RAM if stored data won’t change (or won’t change often) For example, a table of Celsius to Fahrenheit conversions in a digital thermometer 32 10 data addr r w en 1024 × R A M RAM block symbol 32 10 data addr en 1024x32 ROM ROM block symbol

Read-Only Memory – ROM 32 10 data addr en 1024x32 ROM ROM block symbol Let A = log2M word bit storage enable block d0 (aka “cell”) addr0 a0 w o r d addr1 a1 AxM d1 decoder addr(A-1) addr data a(A-1) word word e d(M-1) enable enable clk data en ROM cell rdata(N-1) rdata(N-2) rdata0 Internal logical structure similar to RAM, without the data input lines

ROM Types If a ROM can only be read, how are the stored bits stored in the first place? Storing bits in a ROM known as programming Several methods Mask-programmed ROM Bits are hardwired as 0s or 1s during chip manufacturing 2-bit word on right stores “10” word enable (from decoder) simply passes the hardwired value through transistor Notice how compact, and fast, this memory would be 1 data line data line cell cell word enable

ROM Types Fuse-Based Programmable ROM Each cell has a fuse
A special device, known as a programmer, blows certain fuses (using higher-than-normal voltage) Those cells will be read as 0s (involving some special electronics) Cells with unblown fuses will be read as 1s 2-bit word on right stores “10” Also known as One-Time Programmable (OTP) ROM 1 data line 1 data line cell cell blown fuse a word enable fuse

ROM Types Erasable Programmable ROM (EPROM)
Uses “floating-gate transistor” in each cell Special programmer device uses higher-than-normal voltage to cause electrons to tunnel into the gate Electrons become trapped in the gate Only done for cells that should store 0 Other cells (without electrons trapped in gate) will be 1 2-bit word on right stores “10” Details beyond our scope – just general idea is necessary here To erase, shine ultraviolet light onto chip Gives trapped electrons energy to escape Requires chip package to have window data line data line floating-gate transistor c ell c ell 1 1 a word e - e - enable trapped electrons

ROM Types Electronically-Erasable Programmable ROM (EEPROM)
Similar to EPROM Uses floating-gate transistor, electronic programming to trap electrons in certain cells But erasing done electronically, not using UV light Erasing done one word at a time Flash memory Like EEPROM, but all words (or large blocks of words) can be erased simultaneously Became very common starting in late 1990s Both types are in-system programmable Can be programmed with new stored bits while in the system in which the ROM operates Requires bi-directional data lines, and write control input Also need busy output to indicate that erasing is in progress – erasing takes some time 32 10 data addr en write busy 1024x32 EEPROM

ROM Example: Talking Doll
“Hello there!” audio divided into 4096 samples, stored in ROM speaker 4096x16 ROM “Hello there!” “Hello there!” 16 a digital-to- analog vibration Ra Ren converter sensor da_ld processor v Doll plays prerecorded message, triggered by vibration Message must be stored without power supply  Use a ROM, not a RAM, because ROM is nonvolatile And because message will never change, may use a mask-programmed ROM or OTP ROM Processor should wait for vibration (v=1), then read words 0 to 4095 from the ROM, writing each to the d-to-a

ROM Example: Talking Doll
Local register: a, Rareg (12 bits) 4096x16 ROM processor Ra 16 Ren da_ld digital-to- analog converter v v a<4095 a:=‘0’ S T R areg:=a en:=‘1’ a U v’ da_ld:=‘1’ (a<4095)’ a:=a+1 HLSM Create state machine that waits for v=1, and then counts from 0 to 4095 using a local storage a For each a, read ROM, write to digital-to-analog converter

ROM Example: Digital Telephone Answering Machine Using a Flash Memory
Want to record the outgoing announcement When rec=1, record digitized sound in locations 0 to 4095 When play=1, play those stored sounds to digital-to-analog converter What type of memory? Should store without power supply – ROM, not RAM Should be in-system programmable – EEPROM or Flash, not EPROM, OTP ROM, or mask-programmed ROM Will always erase entire memory when reprogramming – Flash better than EEPROM analog-to- digital converter digital-to- analog ad_ld da_ld Rrw Ren er bu Ra 12 16 processor ad_buf 4096x16 Flash rec play record microphone speaker data “We’re not home.” addr erase busy rw en

ROM Example: Digital Telephone Answering Machine Using a Flash Memory
HLSM Once rec=1, begin erasing flash by setting er=1 Wait for flash to finish erasing by waiting for bu=0 Execute loop that sets local register a from 0 to 4095, reading analog-to-digital converter and writing to flash for each a analog-to- digital converter digital-to- analog ad_ld da_ld Rrw Ren er bu Ra 12 16 processor ad_buf 4096x16 Flash rec play record microphone speaker Local register: a, Rareg (13 bits) (a<4096)’ a<4096 U V ad_ld:=‘1’ ad_buf:=‘1’ Rareg:=a Rrw:=‘1’ Ren:=‘1’ a:=a+1 a:=‘0’ T er:=‘0’ bu bu’ a er:=‘1’ r ec S

Blurring of Distinction Between ROM and RAM
We said that RAM is readable and writable ROM is read-only But some ROMs act almost like RAMs EEPROM and Flash are in-system programmable Essentially means that writes are slow Also, number of writes may be limited (perhaps a few million times) And, some RAMs act almost like ROMs Non-volatile RAMs: Can save their data without the power supply One type: Built-in battery, may work for up to 10 years Another type: Includes ROM backup for RAM – controller writes RAM contents to ROM before turning off New memory technologies evolving that merge RAM and ROM benefits e.g., MRAM Bottom line Lot of choices available to designer, must find best fit with design goals ROM RAM Flash EEPROM NVRAM a

5.8 Queues (FIFOs) A queue is another component sometimes used during RTL design Queue: A list written to at the back, from read from the front Like a list of waiting restaurant customers Writing called a push, reading called a pop Because first item written into a queue will be the first item read out, also called a FIFO (first-in-first-out) back front write items read (and to the back remove) items of the queue from front of the queue

Queues Queue has addresses, and two pointers: rear and front
r f 1 2 3 4 5 6 7 Queue has addresses, and two pointers: rear and front Initially both point to 0 Push (write) Item written to address pointed to by rear rear incremented Pop (read) Item read from address pointed to by front front incremented If front or rear reaches 7, next (incremented) value should be 0 (for a queue with addresses 0 to 7) f r A 1 2 3 4 5 6 7 a f r A B 1 2 3 4 5 6 7 a f r B 1 2 3 4 5 6 7 A a

Queues Treat memory as a circle Two conditions of interest
If front or rear reaches 7, next (incremented) value should be 0 rather than 8 (for a queue with addresses 0 to 7) Two conditions of interest Full queue – no room for more items In 8-entry queue, means 8 items present No further pushes allowed until a pop occurs Causes front=rear Empty queue – no items No pops allowed until a push occurs Both conditions have front=rear To detect whether front=rear means full or empty, need state machine that detects if previous operation was push or pop, sets full or empty output signal (respectively) f r B 1 2 3 4 5 6 7 A B 1 7 2 6 3 5 4 f r a

Queue Implementation Can use register file for item storage
Implement rear and front using up counters rear used as register file’s write address, front as read address Simple controller would set control lines for pushes and pops, and also detect full and empty situations FSM for controller not shown 8x16 register file 16 16 wdata rdata wdata rdata 3 3 w addr r addr wr rd clr wr clr inc inc rd 3-bit 3-bit up counter up counter Controller rear front reset = eq full empty 8- w ord 16-bit queue

Common Uses of a Queue Computer keyboard Digital video recorder
Pushes pressed keys onto queue, meanwhile pops and sends to computer Digital video recorder Pushes captured frames, meanwhile pops frames, compresses them, and stores them Computer network routers Pushes incoming packets onto queue, meanwhile pops packets, processes destination information, and forwards each packet out over appropriate port

Queue Usage Example Example series of pushes and pops
r f 1 2 3 4 5 6 7 I nitially emp t y queue Example series of pushes and pops Note how rear and front pointers move Note that popping doesn’t really remove the data from the queue, but that data is no longer accessible Note how rear (and front) wraps around from address 7 to 0 Note: pushing a full queue is an error So is popping an empty queue f r 1 2 3 4 5 6 9 8 7 1. A t er pushing 9, 5, 8, 5, 7, 2, 3 f r 1 2 3 4 5 6 7 9 8 d a ta: 2. A t er popping a f r 1 2 3 4 5 6 7 9 8 3. A t er pushing 6 r f 1 2 3 4 5 6 7 full 8 4. A f t er pushing 3 ERROR! Pushing a full queue r esults in unknown state. 5. A f t er pushing 4

Multiple Processors Using multiple processors can ease design 5.9
Keeps distinct behaviors separate Ex: Laser-based distance measurer with button debounce Use two processors Ex: Code detector with button press synchronizers (BPS) BPS processor for each input, plus CodeDetector processor Laser-based distance measurer 16 from b utton to displ a y S L D B to laser from sensor ButtonDebouncer Bin Bout Sta r t Red Green Blue si i gi bi ai Door lo c k u Code detector s g b a BPS

Interfacing Multiple Processors
Use signal, register, or other component outside processors Known as global Common methods use global... control signal, data signal, register, register file, queue Typically all multiple processors and clocked globals use same clock Synchronized

Ex: Temperature Statistics with Multiple Processors
16-bit unsigned input T from temperature sensor, 16-bit output A. Sample T every 1 second. Compute output A every minute, should equal average of most recent 64 samples. Single HLSM: Complicated Instead, two HLSMs (and hence two processors) and shared register file Tsample HLSM: Store T into successive RF address, once per sec. Avg HLSM: Compute and output average of all 64 RF words, once per min. Note that each uses distinct timer Keeping the sampling and averaging behaviors separate leads to simple design a

Ex: Digital Camera with Mult. Processors and Queue
Read and Compress processors (Ch 1) Compress may take longer, depends on picture Use queue, read can push additional pics (up to 8) Likewise, use queue between Compress and Store Image sensor Queue [8](8) wdata wr full 8 rdata empty rd Read Compress Queue [8](8) Store circuit Memo r y circuit circuit a

Hierarchy – A Key Design Concept
5.10 Hierarchy – A Key Design Concept Hierarchy Organization with few items at the top, with each item decomposed into other items Common example: Country 1 item at top (the country) Country item decomposed into state/province items Each state/province item decomposed into city items Hierarchy helps us manage complexity To go from transistors to gates, muxes, decoders, registers, ALUs, controllers, datapaths, memories, queues, etc. Imagine trying to comprehend a controller and datapath at the level of gates CityA CityD CityF a Province 2 Province 1 Province 3 CityB CityE CityG CityC Country A Province 2 Province 1 Province 3 Country A Map showing just top two levels of hierarchy

Hierarchy and Abstraction
Hierarchy often involves not just grouping items into a new item, but also associating higher-level behavior with the new item, known as abstraction Ex: 8-bit adder has understandable high-level behavior—adds two 8-bit binary numbers Frees designer from having to remember, or even understand, the lower-level details a7.. a0 b7.. b0 8-bit adder ci c o s7.. s0

Hierarchy and Composing Larger Components from Smaller Versions
A common task is to compose smaller components into a larger one Gates: Suppose you have plenty of 3-input AND gates, but need a 9-input AND gate Can simple compose the 9-input gate from several 3-input gates Muxes: Suppose you have 4x1 and 2x1 muxes, but need an 8x1 mux s2 selects either top or bottom 4x1 s1s0 select particular 4x1 input Implements 8x1 mux – 8 data inputs, 3 selects, one output 4x1 i0 i0 a i1 i1 i2 i2 d i3 i3 2x1 s1 s0 i0 d i1 4x1 i4 i0 s0 i5 i1 i6 i2 d i3 P r o vin c s1 s0 e 1 1 s1 s0 s2

Composing memory very common Making memory words wider Easy – just place memories side-by-side until desired width obtained Share address/control lines, concatenate data lines Example: Compose 1024x8 ROMs into 1024x32 ROM 10 addr addr addr addr 1024x8 1024x8 1024x8 1024x8 addr ROM ROM ROM ROM en en en en data data data data en 8 8 8 8 data(31..0) 1024x32 ROM data 32 10

11 Creating memory with more words Put memories on top of one another until the number of desired words is achieved Use decoder to select among the memories Can use highest order address input(s) as decoder input Although actually, any address line could be used Example: Compose 1024x8 memories into 2048x8 memory a9..a0 addr addr 1x2 1024x8 a10 d0 i0 dcd ROM e d1 en data 8 en addr 1024x8 2048x8 ROM data 8 11 en addr ROM en data 1024x8 ROM addr en data a0 a10 a9 a8 a10 just chooses which memory to access 8 a a P P r r o o vin vin c a To create memory with more words and wider words, can first compose to enough words, then widen.

Chapter Summary Modern digital design involves creating processor-level components High-level state machines RTL design process 1. Capture behavior: Use HLSM 2. Convert to circuit A. Create datapath B. Connect DP to controller C. Derive controller FSM More RTL design More components, arrays, timers, control vs. data dominated Determining fastest clock frequency By finding critical path Behavioral-level design – C to gates By using method to convert C (subset) to high-level state machine Memory components (RAM, ROM) Queues Multiple processors Hierarchy: A key concept used throughout Chapters 2-5

Chapter 1: Introduction

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