1. Design Lab with SystemC
A SoC Design Automation
School of EECS
Seoul National University

2. Outline How to Download SystemC How to Install SystemC
Download procedure
OSCI homepage
How to Install SystemC
System Requirements
Cygwin installation
SystemC Installation notes
Directory tree
Running an example
Useful SystemC Tools
Simulation tools
Debugging tools
Examples
Simple Counter
DCT

3. How to Download SystemC
Download procedure
SystemC download website
Visit OSCI home page:
About SystemC  Download (OSCI standards)
Download what you want
We assume Cygwin (Windows) for the OS throughout this lecture.
Core SystemC language and examples
‘systemc tgz’
You may need a registration for download.

4. How to Download SystemC
OSCI homepage

5. How to Install SystemC System requirements For SystemC release 2.2.0
UNIX platform
Sun Solaris
Linux
HP_UX
Windows platform
Windows NT with Visual C++ 6.0
Cygwin

6. SystemC Installation with Windows Cygwin
Cygwin installation
Cygwin is a UNIX environment, developed by RedHat, for windows.
Installation guide
Cygwin home page 
Click 'Install or update now!'
Run ‘setup.exe’ to get Cygwin packages
Select “install from internet”
Select install directory and local package directory
Select “direct connection”
Select your preferred ftp site
Change to
‘C:\cygwin’ will be the installation directory

7. SystemC installation notes
How to Install SystemC
SystemC installation notes
Uncompress the ‘systemc tgz’ file on your working dir.
- We assume current working directory is ‘/home/userid/works’
tar zxvf systemc tgz
Change to the top level directory (systemc-2.2.0)
cd systemc-2.2.0
Create a installation directory and change to that directory, e.g.,
mkdir build
cd build
Configure the package for your system
../configure –prefix=/home/userid/works/systemc-2.2.0/build
It will automatically generate the Makefile
Compile the package
> make (or gmake)
Install the package
> make install (or gmake install)

8. Directory tree systemc-2.2.0/ config/ docs/ examples/ msvc60/ src/
How to Install SystemC
Directory tree
systemc-2.2.0/
config/
docs/
examples/
msvc60/
src/
build/
include/
lib-cygwin/
Install directory that contains ‘systemc.h’ header file and ‘libsystemc.a’ system-dependent library file

9. How to Install SystemC
Running an example
Move to the directory for pipe example (e.g. systemc-2.2.0/examples/pipe/ )
> cd ./examples/sysc/pipe/
Read the brief description of the example in the ‘README’ file
Build the example using make
> make check

10. How to Install SystemC
Run the executable
./pipe

11. GTKWave: electronic waveform viewer
Useful SystemC Tools
Useful SystemC Tools
GTKWave: electronic waveform viewer
Viewer for waveforms in [VCD/EVCD/LXT/Synopsys] output format
Built using the GTK+ toolkit
GTKWave home page
GTKWave installation with Cygwin
Get ‘gtkwave setup.exe’ from ftp://ftp.cs.man.ac.uk/pub/amulet/gtkwave/1.3/
Run ‘gtkwave setup.exe’, which is self-extracting installation program
Make a symbolic link as follows
ln –s /cygdrive/c/Program\ Files/GTKWave\ /winwave.exe /usr/local/bin/gtkwave

12. Useful SystemC Tools
ModelSim 6.2
Unified kernel for Verilog, VHDL, and SystemC for a true mixed-language environment
Requires optional product add-on to ModelSim 6.2 SE/LE
An additional license is required
Download website

13. Debugging tools GDB INSIGHT DDD GNU source-level debugger
Useful SystemC Tools
Debugging tools
GDB
GNU source-level debugger
INSIGHT
Graphical user interface to GDB
DDD
Data display debugger

14. Examples Simple Counter Environment Function SystemC-2.2.0
Cygwin with gcc compiler
GTKWave waveform viewer
Function
Count from ‘0’ to ‘255’
Reset signal set cntvalue[7:0] signal to ‘0x00’
If count it up to ‘255’, overflow signal is set to ‘1’.

15. Simple counter block diagram
Examples
Simple counter block diagram
testbench
count
reset
overflow
cntvalue[7:0]
clk
clk
clock

16. Counter module: counter.h
Examples
Counter module: counter.h
in/out ports
process function
data member
process registration
sensitivity list
initialization

17. Counter module: counter.cpp
Examples
Counter module: counter.cpp
reset behavior
Increase the ‘local_cntvalue’ on clock rising edge
overflow detect
‘local_cntvalue’ to cntvalue port

18. Examples
Testbench module

19. Top level 10 ns module instantiation & pin connection
Examples
Top level
10 ns
module instantiation & pin connection
trace file (wave.vcd) generation
SystemC simulation start for ‘simul_time’

20. Examples
Makefile

21. Examples
Compilation
make

22. Simulation reset  restart the count
Examples
Simulation
reset  restart the count
overflow  set overflow signal & restart the count

23. Waveform ‘wave.vcd’ file is generated after executing the ‘run.x’.
Examples
Waveform
‘wave.vcd’ file is generated after executing the ‘run.x’.

24. Append the signal names to waveform list
Examples
Append the signal names to waveform list

25. Examples
Simulated waveform

26. Examples
Reset test

27. Examples
Overflow test

28. Algorithm level DCT simulation
Examples
Algorithm level DCT simulation
Functional block diagram
Data Gen
function
(for input
data setup)
FDCT
function
‘sample1’
‘result’
fdct(in, out)
Implemented in C code

29. FDCT source code in C ‘fdct_ref.c’ from MPEG Software Simulation Group
Examples
FDCT source code in C
‘fdct_ref.c’ from MPEG Software Simulation Group
Forward DCT  8x8 matrix of 16-bit data value

30. Input/output of ‘fdct’ function Input: ‘sample1’ Output: ‘result’
Examples
Input/output of ‘fdct’ function
Input: ‘sample1’
Output: ‘result’

31. Timed level DCT simulation
Examples
Timed level DCT simulation
Top level block diagram
f_in[64]
f_out[64]
DataGen
Module
FDCT
Module
Sink
Module
request
ready
valid
ack
clock

32. Assignment These files are given from presentation.
Examples
Assignment
These files are given from presentation.
header files
data_gen_sc.h
sink_sc.h
c++ files
data_gen_sc.cpp
sink_sc.cpp
main.cpp
Make file
Makefile
Sample file
sample1
You can make your own fdct module.
header file
fdct_sc.h
c++ file
fdct_sc.cpp

33. DataGen Module data_gen_sc.h 64 parallel output port
Examples
DataGen Module
data_gen_sc.h
64 parallel
output port
ports for handshake
text file pointer for read data
set file pointer to ‘sample1’ text file
read and send data to fdct module & synchronize

34. Examples
data_gen_sc.cpp
Data_gen_module::set_input(char*)

35. Data_gen_module::do_gen()
Examples
Data_gen_module::do_gen()

36. fdct module & synchronize
Examples
Sink module
sink_sc.h
64 parallel
in port
ports for handshake
read data from
fdct module & synchronize

37. Examples
sink_sc.cpp

38. Examples
Top module
main.cpp

39. This file is same with ‘exmple1’
Examples
Makefile & sample1 files
This file is same with ‘exmple1’

40. void init_fdct(void);
Examples
FDCT module (HW)
Now, you can make your own FDCT module.
FDCT Module
f_in[64]
f_out[64]
member variables
double c[8][8];
double tmp[64];
in[64]
out[64]
f_req
f_rdy
req
rdy
member function
void init_fdct(void);
f_vld
f_ack
ack
vld
process function
void do_fdct(void);
clk

41. ::init_fdct() ::do_fdct()
Examples
::init_fdct()
You can use the same behavior code that is used at algorithm level simulation
::do_fdct()
1. call init_fdct();
 To initialize coefficient (c[8][8])
2. send request to DataGen module;
3. while( vld==0 ) { wait(); }
4. turn off the request signal
5. while( vld==1 ) { wait(); }
6. delay computation cycles (8 cycles)
7. write code for DCT
 read input data into temp[64] and run DCT
8. set ready so that Sink module can receive the data
7. while( ack==0 ) { wait(); }
9. turn off the ready signal
10. while( ack==1 ) { wait(); }

42. Compile & Simulation make ./run.x sample1
Examples
Compile & Simulation
make
./run.x sample1
The result is same as c code does.

43. Run ‘gtkwave’ waveform viewer
Examples
Run ‘gtkwave’ waveform viewer

44. Examples
The waveform
8 cycle execution

45. Discussion Latency of DCT function Timed vs. Untimed Simulation speed
Examples
Discussion
Latency of DCT function
The waveform has been obtained by setting the latency of DCT function to 8 cycles.
Cycle accurate model can be obtained thru ‘wait()’ annotation.
Timed vs. Untimed
SystemC supports both timed and untimed models.
Simulation speed
Faster than other HDL simulators