Computer Organization and Architecture + Networks

Computer Organization and Architecture + Networks
Lecture 5 Memory and Cache Design Cache Memory Internal Memory External Memory

Introduction Computer memory – organized into a hierarchy Memory
Internal: directly accessible by the processor External: accessible by the processor Memory Hierarchy Highest Level (closest to processor)  Processor Registers Cache 1 or more (L1, L2,...) Main memory (made of dynamic random access memory (DRAM))  Internal to the computer disk Fixed hard disk Removable Media (Optical disks and tape)  External to the computer system

Introduction If we go from ①⑤, there is a 3 key characteristics of memory: decreasing cost/bit increasing capacity slower access time The following relationships: Faster access time means greater cost per bit Greater capacity means smaller cost per bit Greater capacity means slower access time

Memory Hierarchy - Diagram
Decreasing cost per bit Increasing capacity Increasing access time Decreasing access of the memory by the processor

Typical Levels in a Hierarchical Memory
Fig Names and key characteristics of levels in a memory hierarchy. Feb. 2011 Computer Architecture, Memory System Design

Desktop, Drawer, and File Cabinet Analogy
Once the “working set” is in the drawer, very few trips to the file cabinet are needed. Fig Items on a desktop (register) or in a drawer (cache) are more readily accessible than those in a file cabinet (main memory). Feb. 2011 Computer Architecture, Memory System Design

Cache Semiconductor RAM 128-512 KB 10 ns Main Memory 4-128 MB 50 ns
Memory Type Technology Size Access Time Cache Semiconductor RAM KB 10 ns Main Memory 4-128 MB 50 ns Magnetic Disk Hard Disk Gigabyte 10 ms, 10 MB/sec Optical Disk CD-ROM 300 ms, 600 KB/sec Magnetic Tape Tape 100s MB Sec-min, 10 MB/min

Characteristics of Memory System
Terms for Computer Memory Systems Location – Processor (Register); Internal (Main/Primary) eg. cache; External (Secondary) eg. disk and tape Capacity – amount of info that can be stored in a memory (in bytes/words) Unit of transfer – no. of data lines into/out of memory module  Size of the word: No of bits used to represent a number  Addressable Unit: Data element size that can be addressed in the memory

Terms for Computer Memory Systems Access method – how to access the content of memory Sequential access: data does not have a unique address - must read all data in sequence until the desired item is found - access time  highly variable eg. Tape drive Direct access: data item have unique address - access is done by using combination of moving to a general memory `area’ followed by a sequential access to reach desired data eg. Disk drives - variable access time

Terms for Computer Memory Systems Access method – how to access the content of memory Random Access: each item have a unique address - access can be selected at random - access time = same to all locations - eg. Main memory and some cache system Associative Access: variation to random access memory - data items are accessed based on their content and not their actual location - data are searched in parallel - eg. Some cache memory

Terms for Computer Memory Systems Performance - Access time (Latency): (i) For Random Access Memory (RAM) time taken to perform a READ/WRITE operation (ii) For Non-RAM time taken to position the READ-WRITE mechanism (head) at the desired location - Memory Cycle Time time taken consisting of access time + additional time required before a 2nd access can be started

Terms for Computer Memory Systems Performance - Transfer Rate  Rate at which data can be transferred into/out of a memory unit (i) For RAM: 1/Cycle Time (ii) For Non-RAM: TN = TA + N/R Physical Type: Semiconductor(RAM)/Magnetic(Disk/Tape)/Optical(CD/DVD) and Magneto-Optical(Hologram) Physical Characteristics - Volatile: info is lost when power is switched off (eg. RAM) - Nonvolatile: info remains even when there is no power supply (eg. Harddisk) N: No of bits R: Transfer Rate TN: Avg time to read/write N bits TA: Avg Access Time

Terms for Computer Memory Systems Physical Characteristics (continue) - Non-erasable memory: cannot be altered (eg. ROM) Organisation - Physical arrangement of bits into words - Not always obvious - e.g. interleaved

Cache Memory Principles
Cache memory is intended to give memory speed Cache contains a copy of portions of main memory

Cache operation - overview
CPU requests contents of memory location Check cache for this data If present, get from cache (fast)  Cache Hit If not present, read required block from main memory to cache  Cache Miss Then deliver from cache to CPU Cache includes tags to identify which block of main memory is in each cache slot

Cache/Main Memory Structure
M: Blocks C: Lines M = 2n/K which particular block is being stored Tag: portion of memory address C << M

Typical Cache Organization

Cache Design - Elements
Cache Size: desired size Mapping Function Replacement Algorithm Write Policy Block/Line Size Number of Caches

Size does matter Cost small enough ≈ cost per bits (memory)
Large enough ≈ access time (cache time) More cache is expensive Speed More cache is faster (up to a point) Checking cache for data takes time

Mapping Function To map main memory blocks into cache lines
To determine which main memory blocks occupies a cache line (1) Direct Mapping In a cache system, direct mapping maps each block of main memory into only one possible cache line (2) Associative Mapping Associative mapping permits each main memory block to be loaded into any line of the cache (3) Set-Associative Mapping In set-associative mapping, he cache is divided into a number of sets of cache lines; each main memory block can be mapped into any line in a particular set.

Direct Mapping Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place Address is in two parts Least Significant w bits identify unique word Most Significant s bits specify one memory block The MSBs are split into a cache line field r and a tag of s-r (most significant)

Direct Mapping Address Structure
Tag s-r Line or Slot r Word w 14 2 8 24 bit address 2 bit word identifier (4 byte block) 22 bit block identifier 8 bit tag (=22-14) 14 bit slot or line: an index into the cache to access a particular line No two blocks in the same line have the same Tag field Check contents of cache by finding line and checking Tag

Direct Mapping Cache Line Table
Cache line Main Memory blocks held 0 0, m, 2m, 3m…2s-m 1 1,m+1, 2m+1…2s-m+1 m m,2m,3m... 2s m-1 m-1, 2m-1,3m-1…2s-1 Eg: m=16K=214 , ,..., FF0000 , ,..., FF0004 FFFC, 01FFFC,..., FFFFFC (214 = ≈ 16K) +1 +m +m-1 Line + Word Tag No.

Direct Mapping Cache Organization

Direct Mapping Example
Line+Word = 339C (Hex) C Line = 14 bits 0 C E 7 M:339C C:0CE7

Direct Mapping pros & cons
Simple and Inexpensive to implement Fixed location for given block If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high

Associative Mapping Solve disadvantage of direct mapping by permitting each memory block to be loaded into any line of cache Memory address is interpreted as tag and word To determine if a block is in the cache, cache control logic simultaneously examine every line’s tag for a match - Tag uniquely identifies block of memory Tag: formed by taking the Leftmost 22 bits of the address

Associative Mapping Address Structure
Word 2 bit Tag 22 bit 22 bit tag stored with each 32 bit block of data Compare tag field with tag entry in cache to check for hit Least significant 2 bits of address identify which 16 bit word is required from 32 bit data block e.g. Address Tag Data Cache line FFFFFC FFFFFC FFF

Associative Mapping Eg: How to find the tag from memory address
F F F F F (Hex) (Binary) (Binary) F F F F D (Hex) Cache Memory

Fully Associative Cache Organization

Associative Mapping Example
Memory Address = 16339C (Hex) C Tag = 22 leftmost bits C E 7

Set Associative Mapping
Cache is divided into a number of sets Each set contains a number of lines A given block maps to any line in a given set e.g. Block B can be in any line of set i (mapping of blocks into lines) e.g. 2 lines per set 2 way associative mapping A given block can be in one of 2 lines in only one set

Set Associative Mapping Address Structure
Word 2 bit Tag 9 bit Set 13 bit Use set field to determine cache set to look in Compare tag field to see if we have a hit e.g Address Tag Data Set number 1FF 7FFC 1FF FFF 001 7FFC FFF

Set Associative Mapping Example ①
13 bit set number Block number in main memory is modulo 213 000000, 00A000, 00B000, 00C000 … map to same set (memory map into cache set 0)

Two Way Set Associative Cache Organization

Two Way Set Associative Mapping Example
Set+Word = 339C (Hex) C Set = 13 bits 0 C E 7

Set Associative Mapping Example ②
A two-way set of associate cache has lines of 16 bytes and a total size of 8 kilobytes. The 64-Megabyte main memory is byte addressable. Show the format of main memory address. Tag Set (d) Word (w) s Tag + Set + Word = Total Memory Address, x Given: Memory = 64 MB and Cache = 16 Bytes Total Memory Address, x  2x = 64 MB  x = 26 Number of Blocks = 64 MB/16 Bytes = 4 MB So, 2s = 4 MB  s = 22 (s = tag + set)

Set Associative Mapping Example ②
A two-way set of associate cache has lines of 16 bytes and a total size of 8 kilobytes. The 64-Megabyte main memory is byte addressable. Show the format of main memory address. Tag = 14 Set (d) = 8 Word (w) = 4 s Word, w = x – s = 26 – 22 = 4 bits Total cache lines = 8 KB/16 Bytes = 512 Bytes Since this is a 2-way set associative addressing, 512/2 = 256 Bytes 2d = 256  d = 8 bits Tag = s – d = 22 – 8 = 14 bits

Set Associative Mapping Summary
Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2d Number of lines in set = k Number of sets = v = 2d Number of lines in cache = kv = k * 2d Size of tag = (s – d) bits

Replacement Algorithms
For direct mapping - No choice; Each block only maps to one line  Replace that line For associative and set-associative mapping, replacement algorithm is required when cache has been filled and new block is brought into the cache 4 common algorithm: Least Recently Used (LRU): replace blocks that has been the longest in the cache without reference to it First-In-First-Out (FIFO): replace blocks that has been in the cache longest Least Frequently Used (LFU): replace block that has the fewest references Random: to pick a line at random

Write Policy Must not overwrite a cache block unless main memory is up to date (required when old block is to be changed) Multiple CPUs may have individual caches I/O may address main memory directly

④-a: Write through All writes go to main memory as well as cache
Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date Lots of traffic Slows down writes Remember bogus write through caches!

④-b: Write back Updates initially made in cache only
Update bit for cache slot is set when update occurs If block is to be replaced, write to main memory only if update bit is set Other caches get out of sync I/O must access main memory through cache N.B. 15% of memory references are writes

⑤ Block/Line Size When blocks are placed in cache, blocks size increase and hit ratio increase Due to Principle of Locality: says that the data in the vicinity of a referenced word are likely to be referenced in near future Hit ratio decreases as blocks becomes larger thus reduces no of blocks that fit into cache and also additional word are less likely to be needed

⑥ Number of Caches Multilevel: L1, L2, L3 Unified vs. Split Caches
Unified: single cache for data and instructions Split Caches: different cache for data and instructions eg. Pentium and PowerPC

Internal Memory Semiconductor Main Memory Subsystems
 ROM/DRAM/SRAM memories Organization Basic element of a semiconductor memory  memory cell Properties of Memory Cells: ①It has 2 stable states to represent 0 and 1 ②Capable of being written into to set the state ③Capable of being read to sense the state Cell has 3 terminals capable of carrying electrical signal

Internal Memory Cell has 3 terminals capable of carrying electrical signal i. Select terminal: selects a memory cell for a read/write operation ii. Control terminal: indicates Read/Write iii. Other terminal: (a) reading: output of cell’s state (b) writing: provide electrical signal that sets the state of cell to 0 or 1

Memory Cell Operation

Internal Memory Earlier computer has a main memory using doughnut-shaped ferromagnetic loops  cores Replaced in the 1970s by semiconducting memory Semiconductor Memory Types All memory types  Random access (individual words of a memory are directly accessed

Semiconductor Memory – (A) RAM
Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic

Dynamic RAM Storage cell is essentially a transistor acting as a capacitor Capacitor charge dissipates over time causing a 1 to change to a 0 Cells must be refreshed periodically even when powered Very high packaging density (essentially analogue device) Charges leak Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory

Dynamic RAM Structure Operation:
Address line active when bit read or written (transistor  On/Off Switch) -Transistor switch closed (current flows) Write Voltage signal is applied to bit line (High Voltage = 1; Low Voltage = 0) Then signal is applied to the address line allowing transfer of charge to capacitor Read -When the Address Line is selected, transistor turns on then, the Charge from capacitor is fed via bit line to sense amplifier (to compare with reference value to determine 0 or 1) -This readout process discharges the Capacitor and this charge must be restored to complete the operation

Static RAM Binary values are stored using flip-flop storage cells
Uses 5-10x more transistors Faster than a dynamic cell Does not need refresh circuits; No charge to leak More complex construction Larger per bit More expensive Cache

Static RAM Structure Operation:
Transistor arrangement gives stable logic state State 1 -C1 high, C2 low -T1, T4  off, T2, T3  on State 0 -C2 high, C1 low -T2, T3  off, T1, T4  on Address Line transistors T5 and T6 is switch on when a signal is applied to address line When a signal is applied to the address line, transistors  on (allow read or write operation) Write – apply desired value to B and compliment to B  forces the 4 transistors into proper state Read – bit value is read from line B

SRAM vs DRAM Both volatile Power needed to preserve data Dynamic cell
Simpler to build, smaller More dense Less expensive Needs refresh circuits (capacitor discharging) Use for main memory Static Faster Use for cache memory

(B) Read Only Memory (ROM)
Permanent data storage - Nonvolatile Writing during manufacture so it is very expensive for small number of ROMs Programmable ROM (PROM) -Data can be written once by the user employing a PROM programmer -Useful for small production runs Read ‘mostly’ memory (read is more than write operation): EPROM, EEPROM, and Flash memory Erasable PROM (EPROM) -Programming is similar to a PROM -Can be erased by exposing to UV light -More expensive than PROM

(B) Read Only Memory (ROM)
Electrically Erasable PROM (EEPROM) -Can be written many times without erasing existing content in the EEPROM -Takes much longer to write than read -More expensive than EPROM Flash memory -Similar to EEPROM in using electrical erase -Fast erasures, block erasures -Higher density than EEPROM -Price: intermediate between EPRON and EEPROM

Organisation in detail (Chip Logic)
Each memory chip contains a number of 1-bit cells eg. 1, 4, and 16 million cell chips are common Cells can be arranged as 4Mx1 [4M of 1 bit word] or in multiple bits per address location (eg. 1Mx4 [4 lots of 1Mbit chip with bit 1 of each word in chip 1 etc.]) To reduce pin count, address lines can be multiplexed with data and/or as high and low halves Typical control lines -WE (write enable), OE (output enable) for write and read operations RAS, CAS (row and column address selects) to provide timing to the chip

Typical 16 Mb DRAM (4M x 4)

Refreshing Disable the DRAM chip when refreshing
Refresh counter steps through all the row values For each row, output lines from the refresh counter are supplied to the row decoder and the RAS line is activated The data are read out and written back into the same location (cell is refreshed)

Packaging Address for 1M (220 = 1M); Address = 20 is the number of pins for the address (A0-A19) Data lines to read data = 8 lines (D0-D7) Power Supply Pin (Vcc) Ground Pin (Vss)

Packaging CE (Chip Enable) = to indicate whether the address is valid for this chip since there are many memory chips Program Voltage (Vpp) = supplied during programming NC (no connect) = to have an even number of pins

Module Organization Address = 18 bit Output = 8 bit

256kByte (256Kx8) memory from 256x1 chips
Module Organization Address = 18 bit Output = 8 bit 256kByte (256Kx8) memory from 256x1 chips 218 = 256K (address = 18-bit address) The address is presented to 8 numbers of 256K x 1-bit chip Each 256K x 1-bit chip provides the input/output of 1 bit

Error Correction A semiconductor memory is subjected to errors
The errors are divided into: Hard Failure Permanent defect Soft Error Random, non-destructive No permanent damage to memory Detected using Hamming error correcting code = Hamming Code

Hamming Error-Correcting Code
Venn Diagram – error-correcting code on 4-bit words Assign the words to the inner compartments Parity Bit – Even Number of Ones (1s) in each circle for remaining compartments 1 A B C By checking the parity bits, the disagreement are found in A and C  correction Error changes on of the data bits

Error Correcting Code Function
(c) Error detected & cannot be corrected (a) No errors (b) Error detected & corrected Calculation new calculation No errors. Fetched data is sent out Error detected and possible to correct error. Data bits + Error Correction Bits is sent to the Corrector to produce a corrected set of data Error detected and not possible to correct. Report it. Data in – when data is read into Memory A calculation (shown as f) is performed on data to produce a code, of length K bits Both M bits data and K bits code are stored Data out – when stored data is read out from Memory A new set of K bits code is generated from the data to be read out Comparison between the new K bits code and the stored K bits code gives the following results:

Advanced DRAM Organization
Enhancements on the DRAM architecture have been explored and some of the products are SDRAM, RDRAM and DDR-SDRAM

Synchronous DRAM (SDRAM)
Exchanges of data with processor is synchronized with an external clock Processor presents address to RAM, then RAM finds data (CPU) waits in conventional DRAM Since SDRAM moves data in time with system clock, CPU knows when data will be ready, CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) to the processor

RAMBUS DRAM (RDRAM) Adopted by Intel for Pentium & Itanium
Main competitor to SDRAM Vertical package – all pins on one side Asynchronous block protocol After an initial 480ns access time, Then 1.6 Gbps is produced

Double Data Rate SDRAM (DDR-SDRAM)
SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle (Rising edge and Failing edge)

Cache DRAM (CDRAM) Developed by Mitsubishi
Integrates small SRAM cache (16 kb) onto generic DRAM chip Methods of Applications Used as true cache consisting of 64-bit lines -Effective for ordinary random access To support serial access of block of data -Eg. Refresh bit-mapped screen -CDRAM can prefetch data from DRAM into SRAM buffer -Subsequently accesses solely SRAM

External Memory Types of External Memory Magnetic Disk RAID Removable
Optical CD-ROM CD-Recordable (CD-R) CD-R/W DVD Magnetic Tape

(A) Magnetic Disk The disk is a metal or plastic platter coated with magnetizable material Data is recorded onto and later read from the disk using a conducting coil, the headD Now glass Improved surface uniformity Increases reliability Reduction in surface defects Reduced read/write errors Lower flight heights (See later) Better stiffness Better shock/damage resistance

Read and Write Mechanisms
During read/write, head is stationary, platter rotates Write Current flowing through a coil produces a magnetic field Electric pulses are sent to the write head and the resulting magnetic pattern recorded on surface below Read (traditional) Magnetic field moving relative to coil produces current (when the surface of the disk passes under the head, it generates a current of the same polarity as the one recorded) Head/Coil is the same for read and write eg. Floppy Disk Read (modern) Separate read head, but positioned close to the write head Read Head  Partially shielded magneto resistive (MR) sensor MR material has an electrical resistance that depends on direction of magnetic field moving under it (by passing a current through the MR sensor, resistance changes are detected as voltage signals) MR design allows high frequency operation (means higher storage density and speed)

Inductive Write MR Read

Data Organization and Formatting
Data is organized into concentric rings or tracks, on the platter Tracks are separated by gaps Disk rotates at a constant speed – constant angular velocity Number of data bits per track is a constant Data density is higher on the inner tracks Logical data transfer unit is the sector Sectors are identified on each track during the formatting process

Disk Data Layout

Disk Velocity To allow the head to read all bits with at the same rate: Rotate disk at constant angular velocity (CAV) Advantages individual blocks can be addressed by track and sector Disadvantages Amount of data that can be stored in the long outer track is the same as the short inner track To increase storage density of the disk: Multiple Zone Recording (more complex circuit) Within a zone, the number of bits per track is same Zones farther from center contains more sector (more bits) than the one near the center

Disk Layout Methods Diagram

Characteristics Single vs. Multiple platters per drive (each platter has its own read/write head) Fixed (rare) vs. movable head  Fixed head has a head per track (rare today); multiple heads  Movable head uses one head per platter (one per surface); 1 head Removable vs. Fixed platters  Removable platter can be removed from disk drive for storage of transfer to another machine  Fixed platter mounted in the disk drive eg. Hard disk of PC Single sided disk (only one side has magnetizable coating)

Multiple Platters Component of a Disk Drive (Multiple Platter)

Characteristics Data accessing times (Disk Performance Parameters)
 Seek time – position the head over the correct track  Rotational latency – wait for the desired sector to come under the head  Access time – seek time plus rotational latency  Block transfer time – time to read the block (sector) off of the disk and transfer it to main memory

Speed Access Time = ① + ②

Winchester Hard Disk Developed by IBM in Winchester (USA)
One or more platters (disks) Very small head to disk gap (operate closer to the disk’s surface)

RAID Redundant Array of Independent Disks
 A family of techniques for using multiple disks as a parallel array of data storage devices with redundancy built in to compensate for disk failure eg. Servers or Larger System Set of physical disks viewed as single logical drive by O/S Data distributed across the physical drives of the array Seven levels: 0 – 6 levels

RAID 0 No redundancy techniques are used
Data is distributed over all diskd in the array Data is divided into strips for actual storage Can be used to support high data transfer rates by having block transfer size be in multiples of the strip Can support low response time by having the block transfer size equal a strip – support multiple strip transfers in parallel

Data Mapping For RAID 0

RAID 1 All disks are mirrored – duplicate
- Data is stored on a disk and its mirror - Read from either the disk or its mirror - Write must be done to both the disk and mirror Fault recovery is easy – use the data on the mirror System is expensive

RAID 2 All disks are used for every access – disks are synchronized together (parallel access) Data strips are small (byte) Error correcting code computed across all disks and stored on additional disks (REDUNDANCY through HAMMING Code) Uses fewer disks than RAID 1 but still expensive Number of additional disks is proportional to log of number of data disks * RAID 2 & 3: make use of the parallel access technique

RAID 3 Similar to RAID 2 however
Only one single redundant disk is used, no matter how large the array – the parity drive Parity bit is computed for the set of individual bits in the same position on all disks If a drive fails, parity information on the redundant disks can be used to calculate the data from the failed disk “on the fly” (easily)

RAID 4 Access is to individual strips rather than to all disks at once (RAID 3) Bit-by-bit parity is calculated across corresponding strips on each disk Parity bits stored in the redundant disk. Write penalty For every write to a strip, the parity strip must also be recalculated and written Thus 1 logical write equals 2 physical disk accesses The parity drive is always written to and can thus be a bottleneck *RAID46: use the Independent Access Technique

RAID 5 Parity information is distributed on data disks in a round-robin scheme (parity strips on a different disk) No parity disk needed

RAID 6 Two parity calculations
Stored in separate blocks on different disks User requirement of N disks needs N+2 High data availability Three disks need to fail for data loss Significant write penalty (write to 2 parity blocks)

RAID 0, 1, 2

RAID 3 & 4

RAID 5 & 6

Optical Storage CD-ROM
Advent of CDs in the early 1980s revolutionized the audio and computer industries Basic operation CD is operated using constant linear velocity (rotate the disk at a variable speed) Essentially one long track spiraled onto the disk Track passes under the disk’s head at a constant rate – requires the disk to change rotational speed based on what part of the track you are on To write to the disk, a laser is used to burn pits into the track During reads, a low power laser illuminates the track and its pits

DVD Digital Versatile Disk - Used to indicate a computer drive
Will read computer disks and play video disks In the track, pits reflect light differently than no pits thus allowing you to store 1s and 0s Master disk is made using the laser Master is used to “press” copies in a mass production mechanical style Cheaper than production of information on magnetic disks  Storage capacity roughly 682 MB (CD) & 17 GB (DVD)  Transfer rate standard is 176 MB/second  Only economical for production of large quantities of disks  Disks are removable and thus archival  Slower than magnetic disks

WORMs; Write Once, Read Many Disks
User can produce CD ROMs in limited quantities Specially prepared disk is written to using a medium power laser Can be read many times just like normal CD ROM Permits archival storage of user information, distribution of large amounts of information by a user Erasable optical disk Combines laser and magnetic technology to permit information storage Laser heats an area that can then have an efield orientation changed to alter information storage (write) “State of the efield” can be detected using polarized light during reads

Magnetic Tape The first kind of secondary memory Still widely used
Very cheap Very slow Sequential access Data is organized as records with physical air gaps between records One wordsis stored across the width of the tape and read using multiple read/write heads

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