VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES

VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES
Sreenivasa Rao CH Department of Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad Web: VLSI Design 21/01/2009 VLSI Design

Bi Polar Transistor Review MOSFETs Review Bi CMOS
Out Line Bi Polar Transistor Review MOSFETs Review Bi CMOS VLSI Design

Two Types of Bipolar Transistors
Physical structure p n Emitter Collector Base B C E PNP transistor Schematic symbol NPN transistor Figure 3.10 VLSI DesignBiCMOS Technology

NPN Bipolar Transistor
n-epi p n + P-substrate Electron flow n+ buried layer p+ SiO2 Al•Cu•Si Base Collector Emitter VLSI DesignBiCMOS Technology

VLSI DesignBiCMOS Technology
NPN Bipolar Biasing Lamp 1.5 V n p S1 B C E 3 V Nonconduction mode Conduction mode Electron flow e- h+ Figure 3.11 VLSI DesignBiCMOS Technology

PNP Bipolar Biasing Nonconduction mode 1.5 V p n S1 B C E 3 V Lamp Conduction mode Hole flow h+ e- Figure 3.12 VLSI DesignBiCMOS Technology

Parasitic Capacitance in Transistors
D G p- Substrate oxide doped poly MOS transistor Bipolar junction transistor p C E B VLSI DesignBiCMOS Technology

Cross Section of an NPN Bipolar
p- substrate n+ p Metal contact C E B Figure 3.13 VLSI DesignBiCMOS Technology

Cross Section of Parasitic Resistances in a Bipolar Transistor
REC REB RBB RBC RCC RCB Metal contact resistance Bulk resistance n+ p- Base Emitter Collector p- Substrate Figure 3.2 VLSI DesignBiCMOS Technology

BIPOLAR ICs VLSI DesignBiCMOS Technology

11 VLSI DesignBiCMOS Technology

NMOS Device + “Metal” Gate SiO 2 Source Drain p-Si n V D G > V T > 0 Electron flow Positive charges Negative charges No current = 0 > 0 VLSI DesignBiCMOS Technology

PMOS Device + “Metal” Gate SiO 2 Source Drain n-Si p V D > 0 G < V T < 0 Hole flow Positive charges Negative charges No current = 0 SiO VLSI DesignBiCMOS Technology

Biasing Circuit for an NMOS Transistor

NMOS Transistor in Conduction Mode, Characteristics Curves of an N-channel MOSFET 15 VLSI DesignBiCMOS Technology

Biasing Circuit for a P-Channel MOSFET

PMOS Transistor in Conduction Mode

MOS Market dominates worldwide chip sales (>75%) Total MOS sales 2003/2004 ~ $250 billion Illustrates strength of CMOS technology - feature sizes now < 0.1um True system-level integration on a chip i.e. converters, filters, dsp processors, microcontroller cores, memory all reside on one die >180 million transistors/chip Decreases in feature size cause some complexities: Layout issues more important Modeling is a key issue Parasitic effects significant Power dissipation issues challenging (BiCMOS, VDD-hopping, etc) VLSI DesignBiCMOS Technology

CMOS IC p-Si USG n-Si Balk Si Polysilicon STI n+ Source/Drain p+ Source/Drain Gate Oxide VLSI DesignBiCMOS Technology

CMOS Inverter 20 VLSI DesignBiCMOS Technology

CMOS Chip with 2 Metal Layers
Nitride PD2 PD1 Oxide Metal 2, Al·Cu·Si IMD USG dep/etch/dep Al·Cu·Si PMD BPSG LOCOS SiO2 n+ n+ p+ p+ p+ p+ N-well Poly Si Gate P-type substrate VLSI DesignBiCMOS Technology

CMOS Chip with 4 Metal Layers Lead-tin alloy bump Passivation 2, nitride Passivation 1, USG Metal 4 Copper Tantalum barrier layer FSG Metal 3 Copper FSG Nitride etch stop layer FSG Nitride seal layer Metal 2 Copper FSG Tungsten plug Tantalum barrier layer M 1 Cu Cu FSG FSG T/TiN barrier & adhesion layer Tungsten local Interconnection PSG Tungsten STI n + n + USG p + p + PMD nitride barrier layer P-well N-well P-epi VLSI DesignBiCMOS Technology P-wafer

Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually. VLSI DesignBiCMOS Technology

Low Power Slower BJT Faster High Power Core: CMOS, Interface: BJT VLSI DesignBiCMOS Technology

Mainly in 1990s CMOS as logic circuit Bipolar for input/output Faster than CMOS Higher power consumption Likely will have problem when power supply voltage dropping below one volt VLSI DesignBiCMOS Technology

A known deficiency of MOS technology is its limited load driving capabilities (due to limited current sourcing and sinking abilities of pMOS and nMOS transistors. Bipolar transistors have higher gain better noise characteristics better high frequency characteristics BiCMOS gates can be an efficient way of speeding up VLSI circuits See table for comparison between CMOS and BiCMOS CMOS fabrication process can be extended for BiCMOS Example Applications CMOS - Logic BiCMOS - I/O and driver circuits ECL - critical high speed parts of the system VLSI DesignBiCMOS Technology

Low Power + High Speed=BiCMOS
Future of Gigascale Integration lies in BiCMOS technology Application Example : Wireless Communications - pagers, cellular phones, laptops, palmtops Requirement for high speed low power front end challenge for analog designers (cannot afford time and energy to digitize first) Historical Roadmap: Bipolar/CMOS 1930’s – MOS invented, didn’t catch on, dormant for 30 yrs 1940’s- 50’s – Bipolars invented, became dominant thru the early 70’s 1970’s - Power consumption issues re-ignited interest in MOS 1980 MOS/Bipolar share of market 50/50 (largely due to CMOS) 1983 – BiCMOS invented 1990’s – CMOS dominant 2000’s - BiCMOS integrated into CMOS, Gigascale Integration VLSI DesignBiCMOS Technology

Characteristics of CMOS Technology Lower static power dissipation Higher noise margins Higher packing density – lower manufacturing cost per device High yield with large integrated complex functions High input impedance (low drive current) Scaleable threshold voltage High delay sensitivity to load (fan-out limitations) Low output drive current (issue when driving large capacitive loads) Low transconductance, where transconductance, gm  Vin Bi-directional capability (drain & source are interchangeable) A near ideal switching device Advantages of CMOS over bipolar Other CMOS Advantages VLSI DesignBiCMOS Technology

Characteristics of Bipolar Technology Advantages of Bipolar over CMOS Higher switching speed Higher current drive per unit area, higher gain Generally better noise performance and better high frequency characteristics Better analogue capability Improved I/O speed (particularly significant with the growing importance of package limitations in high speed systems). high power dissipation lower input impedance (high drive current) low voltage swing logic low packing density low delay sensitivity to load high gm (gm  Vin) high unity gain band width (ft) at low currents essentially unidirectional Other Bipolar Advantages VLSI DesignBiCMOS Technology

Combine advantages in BiCMOS Technology It follows that BiCMOS technology goes some way towards combining the virtues of both CMOS and Bipolar technologies Design uses CMOS gates along with bipolar totem-pole stage where driving of high capacitance loads is required Resulting benefits of BiCMOS technology over solely CMOS or solely bipolar : Improved speed over purely-CMOS technology Lower power dissipation than purely-bipolar technology (simplifying packaging and board requirements) Flexible I/Os (i.e., TTL, CMOS or ECL) – BiCMOS technology is well suited for I/O intensive applications ECL, TTL and CMOS input and output levels can easily be generated with no speed or tracking consequences high performance analogue Latchup immunity VLSI DesignBiCMOS Technology

Simple BiCMOS Inverter
section Bipolar INPUT OUTPUT Q1 Q2 Q3 Q4 Redrawn from H. Lin, J. Ho, R. Iyer, and K. Kwong, “Complementary MOS-Bipolar Transistor Structure,” IEEE Transactions Electron Devices, ED-16, 11 Nov. 1969, p VLSI DesignBiCMOS Technology

Basic BiCMOS Inverter Totem-Pole Configuration (Q1-Q2) Turn-off time VOH=VDD－VBE(ON) VOL=VBE(ON) 1 VLSI DesignBiCMOS Technology

BiCMOS Inverters =0V or = VDD =VBE(ON) or = VDD VBE(ON) VLSI DesignBiCMOS Technology

BiCMOS Inverter I Reduce Turn-off time “bleeder resistors” R1 and R2 are added VOH=VDD－VBE(ON) VOL=VBE(ON) VLSI DesignBiCMOS Technology

BiCMOS Inverter II Reduce Turn-off time VOH=VDD and VOL=0 VLSI DesignBiCMOS Technology

The simplified BiCMOS Inverter Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-type devices, OFF at Vin=0V) The MOS switches perform the logic function & bipolar transistors drive output loads Vin = 0 : T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to Vdd - Vbe (of T4) Note : Vbe (of T4) is base-emitter voltage of T4. (pullup bipolar transistor turns off as the output approaches 5V - Vbe (of T4)) Vin = Vdd : T2 is off. Therefore T4 is non-conducting. T1 is on and supplies current to the base of T3 T3 conducts & acts as a current sink to discharge load CL towards 0V. Vout falls to 0V+ VCEsat (of T3) Note : VCEsat (of T3) is saturation V from T3 collector to emitter Vout Vdd Vin T2 T4 T1 T3 CL VLSI DesignBiCMOS Technology

The simplified BiCMOS Inverter T3 & T4 present low impedances when turned on into saturation & load CL will be charged or discharged rapidly Output logic levels will be good & will be close to rail voltages since VCEsat is quite small & VBE  0.7V. Therefore, inverter has high noise margins Inverter has high input impedance, i.e., MOS gate input Inverter has low output impedance Inverter has high drive capability but occupies a relatively small area However, this is not a good arrangement to implement since no discharge path exists for current from the base of either bipolar transistor when it is being turned off, i.e., when Vin=Vdd, T2 is off and no conducting path to the base of T4 exists when Vin=0, T1 is off and no conducting path to the base of T3 exists This will slow down the action of the circuit Vout Vdd Vin T2 T4 T1 T3 CL VLSI DesignBiCMOS Technology

The conventional BiCMOS Inverter Two additional enhancement-type nMOS devices have been added (T5 and T6). These transistors provide discharge paths for transistor base currents during turn-off. Without T5, the output low voltage cannot fall below the base to emitter voltage VBE of T3. Vin = 0 : T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T5 is turned on & clamps base of T3 to GND. T3 is turned off. T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to Vdd - Vbe (of T4) · Vin = Vdd : T2 is off T1 is on and supplies current to the base of T3 T6 is turned on and clamps the base of T4 to GND. T4 is turned off. T3 conducts & acts as a current sink to discharge load CL towards 0V Vout falls to 0V+ VCEsat (of T3) Vdd Vin T2 T4 T6 Vout T1 T3 CL T5 VLSI DesignBiCMOS Technology

The conventional BiCMOS Inverter Again, this BiCMOS gate does not swing rail to rail. Hence some finite power is dissipated when driving another CMOS or BiCMOS gate. The leakage component of power dissipation can be reduced by varying the BiCMOS device parameters Vout Vdd Vin T2 T4 T1 T3 CL T6 T5 VLSI DesignBiCMOS Technology

More advanced BiCMOS structures Various types of BiCMOS gates have been devised to overcome the shortcomings of the conventional BiCMOS gate BiCMOS devices are available which provide the full Vdd -> GND voltage swing There is a common theme underlying all BiCMOS gates : all have a common basic structure of a MOSFET (p or n) driving a bipolar transistor (npn or pnp) which drives the output BiCMOS can provide applications with CMOS power & densities at speeds which were previously the exclusive domain of bipolar. This has been demonstrated in applications ranging from static RAMs to gate arrays to u-processors. BiCMOS fills the market niche between very high speed, but power hungry bipolar ECL (Emitter Coupled Logic) and very high density, medium speed CMOS VLSI DesignBiCMOS Technology

More advanced BiCMOS structures When the power budget is unconstrained, a bipolar technology optimised for speed will almost always be faster than BiCMOS and will most likely be selected. However, when a finite power budget exists, the ability to focus power where it is required usually allows BiCMOS speed performance to surpass that of bipolar The concept of ‘system on a chip’ becomes a reality with BiCMOS. Most gates in ROM, ALU, register subsystems etc do not have to drive large capacitive loads. Hence the use of BiCMOS technology would give no speed advantage. To take maximum advantage of available silicon technologies, the following mix of technologies in a silicon system might be used : CMOS for logic BiCMOS for I/O and driver circuits ECL for critical high speed parts of the system. VLSI DesignBiCMOS Technology

Comparison of logic families e.g., 74BCT have similar speeds to 74F but with greatly reduced power consumption VLSI DesignBiCMOS Technology

Further advantages of BiCMOS Technology Analogue amplifier design is facilitated and improved High impedance CMOS transistors may be used for the input circuitry while the remaining stages and output drivers are realised using bipolar transistors In general, BiCMOS devices offer many advantages where high load current sinking and sourcing is required. The high current gain of the NPN transistor greatly improves the output drive capability of a conventional CMOS device. MOS speed depends on device parameters such as saturation current and capacitance. These in turn depend on oxide thickness, substrate doping and channel length. Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple circuit and I/Os configurations possible greatly enhance design flexibility and can lead to reduced cycle time (i.e., faster circuits). [Peak bipolar speed is less dependent on circuit capacitance. Device parameters ft , Jk and Rb determine Bipolar circuit speed performance (not covered here) and depend on process parameters such as base width, epitaxial layer profile, emitter width and extrinsic base formation] VLSI DesignBiCMOS Technology

Further advantages of BiCMOS Technology BiCMOS is inherently robust with respect to temperature and process variations, resulting in less variability in final electrical parameters, resulting in higher yield, an important economic consideration. Large circuits can impose severe performance penalties due to simultaneously switching noise, internal clock skews and high nodal capacitances in critical paths - BiCMOS has demonstrated superiority over CMOS in all of these factors. BiCMOS can take advantage of any advances in CMOS and/or bipolar technology, greatly accelerating the learning curve normally associated with new technologies. VLSI DesignBiCMOS Technology

Are there disadvantages with BiCMOS technology ? Main disadvantage : greater process complexity compared to CMOS Results in a > 1.4 times increase in die costs over conventional CMOS. Taking into account packaging costs, the total manufacturing costs of supplying a BiCMOS chip ranges from 1.1-> 1.3 times that of CMOS. However, as CMOS complexity has increased, the percentage difference between CMOS and BiCMOS mask steps has decreased. Therefore, just as power dissipation constraints motivated the switch from nMOS to CMOS in the late ‘70s, performance requirements motivated a switch from CMOS to BiCMOS in the late ‘80s for VLSI products requiring the highest speed levels. Capital costs of investing in continually smaller (<1um) CMOS technology rises exponentially, while the requirement of low power supplies for sub-0.5um CMOS results in degradation of performance. Since BiCMOS does not have to be scaled as aggressively as CMOS, existing fabs can be utilised resulting in lower capital costs. Extra costs incurred in developing a BiCMOS technology is more than offset by the fact that the enhanced chip performance obtained extends the usefulness of manufacturing equipment & clean rooms by at least one technology generation. VLSI DesignBiCMOS Technology

BiCMOS - Brief Historical Perspective Most early BiCMOS applications were analogue; BiCMOS operational amplifiers were introduced in the mid-70s followed by BiCMOS power ICs. Digital LSI BiCMOS devices were introduced in the mid-80s, motivated by high power dissipation of bipolar circuits, speed limitations of MOS circuits & a need for high I/O throughput. Development of VLSI BiCMOS resulted in very high performance memories, gate arrays & micro-processors BiCMOS follows the same scaling curve as mainstream CMOS technology resulting in explosive growth in BiCMOS product growth. BiCMOS has been established as the technology of choice for high speed VLSI. VLSI DesignBiCMOS Technology

IC Fabrication Processes
VLSI DesignBiCMOS Technology

BiCMOS Fabrication Theoretically there should be little difficulty in extending CMOS fab processes to include bipolar as well as MOS transistors. In fact, a problem of p-well and n-well CMOS processing is that parasitic bipolar transistors are inadvertently formed as part of the outcome of fabrication (see section on CMOS latchup). Production of npn bipolar transistors with good performance characteristics can be achieved, e.g., by extending the standard n-well CMOS processing to include further masks to add two additional layers; the n+ subcollector and p+ base layers. The npn transistor is formed an n-well & the additional p+ base region is located in the well to form the p-base region of the transistor. The second additional layer, the buried n+ subcollector (BCCD) is added to reduce the n-well (collector) resistance & thus improve the quality of the bipolar transistor. VLSI DesignBiCMOS Technology

Arrangement of BiCMOS npn transistor (orbit 2um CMOS) for reference VLSI DesignBiCMOS Technology

Comparison between CMOS Technology and Bipolar Technology
Low Static power dissipation High input impedance Scalable threshold voltage Hign Noise margin High packing density Low gm (gm α Vin ) Low out put drive current High power dissipation Low Input Impedance Low volatage swing Logic Low packing density High gm (gm α eVin ) High Drive current High Speed High gain Low out put resistance VLSI DesignBiCMOS Technology

BiCMOS Processes CMOS + Bipolar VLSI DesignBiCMOS Technology

BiCMOS Processes CMOS + Bipolar
VLSI DesignBiCMOS Technology

BICMOS Logic BICMOS Logic is typically comprised of CMOS logic feeding a bipolar drive 2-input NAND is shown below N-tree pull down logic must be inserted twice: once in the actual CMOS logic circuit again in the base current path for the pull-down NPN transistor (N1 and N2) N3 holds the pull-down NPN off when the output is pulling high The circuit in (a) contains a VBE drop on the output up-level (VOH = VDD – VBE) VOL is a VCEsat which is a few hundred mV above ground Feedback provided by the inverter in (b) pulls output VOH all the way to VDD VLSI DesignBiCMOS Technology

Bipolar Logic Families
Table 3.1 58 VLSI DesignBiCMOS Technology

Why BiCMOS? Systems need CMOS for high density and low power digital functions Bipolar for RF and analog functions Integration for better systems Faster, smaller, lower power, more reliable Status: ALL major semiconductor companies either shipping or developing BiCMOS VLSI DesignBiCMOS Technology

Why Not BiCMOS? Cost, Cost, and Cost Process complexity Need to evaluate cost versus benefit Circuit design challenges: CMOS voltages scale (up to a point) Bipolar voltages do not scale VLSI DesignBiCMOS Technology

Complementary BiCMOS NPN PNP PMOS NMOS INDUCTOR No SOI fT of npn = 25 GHz fT of pnp = 2.5 GHz VLSI DesignBiCMOS Technology Source: NEC, 1998 IEDM

BiCMOS NAND Gate VLSI Design

BiCMOS NAND VLSI Design

BiCMOS Performance Self cap of CMOS leads to slow circuits
Bipolar transistor parasitics don’t scale as badly as CMOS But BiCMOS consumes more power VLSI Design

Technology Performance
Mixed-Signal Technology Performance SOI BiCMOS CMOS Time VLSI Design

BiCMOS NAND2 Gate VLSI Design

BiCMOS NOR VLSI Design

Problem Implement a BiCMOS NAND gate. VLSI Design

Solution E=AB+CD =((AB)’ (CD)’)’ VLSI Design

SOI Implementation of Bi-Polar Technology
VLSI Design

Integrated Circuit Products
Linear IC Products Operational Amplifier Voltage Regulator Stepper Motor Driver Digital IC Products Volatile Memory RAM DRAM SRAM MPU or CPU Digital IC Products (continued) Nonvolatile Memory ROM PROM EPROM EEPROM ASIC PLD PAL PLA MPGA FPGA VLSI Design 73

References Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, Cmos Digital Integrated Circuits Analysis And Design, Sung-mo Kang,Yusuf Leblebici VLSI Design

--Be Mentally Balanced, Disciplined, Systematic and maintain the burning desire to win the final till the last fraction of second…. VLSI Design

VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES

Similar presentations

Presentation on theme: "VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES

Similar presentations

Presentation on theme: "VLSI Design Bi CMOS UNIT II : BASIC ELECTRICAL PROPERTIES"— Presentation transcript:

Similar presentations

About project

Feedback