1. Virtual Memory User memory model so far:
Separate Instruction and Data memory
In reality they share the same memory space 0x …
User space
Instruction memory
Data memory
0x7fffffff

2. Virtual to Physical Address Mapping0x …
0x7fffffff
User space
Instruction
and Data
2 GB
Virtual
address
Physical
address
Physical
memory
Virtual memory 2 GB, HUGE amount
Physical memory only 16 MB

3. Address Mapping CP0 MIPS PIPELINE Instr Data 32 32 Physical memory
16 Mb
Arbiter
24-bit
Physical Address
32-bit Virtual Address

4. Virtual Address User 1 2 GB Virtual Address 32-bit 31 10 9 Page 0
Page 0
Page 1
Selects Page # x
Offset within
page #x ….
Page x
1024 Bytes
Page x
Page n 22 10
2 Pages
2 Addresses

5. Virtual Memory Virtual Address 2 GB Primary Memory Physical memory
16 MB
Page 0
Page 1
Page x ….
Page 1
Page x
Secondary Storage
Hard Disk 2 GB
Page n
Page 0
Not Allocated Yet

6. Memory Resident Pages Only very few pages are RESIDENT in physical 3110 9
Virtual 32-bit Address
Selects Page # x
Offset
Address Translation
of page #x 23 10 9
Physical 24-bit Address

7. Page Fault What about a NON RESIDENT page?
We know the Virtual Address, but:
No Physical Address, since the page is on Hard Disk (SWAPPED)
What about a not allocated page
We try to access a Virtual Address that we have not (yet) access to, that is an ERROR
In both cases we get a PAGE FAULT

8. Page Table Virtual Address 2 GB Page Resident Physical Memory Page x
Physical Addr [23:10]
Page x Y ….
Hard Disk
Page y N
Place on Hard Disk
Page y
For Non Resident Pages we get a PAGE FAULT

9. Swapping Virtual Address Physical Memory 2 Gb Resident …. Page y
Secondary Storage
Physical Addr [23:10]
Page y Y
Place on Hard Disk
Page y
The OS copies Page y to physical memory
and restarts the failing user instruction

10. Page Fault and the OS A Page Fault is handled by the Kernel (OS)
1) If physical memory not full
Copy the page from hard disk to a empty page X in physical memory
Update the Page Table, Resident = YES, Physical Addr [23:10]=X
Restart the failing instruction in the user program
2) If physical memory full
Choose one page X from physical memory, store it on hard disk at XX
Update the Page Table (X), Resident = NO, place on HD = XX
Proceed with 1)
What if page X is unchanged (only read operations), skip storing to hard disk, just set Resident = NO

11. Multiple User Processes
Virtual memory n * 2 Gb
Virtual
address
Physical
address
16 Mbyte 0x …
0x7fffffff
User 1
Page
Table 1
User n 0x …
0x7fffffff
User 2
Page
Table 2
User 1
HD address …. 0x …
0x7fffffff
User n
Page
Table n
User n
User 1
User 2
User 1
User 2

12. Where do we store the Page Tables?
We store the Page Tables in Kernel memory
Protected from User access!
16 Mbyte
User Memory
Dirty
Resident 22
Physical Addr [23:10]
2 entries
huge array!
Store only
allocated pages D R
Place on Hard Disk
Kernel Memory
Page
Table 1
Page
Table 2
Page
Table n

13. Address Mapping CP0 User Memory MIPS PIPELINE Instr Data 32 32 24-bit
Physical Address
32-bit Virtual Address
User process 2 running
Kernel Memory
Page
Table 1
Here we need
page table 2 for
address mapping
Page
Table 2
Page
Table n

14. Translation Lookaside Buffer (TLB)
CP0
On TLB hit, the 32-bit virtual address
is translated into a
24-bit physical address by hardware
We never call the Kernel!
User Memory
MIPS PIPELINE 32 32 24 D R
Physical Addr [23:10]
Virtual Address
Kernel Memory
Page
Table 1
Page
Table 2
Page
Table n

15. Memory Hierarchy Hardware is FAST but EXPENSIVE14
Hardware is FAST but EXPENSIVE
No need to use more than 2 entries
STILL TO BIG! Make is smaller.
Select a subset of the Page Table and store it in the TLB
16 Mb = 2 pages 14
User Memory
Valid bit 24 V
22-bit Page # D
Physical Addr [23:10]
Kernel Memory
Page Table 2

16. Address Translation A TLB hit, we get a physical address
The Page # found in TLB and Valid entry (V-bit)
If a Write operation, set Dirty (D-bit)
A TLB miss, causes a TLB miss exception
If Page NOT Resident in Physical memory,
Page Fault and the OS slide
if page X is swapped to hard disk and X in TLB, clear V bit
If Page Resident in Physical memory
Find a free TLB entry and update it
1) 22-bit Page #, set V-bit, clear D-bit, 14-bit physical address
If TLB full, chose a TLB entry
if D-bit, update Page Table Dirty bit, proceed with 1)

17. TLB control CP0 Control Signals TLB MISS R/W Page Table MIPS PIPELINE32
Data bus
Virtual Addr