1. Seyed Mohammad Seyedzadeh, Rakan Maddah, Alex Jones, Rami Melhem
PRES: A Pseudo-Random Encoding Scheme to Increase Bit Flip Reduction in the Memory*
Seyed Mohammad Seyedzadeh, Rakan Maddah, Alex Jones, Rami Melhem
Motivation
Background and Key Observation
Write minimization using a random base coset
Nonvolatile memory technologies such as Spin-Transfer Torque Random Access Memory (STT-RAM) and Phase Change Memory (PCM) are emerging as promising replacements to DRAM.
PCM and STT-RAM have a number of challenges that needs to be dealt with before deployment in functional systems.
PCM suffers from limited endurance
STT-RAM Suffers from high write bit error rate
Solution: Bit flip minimization
Service write requests while flipping as few bits as possible
Preserves PCM’s endurance and improves STT-RAM’s write reliability
Differential Write [1]:
Flip-N-Write (FNW) [2]:
Flip-Min [3,4]:
Step 1. Find the number of combinations with the weight w so that each combination has at least one element with weight w and at most 2k elements with weight w as follows: 
Old 1
Old 1
Old 1
New 1
New 1
New1 1
New 1
New2 1
Saves 2 bit flips
New3 1
Saves 3 bit flips
Step 2. Multiply outputs of Step 1 by the corresponding weights as follows: 
Saves 4 bit flips
We observe that increasing the number of encoded vector candidates decreases the number of bit flips required for “unbiased” data sets.
The effectiveness of techniques is directly correlated with the randomness of the elements that form the base coset.
We demonstrate mathematically and by simulation that random encoding outperforms the leading bit-minimization encoding approach based partially inverting bits of the current value.
Step 3. Calculate the average number of bits updated per write as follows:
Write minimization using FNW
PREM: Pseudo-Random Encoding Model
PRES: Pseudo-Random Encoding Scheme
The use of traditional pseudo-random number generator has a few difficulties such as irreversibility and the high hardware overhead.
To address these difficulties, we propose PRES, a novel tree-structure pseudo-random encoding model to generate pseudo-random vectors directly from the input value.
We first define a pseudo-random encoding model (PREM) to decorrelate a data block B as:
Given a memory block of size n and k auxiliary bits, the number of written bits (NWB) by FNW can be expressed as:
We create p different patterns by subdividing B into sub-blocks conceptually represented by the rows (or columns) of a two dimensional matrix.
PRES simultaneously and independently encode these sub-blocks using PREM in two opposite directions to generate two different pseudo-random codewords.
Bit Flip Reduction
( k=8 auxiliary bits) P0 P1
....
Pn-2
Pn-1
Encoder B0 B1
Bn-2
Bn-1
Decoder
Experimental Results
Table. The number of operations used in PRES, FlipMin and FNW
References:
[1] B. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-change technology and the future of main memory,” Micro, IEEE, 2010.
[2] S. Cho and H. Lee, “Flip-n-write: a simple determin- istic technique to improve pram write performance, energy and endurance,” in Microarchitecture, MICRO nd Annual IEEE/ACM International Symposium on. IEEE, 2009, pp. 347–357.
[3] A. N. Jacobvitz, R. Calderbank, and D. J. Sorin, “Coset coding to extend the lifetime of mem- ory,” in High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on. IEEE, 2013, pp. 222–233.
[4] A.N.Jacobvitz,R.Calderbank,andD.J.Sorin,“Writing cosets of a convolutional code to increase the life- time of flash memory,” in Communication, Control, and Computing (Allerton), th Annual Allerton Conference on. IEEE, 2012, pp. 308–318.
*This Paper has been accepted in 52st annual Design Automation Conference, San Francisco, CA, Jun 2015.
Scheme
PRES
FlipMin
FNW
Operation
XOR
AND
Encoder
n-bit Input, (n+k)-bit Output
n*(n+k)
(k+1)*(n+k)*2k
(n+k)*k*2k
n+k
n=32, k=4
1024
2880
2304 36
n=64, k=8
32768
165888
147456 72
Decoder
2*(n+k)
1152
144
4608
Bit Flip Reduction
( k=4 auxiliary bits)
Our measurements reveal that the data vectors generated by PRES, FlipMin and FNW pass
98.94%, 95.61% and 88.67% of NIST SP tests, respectively.
Those findings back our rationale that the higher the randomness of the base coset elements
the higher the rate of bit flip reduction that can be achieved.
Bit Flip Reduction
( k=8 auxiliary bits)