1. The Making of The Perfect MOSFET
Alan Elbanhawy
Fairchild Semiconductor
PESC June 21, 2006

2. Outline MOSFET Components Silicon Losses Packaging Related losses
Gate Driver Losses
Integration and Design Optimization
Conclusion

3. MOSFET Components Silicon Package Gate Driver Conduction Losses
Dynamic Losses
Distributed Parameters
Effects, Rg
Shoot Through
Reverse Recovery Losses
Price
Rise and Fall Times
Sink and Source Currents
Source Resistance
Parasitic Inductances
Thermal Resistance
Footprint
Price
Package
Parasitic Inductances
Parasitic Resistances
Skin Effect
Thermal Resistance
Footprint
Price

4. Optimum Range for RDS(ON)
Conduction Losses
Optimum Range for RDS(ON)
Optimum on Resistance RDS(ON) as a function of load current and input voltage for the top MOSFET
Power dissipation as a function of the on resistance RDS(ON) and the load current

5. Distributed and segmented parameters model
MOSFET Outlines
Gate lead

6. Effect of distributed Rg-Cgs and die current Density
The first and last segment currents for different combinations of Rg and Cgs
Gate voltage and drain currents at different Segments
Vgth
Uneven Power dissipation across the die during turn on!

7. Effect of Rg on Current Rise Time
Clearly tri = Rg*Cgs*Constant. This equation shows that the current rise time is directly proportional to Rg*Cgs which dictates that both parameters must be minimized for better performance
Current Fall time, tif
Current Rise time, tri

8. Effect of Rg on MOSFET Vds Rise and Fall Times
VDS Fall time
VDS Rise time

9. Lab Verification, tri, trv
Vds Rise time
Vds Rise time
Rg = 0 Ohm, Current Rise time
Rg=4.7 Ohm, Current rise time

10. Shoot Through in Synchronous Buck Converter
Conduction Losses
Dynamic Losses
Distributed Parameters
Effects, Rg
Shoot Through
Reverse Recovery Losses
Price

11. Distributed Parameters Model Solution, Voltages and Currents
Gate Threshold Voltage
Segments Currents
Gate-Source Voltage
Segments gate-source voltage
Segment Instantaneous Power

12. Distributed Rg Influence on Shoot Through Current
Drain Current
Gate threshold
Voltage
Gate-Source
Voltage

13. Distributed CGD Influence on Shoot Through Current
Drain current
Gate threshold voltage Vgth
Gate to source voltage

14. Distributed CGS Influence on Shoot Through Current
Drain Current
Gate threshold
Voltage
Gate-Source
Voltage

15. Lumped parameters Model with Parasitics
Full parasitic model
Added source and gate inductances only
Simple model

16. Loop Inductance Effects on Shoot Through

17. Loop Inductance Effects on Reverse Recovery
Loop Inductance 0nH – 10nH

18. Source Inductance Effects
Parasitics, Current
rise and fall times
Fall time as a function of the Source inductance Ls and Load Current IL
Vgth=1.5, gm=30
Parasitics, Current
sharing

19. Source Inductance Effects
Low Drain Current
High Drain Current
Fall time
Rise time
Power Dissipation

20. Parasitic Resistance and Skin Effect
The Fourier series for a square wave
for n=20 and n=200
Square wave Frequency Spectrum
Square wave synthesis

21. Package Effects, Parasitics and Skin Effects
BGA
Parasitic resistance as a function of frequency

22. Skin Effect and Power Loss for HS MOSFET
SO8 Package
Conduction loss (z-axes) as a function of the fundamental switching frequency f and the silicon on-resistance for an
The percentage error (z-axes) as a function of the switching frequency f and the silicon on-resistance for a
BGA 5 x 5.5 mm Package

23. Package Thermals
Power Ball Grid Array BGA package is an example of the modern packages to address all the requirements of high frequency and high power densities modern DC-DC converters
JC = 0.46 C/W
Heat sinking from the top of the
package
Very low footprint and profile

24. Gate Driver Influence on Losses
Rg = 2
Rg = 6
Uneven current distribution
Rg = 4
Rise Time
Rg = 6
Rg = 2
Optimum gate
Drive voltage
Rg = 4
Fall Time

25. Current as a function of L and time
Parasitic Drain Inductance Effects
Vdrain
Iind
Ls is PCB trace and package inductance, Cp is MOSFET Coss and stray capacitance
For tr & tf >> tres :
Overstress voltage =
Power Dissipation =
For 20A, 10nH, 1nF and 1MHz:
Overstress voltage = 60Volt
Power Dissipation =4W = 4
Current as a function of L and time

26. Gate Driver Influence on Losses
Why match MOSFETs and gate drivers?
Use one VRM board with three different drivers
All MOSFETs, Inductors and Filter capacitors are identical in all three cases
The very same PCB
The same test setup and test condition on an ATE
How will the efficiency curves be different?

27. Current Density (A/m^2) Current Density (A/m^2)
Integration and Design Optimization
Current Density (A/m^2)
Top MOSFET On
Current Density (A/m^2)
Bottom MOSFETs On

28. Conclusion
The pursuit of the perfect MOSFET must be launched simultaneously on three fronts, silicon, package and gate driver.
The optimization of the MOSFET parameters requires an extremely careful consideration of the individual parameter and its effect on all the loss mechanisms in a given power MOSFET and all of these in conjunction with each other and the effect of a given combination of these parameters on the overall performance of the device in the intended application which in our case is a synchronous buck converter

29. Thanks for your attention
Questions?