1. Chapter 4 Simplification of Boolean Functions Karnaugh Maps
Don’t Care Conditions
Technology Mapping
Optimization, Conversions, Decomposing, Retiming
Chapter 4
Karnaugh Maps
Don’t Care Conditions
Technology Mapping
Optimization, Conversions, Decomposing, Retiming

2. Boolean Cubes for n = 1, 2, 3, and 4
10 11
00 01
0 1
n = 1
n = 2
n = 3
Boolean Cubes for n = 1, 2, 3, and 4
n = 4

3. Boolean Functions and Boolean Cubes
Each Boolean n-cube represents a Boolean function of n variables
Each vertex represents a minterm
Each m-subcube represents 2m minterms, m < n, with the same n – m literals
Each m-subcube of 1-minterm represent a product of n – m literals
= l1l2…ln – m (x′n – m + 1 x′n – m + 2 … x′n + x′n – m + 1 x′n – m + 2 … xn + … + xn – m + 1 xn – m + 2 … xn)
= l1l2…ln – m
For any Boolean function a prime implicant is a subcube not contained in any other prime implicant
As essential prime implicant is a subcube that contains a 1-minterm that is not included in any other prime implicant
Boolean Functions and Boolean Cubes

4. Representation of Carry and Sum Functions with Boolean Cubesci xi yi
ci + 1 si 1
Carry Function ci + 1
Sum Function si
Representation of Carry and Sum Functions with Boolean Cubes
Truth Table

5. Map Representation (Karnaugh) maps define Boolean functions
Map representation is equivalent to truth tables, Boolean expressions and Boolean cube representation
Map aid in visually identifying prime implicants and essential prime implicants in each Boolean function
Maps are used for manual optimization of Boolean functions
Map Representation

6. Boolean Subcubes and Corresponding Karnaugh Maps for n = 1, 2, 3, and 4y m0 m1 m2 m3 x 1 x 1 1
n = 1
n = 2 zw m0 m1 m3 m2 m4 m5 m7 m6
m12
m13
m15
m14 m8 m9
m11
m10 00 01 11 10 xy 00 yz m0 m1 m3 m2 m4 m5 m7 m6 x 00 01 11 10 01
Boolean Subcubes and Corresponding Karnaugh Maps for n = 1, 2, 3, and 4 11 1 10
n = 3
n = 4

7. 2–variable Map Example: x y AND OR XOR 2–variable Map y y x x x′y′ x′y1 2 3 1 2 3 x 1 x 1
Subcube x′
x′y′
x′y
Subcube y 1
Subcube x
xy′ xy 1
Map Organization
Example of 1-subcubes
Example: x y
AND OR
XOR 1
2–variable Map
Truth Table y y y 1 2 3 1 2 3 1 2 3 x 1 x 1 x 1 1 1 1 1 1 1 1 1 1
AND OR
XOR

8. Three–variable Map yz x x′y′z′ x′y′z x′yz x′yz′ xy′z′ xy′z xyz xyz′ yz1 3 2 4 5 7 6 x 00 01 11 10
x′y′z′
x′y′z
x′yz
x′yz′ 1
xy′z′
xy′z
xyz
xyz′
Map Organization yz 1 3 2 4 5 7 6 x 00 01 11 10
Subcube z
Subcube z′ 1
Subcube x
Example of 2-subcubes yz 1 3 2 4 5 7 6
Three–variable Map x 00 01 11 10
Subcube x′y′
Subcube yz 1
Subcube xz′
Example of 1-subcubes

9. Map Representation of Carry and Sum Functionsci xi yi
ci + 1 si 1
xiyi
xiyi 1 3 2 4 5 7 6 1 3 2 4 5 7 6 ci 00 01 11 10 ci 00 01 11 10 1 1 1 1 1 1 1 1 1 1
Carry Function ci + 1
Sum Function si
Map Representation of Carry and Sum Functions
Truth Table

10. Four–variable Map zw xy zw zw xy xy Four–variable Map 00 01 11 10 001 3 2 4 5 7 6 12 13 15 14 8 9 11 10 xy 00 01 11 10 00
x′y′z′w′
x′y′z′w
x′y′zw
x′y′zw′ 01
x′yz′w′
x′yz′w
x′yzw
x′yzw′ 11
xyz′w′
xyz′w
xyzw
xyzw′ 10
xy′z′w′
xy′z′w
xy′zw
xy′zw′
Map Organization zw zw 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 xy 00 01 11 10 xy 00 01 11 10
Subcube y′w 00 00
Subcube x′
Four–variable Map 01
Subcube x′y 01
Subcube w′ 11 11
Subcube xz 10 10
Example of 2-subcubes
Example of 3-subcubes

11. Representation of Greater-than and Less-than Functions in Maps
y1y0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10
x1x0 00 01 11 10 00 x1 x0 y1 y0
Greater Than
Equal
Less Than 1 01 1
G = x1y1′ + x0y1′y0′ + x1x0y0′ 11 1 1 1 10 1 1
Greater-than Function
y1y0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10
x1x0 00 01 11 10 00 1 1 1
Representation of Greater-than and Less-than Functions in Maps 01 1 1
L = x1′ y1 + x1′x0′y0 + x0′y1y0 11 10 1
Truth Table
Less-than Function

12. Example of 3-subsubes and 4-subcubes
Five–variable Map
v = 0
v = 1 zw 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 xy 00 01 11 10 00 01 11 10 00
x′y′z′w′v′
x′y′z′wv′
x′y′zwv′
x′y′zw′v′ 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26
x′y′z′w′v
x′y′z′wv
x′y′zwv
x′y′zw′v 01
x′yz′w′v′
x′yz′wv′
x′yzwv′
x′yzw′v′
x′yz′w′v
x′yz′wv
x′yzwv
x′yzw′v 11
xyz′w′v′
xyz′wv′
xyzwv′
xyzw′v′
xyz′w′v
xyz′wv
xyzwv
xyzw′v 10
xy′z′w′v′
xy′z′wv′
xy′zwv′
xy′zw′v′
xy′z′w′v
xy′z′wv
xy′zwv
xy′zw′v
Map Organization
v = 0
v = 1 zw 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 xy 00 01 11 10 00 01 11 10 00 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 x′
Five–variable Map 01 vw 11 10
zw′
xz′
Example of 3-subsubes and 4-subcubes

13. Six–variable Map Six–variable Map v = 0 v = 1 v = 0 v = 1 zw zw xy xy1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 xy 00 01 11 10 00 01 11 10 xy 00 01 11 10 00 01 11 10 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 00 m0 m1 m3 m2
m16
m17
m19
m18 00 01 m4 m5 m7 m6
m20
m21
m23
m22 01
u = 1
u = 1 11
m12
m13
m15
m14
m28
m29
m31
m30 11
x′v 10 m8 m9
m11
m10
m24
m25
m27
m26 10 32 33 35 34 36 37 39 38 44 45 47 46 40 41 43 42
m32
m33
m35
m34 48 49 51 50 52 53 55 54 60 61 63 62 56 57 59 58 00
m48
m49
m51
m50 32 33 35 34 36 37 39 38 44 45 47 46 40 41 43 42 48 49 51 50 52 53 55 54 60 61 63 62 56 57 59 58 00 01
m36
m37
m39
m38
m42
m53
m55
m54 01 xz
u = 0
u = 0 11
m44
Six–variable Map
m45
m47
m46
m60
m61
m63
m62 11 10
m40
m41
m43
m42
m56
m57
m59
m58 10
Map Organization
z′w′
Example of 4-subcubes

14. Boolean Simplification with Map Method
Truth table, canonical form or standard form
Determine prime implicants
Generate map
Select essential prime implicants
Find minimal cover
Standard form
Boolean Simplification with Map Method

15. Boolean Simplification with Map Method
Example: Maps method
Problem: Using the map method, simplify the Boolean function
F = w′y′z′ + wz + xyz + w′y yz yz 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 wx 00 01 11 10 wx 00 01 11 10 00 1 1 1 00 1 1 1 01 1 1 1 01 1 1 1 11 1 1 11 1 1 10 1 1 10 1 1
Boolean Simplification with Map Method
Map Organization
Prime Implicants in the Map
PI List: w′z′, wz, yz, w′y
EPI List: w′z′, wz
Cover List: (1) w′z′, wz, yz
(2) w′z′, wz, w′y

16. Selection of Prime Implicants
Example: Selection of prime implicants
Problem: Simplify the Boolean function
F = w′x′yz′ + w′xy + wxz + wx′y′ + w′x′y′z′ yz 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 wx 00 01 11 10 00 1 1 01 1 1 11 1 1 10 1 1
Selection of Prime Implicants
PI List: w′x′z′, w′xy, wxz, wx′y′, x′y′z′, wy′z, xyz, w′yz′
EPI List: empty
Cover List: (1) w′x′z′, w′xy, wxz, wx′y′
(2) x′y′z′, wy′z, xyz, w′yz′

17. Don’t–Care Conditions
Completely specified functions have a value assigned for every minterm
Incompletely specified functions do not have values assigned for some minterms which are called don’t–care minterms (d–minterms) or don’t–care conditions
Don’t–care minterms can be assigned any value during simplifications in order to simplify Boolean expressions
Don’t–Care Conditions

18. Don’t–Care Conditions
Example: Don’t–care conditions
Problem: Derive Boolean expressions for the 9’s complement of a BCD digit
x1x0
x1x0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10
x3x2 00 01 11 10
x3x2 00 01 11 10
Digits
Nine’s Complements
Decimal
BCD x3 x2 x1 x0 y3 y2 y1 y0 9 1 8 2 7 3 6 4 5 00 1 1 00 1 1 01 01 1 1 11 X X X X 11 X X X X 10 X X 10 X X
y3 = x3′ x2′ x1′
y2 = x2  x1
x1x0
x1x0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10
x3x2 00 01 11 10
x3x2 00 01 11 10
Don’t–Care Conditions 00 1 1 00 1 1 01 1 1 01 1 1 11 X X X X 11 X X X X
Nine’s–Complement Table 10 X X 10 1 X X
y1 = x1
y0 = x0′
Map Representation

19. Technology Mapping for Gate Arrays
Gate arrays contain only one type of m-input gate (such as 3-input NOR, 3-input NAND)
Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type of gate
Technology mapping consist of three tasks
Conversion replaces each operator with an operator representing the gate function given in the gate array
Optimization eliminates unnecessary inverters
Decomposition replaces a n-input gate with an m-input gate available in the gate array
Technology Mapping for Gate Arrays

20. Conversion and Optimization
Rule 1:
Rule 2:
Rule 3:
Rule 4:
Conversion Rules
Rule 5:
Conversion and Optimization
Optimization Rules
Conversion Procedure:
Replace AND and OR gates with NAND or NOR gates by using Rules 1 – 4, and eliminate double inverters whenever possible

21. Translation of Standard Terms to NAND and NOR Schematics
Form Type
Standard Form Implementation
NAND Implementation
NOR Implementation
Sum of products
Product of sums
Translation of Standard Terms to NAND and NOR Schematics

22. Conversion to NAND (NOR) Gates
Example: Conversion to NAND (NOR) gates
Problem: Derive the NAND and NOR implementations of the carry function
2.4
1.4 xi xi
xiyi yi
2.4
2.8
ci + 1 yi
1.4
1.8
ci + 1 1 3 2 4 5 7 6 ci 00 01 11 10 ci ci 1
2.4
1.4 1 1 1 1
NAND Implementation
Map Definition Carry Function ci + 1
ci + 1 = xiyi+ xici + yici
ci + 1 = (xi + yi)(xi + ci)(yi + ci)
Conversion to NAND (NOR) Gates
2.4
1.4 xi xi
Standard Forms yi
2.4
2.8
ci + 1 yi
1.4
1.8
ci + 1 ci ci
2.4
1.4
NOR Implementation

23. Decomposition of 10–input AND Gate into 3–input AND Gates
2.4
2.4
2.4
2.4
2.4
2.4
Level Number
Number
of Inputs
Number of Gates 1 10
[10 / 3] = 3 2
3 + (10 – 3([10 / 3])) = 4
[4 / 3] = 1 3
1 + (4 – 3([4 / 3])) = 2
[2 / 3] = 1
2.4
2.4
Decomposition of 10–input AND Gate into 3–input AND Gates
Input and Gate Computation on Each Level
2.4
2.4
One Possible Decomposition
Alternative Decomposition

24. Technology Mapping for Gate Arrays
Example: Technology mapping for gate arrays
Problem: Implement the sum function using 3–input NAND gates ci xi yi ci xi yi si si
xiyi 1 3 2 4 5 7 6 ci 00 01 11 10 1 1
AND–OR Implementation
Conversion to NAND Network 1 1 1 ci xi yi ci xi yi
Map Definition Sum Function si
Technology Mapping for Gate Arrays si si
OR Gate Decomposition
Optimized NAND Network

25. Design Retiming Example: Design retiming
Problem: Implement 4–bit carry-look-ahead function c4 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0 using 3–input NAND gates g1 p3 p2 c4 p1 g0 p3 p2 p1 p0 c0
AND-OR Implementation g3 g3 p3 p3 g2 g2 p3 p3 p2 p2 g1 g1 p3 p3 p2 c4 p2 p1 p1 c4 g0 g0 p3 p3 p2 p2 p1 p1 p0 p0 c0 c0
Decomposition of AND-OR Implementation
Performance Optimized Decomposition g3
Design Retiming g3 p3 p3 g2
1.8
1.8
1.8 g2 p3 p3 p2 p2
1.8 g1
1.8 g1 p3 p3 p2
1.8
1.8 c4 p2
1.8 p1
1.8 p1
1.8
1.8 c4 g0 g0 p3 p3 p2 p2 p1
1.8 p1
1.8 p0
1.8 p0 c0 c0
1.8
NAND Implementation of Above
Delay = 8.2ns
Performance Optimized NAND Implementation
Delay = 6.4ns

26. Technology Mapping Procedure for Gate Arrays
Start
Convert
Decompose
Eliminate invertors
Retime
yes no
I/O
delay OK?
Done
Technology Mapping Procedure for Gate Arrays

27. Technology Mapping for Custom Libraries
Libraries contain gates with different functions and different delays
Technology mapping means covering schematic with library gates
Minimize delay on critical paths
Minimize cost on non-critical paths
Technology Mapping for Custom Libraries

28. Technology Mapping for Custom Libraries
Example: Technology mapping for custom libraries
Problem: Convert the expression w′ z′ + z(w + y) into a logic schematic using any of the gates defined in the digital logic gates, multiple-input gates, and complex gates libraries y
2.4 y
2.4
1.4
2.4 F
2.0 F w w
2.4 z z
AND–OR Implementation (Delay = 7.2ns, Cost = 28)
Alternative A (Delay = 5.4ns, Cost = 20) y y
1.4
1.4
2.0
1.4 F
1.4 F w
1.4 w z
1.4 z
Technology Mapping for Custom Libraries
NAND Implementation (Delay =5.2ns, Cost = 22)
Alternative B (Delay = 3.8ns, Cost = 20) B y A y
1.4
1.4
2.0
1.4 F
1.4 F w
1.4 w z
1.4 z
Two Possible Conversions
Cost Optimized Alternative B (Delay = 3.8ns, Cost = 18)

29. Conversion Procedure for Custom Libraries
Start
Convert to NAND schematic
Select a path
Select gate
Select a library component
Record replacement gain no no no
All paths considered?
All gates considered?
All components considered?
Recompute Delay
Select maximum gain replacement
yes
yes
Conversion Procedure for Custom Libraries
yes
Done

30. Chapter Summary Simplification of Boolean functions by
Map method (visual)
Technology mapping for gate arrays
Decomposition
Conversion
Optimization
Retiming
Technology mapping for custom libraries by schematic covering with complex gates with
Time optimization on circuit paths
Cost optimization on non-critical paths
Chapter Summary