1. SEE Single Event Effects Radiation Environment and its Effects in EEE Components and Hardness Assurance for Space Applications
César Boatella Polo (TEC-QEC)
ESA-CERN-SCC Workshop, CERN
09-10 May 2017

2. Single event effects in space environment
Heavy ions
Protons
Electrons

3. Historical facts
1975: [Binder] first reported “single event effect” SEE anomalies; unexpected triggering in bipolar digital circuits due to cosmic rays
1978 – 1985: SEUs in Pioneer 12 (Venus probe), in a 1024 bit PMOS shift register
: SEU example in the OBC of Spot1-2-3; Half of these SEUs lead to operational problems, including switching the satellite to safe mode.
[R. Ecoffet,
TNS ]

4. Outline SEE basic mechanisms Beam: LET, range, energy
Counting events, cross-section
Different types of SEEs
SEU, SET SEL SEB SEGR
New effects: MBUs, proton and electron direct ionization
Practical aspects of SEE testing
Checking the beam
PIN diode, SEU monitor, RPUM
Statistics, Uncertainties, Error Bars
Part-to-part variations

5. Outline SEE basic mechanisms Beam: LET, range, energy
Counting events, cross-section
Different types of SEEs
SEU SET SEL SEB SEGR
New effects: MBUs, proton and electron direct ionization
Practical aspects of SEE testing
Checking the beam
PIN diode, SEU monitor, RPUM
Statistics, Uncertainties, Error Bars
Part-to-part variations

6. SEE basic mechanisms
An accelerated charged particle looses energy along its path trough any material. This energy is absorbed via mainly Coulombian interactions and therefore charge is generated in the material. If the material is a semiconductor exposed to an electrical field, this charge can be collected by the semiconductor through various mechanisms (Funneling, Diffusion, Recombination). Depending on how much and where the charge is deposited and collected in an active electronic device, the normal behavior of the device can be significantly affected.

7. Both Heavy ions (Z2), protons can induce SEE
High energy proton
Most protons pass through the device with little effect
Heavy ion
electron or neutron
Each ion produces an ionizing track
A few protons (~10-5) cause nuclear reactions
Short range recoils produce ionization
Direct energy deposition
by the ion along the track.
Energy mainly deposited by fragments of nuclei, from
inelastic collision between a proton and a silicon nucleus.
The fragments usually deposit in turn all their energy along
their track or produce a cascade of particles.

8. Ion deposited charge: Linear Energy Transfer LET
[MeVcm2/mg]
Higher Energy => Lower LET
proton LET
In Silicon : r = 2.32 g/cm3
97 MeVcm2/mg= 1 pC/µm
[ECIF cocktail calculator,
Javanainen, Knyazheva et al.]
[J. F. Ziegler et al.,
Higher LET => Lower range
The amount of deposited charge is proportional to the energy loss of the incident particle which depends on the target material and on the incident particle.

9. Example of test facility: RADEF

10. Example of ion beam cocktail at RADEF

11. Charge collection by drift and diffusion
slower collection
by diffusion
fast collection by funneling (drift)
source
drain
Microbeam ions
Bulk NMOS
Multiple pulse amplitudes and shapes are measured depending on the ion strike location
[Ferlet-Cavrois, 2006]

12. The volume responsible for charge collection for a SEE (in μm3)
Sensitive Volume SV
The volume responsible for charge collection for a SEE (in μm3)
E, Z a b c
p+(E)
Recoil p n
Real sensitive volumes do not really have regular shapes and therefore, not only incidence angle but also pitch and roll may have an impact in the total amount of charge collected.
Heavy ion (Z>2)
High E proton

13. Why SEE testing? For SEE rate prediction
Need to know:
Space Environment: Integral flux as a function of LET or energy
Cross-section vs. ion LET or proton energy
Cross Section
Fluence
LET or Energy

14. SEE Cross Section Curve vs LET
The SEE cross section measures the probability for a SEE to occur Fit with Weibull (integral form) SEE cross-section is a crucial input for in-orbit SEE rate prediction.
W and S are fitting parameters
[Nparticules/cm2]
[cm2]

15. Outline SEE basic mechanisms Beam: LET, range, energy
Counting events, cross-section
Different types of SEEs
SEU, SET SEL SEB SEGR
New effects: MBUs, proton and electron direct ionization
Practical aspects of SEE testing
Checking the beam
PIN diode, SEU monitor, RPUM
Statistics, Uncertainties, Error Bars
Part-to-part variations

16. Some Classes of SEE
Soft Errors (no permanent damage)
SEU Single-Event Upset
MBU, MCU Multiple Bit (or Cell) Upset
ASET Analog Single Event Transient
DSET Digital Single Event Transient
SEFI Single Event Functional Interrupt
Hard Errors (permanent damage to device/circuit)
SEL Single-Event Latchup
SEHE Single-Event Hard Errors
SEDR Single-Event Dielectric Rupture
SEB Single-Event Burnout
SEGR Single-Event Gate Rupture
Destructive events
This is not a complete listing of all possible single-event effects!!

17. Single-Event Upset in SRAMs: The Feedback Mechanism
Race Condition
Recovery
VDD
Feedback
Ion Strike
i(t)
Recovery occurs before feedback:
No Upset
Feedback occurs before recovery:
Cell Upsets
LET = 45 MeV-cm2/mg
LET = 40.5 MeV-cm2/mg
LET = 9 MeV-cm2/mg
Threshold LET  42 MeV-cm2/mg
[J. R. Schwank, P. E. Dodd, 2001]
SEU is a circuit effect initiated at the device level.

18. Multiple Cell Upset (MCU)
40nm SRAM
Tilt=0, Roll=90,
Xenon, UCL
smaller cells => more MCUs
[ESTEC contract 18799/04/NL/AG
Hirex SEE test report, HRX/SEE/0288
STMicroelectronics 40nm SRAM]
One ion strike can induce more than 100 cell upsets
Low LETth on state of the art memories forces to use more complex EDAC algorithms / methods in order keep availability. Old hamming correction codes can be defeated by MCUs.

19. SEU sensitivity for low energy protons (1)
Memory Devices with very low LET thresholds are sensitive to proton-induced SEU set by direct ionization.
Bulk 65nm SRAM
[B. Sierawski, TNS 2009]
[H. Puchner, REDW 2011]
State of the art memories (Higly scaled devices) have very low LETth and can be prone to proton direct ionization.

20. SEU sensitivity for low energy protons (2)
Protons have a low LET and relative low penetration compared to heavier ions but can be very abundant depending on the orbit or during solar flares.
[SRIM]
[H. Puchner, REDW 2011]

21. SEU sensitivity for high energy electrons
28 nm
[Pellish 2013]
[Samaras 2014]
New highly integrated technologies may be sensitive to electron induced SEE. This could be an issue in Jupiter environment. Technology evolution may even lead to direct ionization by low energy electrons.

22. Single-Event Transients in Digital Logic Circuits (DSETs)
D-Latch
(sequential)
Inverters
(combinational)
Ion Strike
v(t)
[Buchner, TNS Dec.1997]
A strike on the inverter shortly before a clock edge can pass bogus data into the D-latch.

23. DSET propagation increases with frequency
D-Latch errors
Propagated SETs
from inverter strikes
[Buchner, 1997]
As clock edges come more frequently, the probability of a transient being captured and propagated to subsequent circuitry increases.
Trend in new technologies: combinatorial SET pulses are becoming larger than gate transition times and can propagate. Single event rates in combinatorial logic are becoming comparable to those in latches.

24. Example of DSETs measured at the output of a chain of logic cells
“Rail-to-rail” transients
Large variety of SET duration, depending on the ion strike location within the logic path
The modelling of SET propagation is layout dependant
New generation technologies are particularly prone to DSETs
130nm logic
[Ferlet-Cavrois07]

25. SET glitches in PLL built in ProASIC3 FPGA
Sample glitches
[A. Evans, iRoC Tech., IRPS 2015]
Micro-beam experiment
PLL sensitive region
Au ions, 144 µm × 144 µm

26. SETs in Complex Circuits
Cross section normalized per-gate
50 MHz operation
Significant variation (close 10x) depending on circuit function

27. Analog SET - ASET: Example in lm124
[Buchner, 2004]
The output signal displays different ASET shapes depending on the strike position,
May affect subsequent circuits if not well filtered in the design

28. ASET on a DC-DC converter
[Y. Ren et al, 2011]
The single event transient (SET) pulses on the internal reference voltages (band gap references) propagate to the soft start circuits which falsely triggers a short alert signal to the system. This results in a reset and thus an output power drop that will last the required time to discharge and charge the soft start capacitor.

29. SEFI, may appear in complex digital sequential devices, for example in SDRAM, CPU, ADC, DAC, FPGA, POL, memories …
Samsung 1Gbits DDR1 SDRAM
8-Gbits NAND-Flash, Samsung
[Hagen Schmidt, IDA, 2008]
SEFI is in fact a SEU in a critical register impacting the device’s functionality.
SEFI in a memory:
Rows, columns, blocks are in error;
Need reset or power cycling
Mitigated by decreasing the refresh time
SEU-MBU-SEFI-SEL:
Effect of die revision: x102 SEE rate
Lot-to-lot variations
[Ladbury 2006]

30. Single Event Latch-up, SEL
Integrated devices contain parasitic structures due to the proximity of their transistors.
An ion strike can trigger the PNPN parasitic structures present in CMOS devices,
This may create a low resistance path between power and ground.
Run-away current
What is the context in space appliciation
Thyristor
From Wikipedia, the free encyclopedia
Jump to: navigation, search
Circuit symbol for a thyristor
An SCR rated about 100 amperes, 1200 volts mounted on a heat sink - the two small wires are the gate trigger leads
The thyristor is a solid-state semiconductor device with four layers of alternating N and P-type material. They act as bistable switches, conducting when their gate receives a current pulse, and continue to conduct for as long as they are forward biased (that is, as long as the voltage across the device has not reversed).
Some sources define silicon controlled rectifiers and thyristors as synonymous[1].
Other sources define thyristors as larger set of devices with at least four layers of alternating N and P-type material, including: [2] [3]
silicon controlled rectifier
gate turn-off thyristor (GTO)
triode ac switch (TRIAC)
Static Induction Transistor/Thyristor (SIT/SITh)
MOS Controlled Thyristor (MCT)
Distributed Buffer - Gate Turn-off Thyristor (DB-GTO)
integrated gate commutated thyristor (IGCT)
MOS composite static induction thyristor/CSMT
reverse conducting thyristor
Contents
[hide]
Function
History
Applications
Comparisons to other devices
Failure modes
Silicon carbide thyristors
Types of thyristor
See also
Notes
Further reading
External links
[edit] Function
The thyristor is a four-layer semiconducting device, with each layer consisting of alternately N-type or P-type material, for example P-N-P-N. The main terminals, labeled anode and cathode, are across the full four layers, and the control terminal, called the gate, is attached to p-type material near to the cathode. (A variant called an SCS—Silicon Controlled Switch—brings all four layers out to terminals.) The operation of a thyristor can be understood in terms of a pair of tightly coupled Bipolar Junction Transistors, arranged to cause the self-latching action:
Thyristors have three states:
Reverse blocking mode — Voltage is applied in the direction that would be blocked by a diode
Forward blocking mode — Voltage is applied in the direction that would cause a diode to conduct, but the thyristor has not yet been triggered into conduction
Forward conducting mode — The thyristor has been triggered into conduction and will remain conducting until the forward current drops below a threshold value known as the "holding current"
[edit] Function of the gate terminal
The thyristor has three p-n junctions (serially named J1, J2, J3 from the anode).
Layer diagram of thyristor.
When the anode is at a positive potential VAK with respect to the cathode with no voltage applied at the gate, junctions J1 and J3 are forward biased, while junction J2 is reverse biased. As J2 is reverse biased, no conduction takes place (Off state). Now if VAK is increased beyond the breakdown voltage VBO of the thyristor, avalanche breakdown of J2 takes place and the thyristor starts conducting (On state).
If a positive potential VG is applied at the gate terminal with respect to the cathode, the breakdown of the junction J2 occurs at a lower value of VAK. By selecting an appropriate value of VG, the thyristor can be switched into the on state suddenly.
It should be noted that once avalanche breakdown has occurred, the thyristor continues to conduct, irrespective of the gate voltage, until both: (a) the potential VG is removed and (b) the current through the device (anode−cathode) is less than the holding current specified by the manufacturer. Hence VG can be a voltage pulse, such as the voltage output from a UJT relaxation oscillator.
These gate pulses are characterized in terms of gate trigger voltage (VGT) and gate trigger current (IGT). Gate trigger current varies inversely with gate pulse width in such a way that it is evident that there is a minimum gate charge required to trigger the thyristor.
[edit] Switching characteristics
In a conventional thyristor, once it has been switched on by the gate terminal, the device remains latched in the on-state (i.e. does not need a continuous supply of gate current to conduct), providing the anode current has exceeded the latching current (IL). As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (IH).
V - I characteristics.
A thyristor can be switched off if the external circuit causes the anode to become negatively biased. In some applications this is done by switching a second thyristor to discharge a capacitor into the cathode of the first thyristor. This method is called forced commutation.
After a thyristor has been switched off by forced commutation, a finite time delay must have elapsed before the anode can be positively biased in the off-state. This minimum delay is called the circuit commutated turn off time (tQ). Attempting to positively bias the anode within this time causes the thyristor to be self-triggered by the remaining charge carriers (holes and electrons) that have not yet recombined.
For applications with frequencies higher than the domestic AC mains supply (e.g. 50 Hz or 60 Hz), thyristors with lower values of tQ are required. Such fast thyristors are made by diffusing into the silicon heavy metals ions such as gold or platinum which act as charge combination centres. Alternatively, fast thyristors may be made by neutron irradiation of the silicon.

31. SEL Facts Self-sustained current, only recovered by power cycle
SEL increases with temperature
Modern devices may have different latchup paths
Both high current and low current SELs can occur
Characterization of SEL requires long range ions
SEL is a critical effect with potential catastrophic impact on spacecraft systems
SEL sensitive components shall as far as possible be avoided

32. SEL increases at high temperature
[JPL course by L.Scheick]

33. Single Event Hard Errors: stuck bits
[Edmonds 2001]
Large part to part variations
Samsung 1Gbits DDR1 SDRAM
Hyundai 64-Mb SDRAM
Due to Micro-dose or displacement damage
[Edmonds 2008]
Bit Cells that can not be wrote any more, their content is stuck.
They may recover with time, or not. Can beat EDAC, in the past they appeared at EOL, now may occur at BOL

34. DDR3 results – Stuck bits
Hard SEUs: can not be removed by rewriting
[M. Herrmann, IDA, 2014]

35. Stuck bits in NAND-flash
[K. Grürmann, IDA, 2012]

36. Destructive events in NAND-Flash
Samsung 8Gb NAND-Flash
Thermal picture charge pump region
[K. Grürmann, IDA, 2012]
[F. Irom, TNS Feb. 2010]
Permanent damage with indefinite data loss
16 Gbit Micron shows also other failure types affecting the on-chip microcontroller

37. Single Event Burnout SEB
Parasitic BJT
(Bipolar Junction Transistor)
[S. Liu, 2006]
Triggered by heavy ions, and possibly by protons and neutrons
Always destructive
power BJTs, FETs, MOSFETs are sensitive to SEB
Creating a direct current path between drain and source
Parasitic bipolar transistor
Bipolar Junction Transistor
What is the context in space appliciation

38. SEB damage in MOSFETs, IGBT
IGBT damage
[E. Lorfèvre, 1998]
Power MOSFET
[E. G. Stassinopoulos, 1992]

39. SEB damage in Schottky diodes
200V Schottky diodes
[J. S. George, 2013]
Also observed in low voltage Schottky diodes (35V – 45V)
[M. O’Bryan 2012]
IR at reverse Voltage of 45V
[TRAD SEE test report 2015]

40. Single Event Gate Rupture SEGR
Gate oxide
Gate
The charge deposited by the incident ion increases the electric field already present at he gate, exceeding the oxide breakdown field.
Always destructive
Decreases with angle of incidence
Increases with electric field
Power MOSFETs most susceptible
MIM capacitor structures
What is the context in space appliciation

41. SEGR damage [O.H. Pakarinen, NIM B 2009]
[A. Mefteh, Phys. Rev. B, 1994]
The initial ion track damage is ≤ 10nm in diameter

42. Safe Operation Area (SOA): issue of ion range (energy) used for testing
Manufacturer’s data with short range ions
Data with long range ions
IRHMB57260SE 200V NMOSFET.
SEE were SEB and SEGR
[L. Scheick, DW 2009]
[L. Scheick, JPL 2008

43. Single Event Dielectric Rupture (SEDR) in linear devices
OP27 Low Noise Operational Amplifier.
[G. Lum 2000,
N. Boruta 2001]
These events often occur at the output capacitor of linear operational amplifiers when supply and output voltage bias is close to the maximum limit.

44. Single Event Effects - Summary
All listed in E-10-12
Non Exhaustive list, more in ECSS E-ST-10-12C

45. Complex devices may be sensitive to many different SEE types
Example: mixed signal ASICs,
SEEs may propagate to other blocks / subsystems
SET, SEB, SEGR, SEFI
SET, SEFI, SEDR
SET
SET, SEDR
SEB
SET
SEU
SEFI
SEU
SEFI
SET, SEDR
SEU
SEFI
SET
SET
SEU
SEFI
SET
SET
SEFI
SEU
SEFI
SET, SEDR
SEU
SEFI
SHE
SEU
SEFI
SEU
SEFI
SHE
SEGR?
SEU
SEFI
SEL in CMOS technology [

46. Examples of SEE anomalies
PRARE on ERS-1. A 64-kbit CMOS SRAM failed due to SEL. PRARE only lasted operational for 5 days
IAISI on METOP. About half the SEUs are located in the SAA. Those upsets may be related to the emerging issue of high-Z recoils within the radiation hardened device (HX6228 memory).
ISS. SETs on optocoupler 6N134 are held responsible of unexpected reset on a reset circuit that was designed only to be used for ground testing.
[R. Ecoffet TNS 2012]

47. Outline SEE basic mechanisms Beam: LET, range, energy
Counting events, cross-section
Different types of SEEs
SEU, SET SEL SEB SEGR
New effects: MBUs, proton and electron direct ionization
Practical aspects of SEE testing
Checking the beam
PIN diode, SEU monitor, RPUM
Statistics, Uncertainties, Error Bars
Lot-to-lot variations

48. Checking the beam: the ESA SEU monitor
[F-X Guerre, HIREX, 2013]
4 dies module of the 0.25um
ATMEL AT60142F 4Mbit SRAM

49. Uniformity of beam flux
Kr, 305 MeV
+/-10%
+/-20%

50. Checking the beam: the ESA calibrated PIN diode system
Charge collection
Energy deposited in the PIN diode (MeV)
9.3MeV/a
RADEF cocktail

51. Statistics: counting events
In this case
For a fluence of 1E5 particles/cm2
The number of SEB detected is
proportional to fluence.
Counting SEB events at GANIL (Xe)
LET [MeVcm2/mg]
27, 60
[Binois, Carvalho, 2013]
SEE test fluences are tuned / adapted during SEE testing depending on the SEE effect tested. The goal is always to get enough statistics in order to obtain reliable results.

52. Fluence of events follows Poisson, i. e
Fluence of events follows Poisson, i.e. Weibull function with a shape factor of 1
SEGR in power MOSFET and capacitors 10 1 2 3 4 5 6 -3 -2 -1
Capacitor
Weibull probability
Fluence of failure (cm )
HG0K
Shape factor
(slope) is 1
Observed for both planar large area capacitors and power MOSFETs
This statistical behaviour is expected for all single event effects
[V. Ferlet-Cavrois, TNS 2012]

53. Suggested Error Bar Recipe, in the new version of the ESCC25100 (Oct
Uncertainty on the facility dosimetry
10% [ESCC25100 ]
Follows a Poisson distribution
Advised 95% confidence level
“Real” value will be within measured N events plus or minus error bar for 95% of data.
The accuracy of the X-section depends on the fluence deposited and the number of events detected.

54. Upper and Lower limits of Error Bars
[ESCC 25100, Oct. 2014]
100 events is generally considered as a reasonable amount of statistics during SEE testing in order to ensure a high confidence level of the results.

55. Test Example, use of Error Bars
Same reference but different date codes:
different latch-up response
256k x 16 SRAM Samsung K6R4016V1D

56. Cumulated effects: TID + SEE
In some cases SEE sensitivity can vary with received TID.
DC220 and DC328 were showing similar SEL response,
Same process?
But their TID response is different
Not really

57. 256k x 16 SRAM Samsung K6R4016V1D Same Example: with heavy ions
Manufacturer process changes also affect SEE sensitivity. Test the LOT that you want to fly. Always test your lot if you are using COTS.
256k x 16 SRAM Samsung K6R4016V1D

58. SEE Test complexity (1)
SEE tests can be very long and complex on devices like ASICs, FPGAs, µProcessors or new state of the art electronic devices, many different SEE types can appear at the same time.
The presence of a radiation effects expert and a electronic design engineer is often required because real-time decision making is critical depending on test results. Repeating SEE test can be very costly in terms of planning and budget.
SEE tests can be done at device level or at board / application level. The later are even more complex.

59. Complex Application level SEE test sequence example
SEE Test complexity (2)
Example of planning of a SEL test on a simple device (CMOS switch)

60. Conclusion Large variety of single event effects
SEE are linked to the DUT technology
New SEEs arise in new technologies.
Highly scaled techs have higher SEE sensitivity
SEE tests can be very complex
Real-time decision making is a must.
COTS issue
Test of the flight lot is mandatory
Secure procurement for an homogeneous lot
For experimenters
Check your beam
Use error bars
Ask a radiation effects expert in case of doubt