1. SoCLog: A Real-Time, Automatically Generated Logging and Profiling Mechanism for FPGA-based Systems On Chip
Ioannis Parnassos, Panagiotis Skrimponis,
Georgios Zindros, Nikolaos Bellas

2. Motivation
What: Need for system-level performance analysis of SoCs Why important: Use to evaluate system-level performance and iteratively optimize How: Limited availability of graphical logging/profiling mechanisms at system level to detect performance bottlenecks and improve performance No VTUNE for FPGA SoC exists
There is a need to analyze performance and understand performance bottlenecks in modern FPGA-based SoCs. This is important not only for designers for manually optimizing an accelerator-based SoC design, but also as an analysis tool which is part of a system-level HLS tool.
There are no tools that offer system-level run-time logging/profiling mechanisms to help in this analysis of the performance of an instantiation of a design.
No VTUNE for FPGA SoCs.
September 1, 2016
FPL 2016

3. SoCLog
SoCLog is a hw/sw infrastructure to automatically generate logging mechanisms in an FPGA-based SoC
Runtime capture and visualization of activity of the components of an SoC
Automatic generation of all hardware component required and easy access of all activity information at the application software level
So, to fill this need we are proposing SoCLog, a SW/HW framework used to automatically generate logging and profiling mechanisms in FPGA-based SoCs.
SoCLog hides the complexity by capturing logging information for each component of an SoC at runtime and providing intuitive visualization of this information
All logging hardware required is automatically generated given the SoC as input.
September 1, 2016
FPL 2016

4. SoCLog HW Architecture
SoCLog attaches Sampling and Triggering hardware mechanisms to each component of an SoC :
Accelerators, Peripheral, Buses
Accelerators can be generated for example by an HLS tool. This mechanisms are used to detect the beginning and end of a transaction: accelerator invocation, bus read and writes, peripheral use.
Additional components are also added such as DDR controllers, SRAMs, and a system manager for scheduling computations and orchestrating data movement. It can be a Microblaze processor.
Sampling and Trigger (S&T) mechanisms used to detect Start/End of a transaction. Added as attachments by SoCLog automatically to
Accelerators
Peripherals
Buses
September 1, 2016
FPL 2016

5. SoCLog HW Architecture
Detect the Beginning and End of each
Read Data Channel Transaction
Detect the Beginning and End of
Accelerator invocation
AXI-4 Bus
AXI-4 Bus Read Channel S&T
DCT accelerator
DCT Accelerator S&T
ap_start
ap_done
Trigger
BRAM Event Logging
Profile Logic
September 1, 2016
FPL 2016

6. SoCLog SW Architecture
Extends RIFFA 2.0 API
int fpga_recv_log (fpga_t *fpga, int chnl, void * data, long timeout)
fpga_t * fpga = fpga_open(0);
int r = read_data(“input_file", buf, BUF_SIZE);
printf("Read %d bytes from file", r);
int s = fpga_send(fpga, chnl, buf, BUF_SIZE/4, 0, 1, t);
printf("Sent %d words to FPGA", s);
r = fpga_recv(fpga, chnl, buf, BUF_SIZE/4, t);
printf("Received %d words from FPGA", r);
// Process results ...
w = fpga_recv_log (fpga, chnl, log_buf, t);
// Process log data in log_buf and show in GUI ...
fpga_close(fpga);
RIFFA (Reusable Integration Framework for FPGA Accelerators)
is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus.
September 1, 2016
FPL 2016

7. JPEG application (VIDEO)
SoC with three HW accelerators
DCT
Quantization, inverse Quantization (Q/iQ)
iDCT
Unoptimized DCT (839 cycles/block)
Optimized iDCT (255 cycles/block)
Both DCT/iDCT are optimized
September 1, 2016
FPL 2016

8. Conclusions
SoCLog a system-level logging/profiling, GUI-based, HW/SW infrastructure for FPGA SoCs
Transparent to the user
Very low area overhead
Can be used to evaluate performance and detect bottlenecks at system level
Incrementally and spirally drive optimization directives at component level
September 1, 2016
FPL 2016