1. Present System Back-end Front End PMT ROS Optical links ADC Pipeline
40 MHz
100 KHz
Optical links
100 KHz
ADC
100 KHz
Pipeline
Event Buffer IB
Ser
PMT
OMB
ROD
ROS
100 KHz
Interface
Control Configuration
Adders
L1 Accept – 100 KHz
Central Trigger Processor
L1Calo
Muons
40 MHz
Trigger PP

2. Upgrade implications. Back-end Front End ROS PMT Event Buffer Pipeline
40 MHz
100 KHz
100 KHz
100 KHz
Input Stage (DES)
Pipeline
Event Buffer
ROD
Processor
ROS
Optical links
ADC
SER
PMT
40 MHz
40 MHz
Trigger PP
Interface
Control Configuration
40 MHz
100 KHz
Central Trigger Processor
Muons
Tracks
L1Calo
L1 Accept

3. Rio Stockholm Chicago Heidelberg Valencia CERN ROS Front End Back-end
Central Trigger Processor
L1Calo
Muons
ROS
Front End
Back-end
Trigger PP
OMB
ADC IB
Ser
Interface
Control Configuration
Event Buffer
100 KHz
Pipeline
PMT
L1 Accept – 100 KHz
ROD
40 MHz
Adders
Chicago
Argonne
Heidelberg
Stockholm
Valencia
CERN
Back-end
Front End
Input Stage (DES)
Pipeline
Event Buffer
ROD
Processor
ROS
Optical links
ADC
SER
PMT
40 MHz
40 MHz
Trigger PP
Interface
Control Configuration
40 MHz
100 KHz
Central Trigger Processor
Muons
Tracks
L1Calo 3
L1 Accept

4. Letter of Intent LINKS WITH Front-End
One FE motherboard (12Ch) would be read-out by 12 GBT links.
16 SNAP12 connectors for Slice.
LINKS to ROS
Through backplane and a Transition Module with the standard defined by ROS.
ROD PROCESSOR
Pipeline- Event buffer
Transmission to Pre-Processor
DQ check
Reconstruction
PREPROCESSING
Pre-Processor in a different device (FPGA) with links to L1Calo.
InputStage – PreProc high speed links through the motherboard.

6. Conclusions
Seems clear that every sub-detector will provide their own ROD.
“Not much appetite for the pursuit of a “Single ROD”” (D. Francis)
SNAP12 conectors. December?
Portugal collaboration – GBT firmware
Who is really working?
Argonne – Chicago : LVPS – ADC / ASIC design – Dataformat. First results shown.
Stockholm already have experience with FPGA Transceivers
GBT protocol simulated ( not shown)