1. Diode Transistor Logic – DTL
Chapter 6
Diode Transistor Logic – DTL

2. Diode Transistor Logic
One of the major issues with RTL is its low fan-out.
Even with adding active devices to the output, the fan-out is still quite limited.
In the early 1960's, a solution for the problem was proposed in the form of a new logic family which utilizes diodes in addition to transistors.

3. Basic DTL Inverter V in
out CC R C B Q o D I L X

4. Basic DTL Inverter Vout = VCC - IRC * RC VOH Vout = VOH = VCC VOL
If Vin = 0, DI is forward biased, Vx = VD,I (ON).
However, this is not enough to turn on both DL and QO. Therefore, they both will be off.  IC,O = 0.
If we assume that there is no load, then IRC = 0.
Vout = VOH = VCC
VOL
If Vin is high enough, DI, DL and QO will all be on. Eventually, QO will saturate. At that point
Vout = VOL = VCE,O (Sat)

5. Basic DTL Inverter (Contd.)
VIL
VIL occurs when IRC stops being 0. If we assume that no load is added, then this will only happen when IC,O is no longer 0. That occurs when the transistor switches from cut-off to forward active mode.
Therefore, VIL is the input voltage that causes QO to switch from cut-off to forward active.
QO needs VBE (FA) between its base and emitter to switch on.
That makes
VX = VD,L (ON) + VBE (FA)
However,
Vin = VX – VD,I (ON)
If we assume that the two diodes are similar, then
VD,I (ON) = VD,L (ON)
Therefore,
Vin = VIL = VBE (FA)

6. Basic DTL Inverter (Contd.)
VIH
VIH occurs when IRC stops changing. If we assume that no load is added, then this will only happen when VCE,O becomes constant. That occurs when the transistor reaches saturation mode.
Therefore, VIH is the input voltage that causes QO to saturate.
QO needs VBE (Sat) between its base and emitter to saturate.
That makes
Vin = VIH = VBE (Sat) + VD,L (ON) – VD,I (ON)
VIH = VBE (Sat)

7. DTL VTC
NOTE:
We still have the same problem with the very small low noise margin (NML) as in RTL V
out in IL
= V BE
(FA) IH
(Sat) OL CE OH CC

8. Basic DTL NAND Gate
Using the above circuit, we can make a NAND gate simply by adding input diodes in parallel
Exercise:
Prove that the above circuit implements the NAND function V A
out CC R C B Q o D L

9. Modified DTL
To improve the low noise margin, we can add a level shifting diode into the circuit.
Adding DL,2 will increase the input voltage required to turn the transistor on and then to saturate it.
Therefore, both VIL and VIH will increase by an amount of VD(ON).
The VTC shifts to the right by that amount. NML increases by that amount and NMH decreases by that amount as well. Given that the NMH was quite large to start with, this reduction will not cause any major issues.

10. Modified DTL (Contd.)
Adding the level shifting diode is not without a side effect. The side effect here is increased switching time. Actually, the switching time increases quite a bit. The reason is that there are more junctions to charge/discharge whenever the gate changes states.
To improve the situation, a way of quickly discharging a large current down to ground is needed. So, a discharge path through a resistor is added to the base of QO.

11. Modified DTL (Contd.)

12. Transistor Modified DTL
The fan-out of DTL is limited by the amount of current that the transistor is capable of absorbing when in saturation. This amount is determined by the amount of current supplied into its base.
To increase this current, we can replace the first level shifting diode by a "self-biased" transistor setup.
The "self-biased" transistor
The transistor in the configuration on the right is self biased to always operate in Forward Active mode. Given the voltage polarity across the resistor, the B-C junction can never be forward biased.
Since it only operates in forward active mode, then the emitter current is always (bF + 1) times the base current.

13. Transistor Modified DTL
Putting the circuit together we get: V in
out CC R C
rRB Q o D I L
- V EE
(1-r)RB

14. Transistor Modified DTL
The table below shows the function of each element in transistor modified DTL.
Element
Function DI
Input diode. Limits IIH
rRB
Limits IIL
(1-r)RB
Self biases QL QL
Base driving current for QO DL
Level shifting diode RD
Discharge path. QO
Output inverting BJT. RC
Passive current sourcing pull-up

15. Developing the VTC Assume:
VD(ON) = 0.7, VBE(FA) = 0.7V, VBE(Sat) = 0.8, and VCE(Sat) = 0.2. V in
out
5 V
6 kW
1.75 kW Q o D I L
5 kW
2 kW

16. Developing the VTC For Vin = 0, QO is off.
Therefore, VOH = VCC = 5 V.
For Vin high, QO will be saturated.
Therefore, VOL = VCE (Sat) = 0.2 V.
QO turns on when:
VIL = VBE,O (FA) + VD,L (ON) + VBE,L (FA) – VD,I (ON)
VIL = 2 VBE (FA) = 1.4 V.
QO saturates when:
VIH = VBE,O (Sat) + VD,L (ON) + VBE,L (FA) – VD,I (ON)
VIH = VBE (Sat) + VBE(FA) = 1.5 V.

17. The Modified DTL VTC V V = V V = VBE (Sat) + VBE (FA) V = V (Sat) V
out V
= V OH CC V
= VBE (Sat) + VBE (FA) IH V
= V
(Sat) OL CE V
= 2 V
(FA) V IL BE in

18. The Modified DTL Fan-out
Output high fan-out.
When the output of the driving gate is high, the input diodes of all load gates will be turned off.
Therefore, IIH = 0.
Output high fan-out is infinite.
Output low fan-out.
The maximum fan-out can be determined by how much output current – IOL – the driving gate can sink into the collector of QO compared to the amount of current generated from the input of each load gate – IIL.

19. The Modified DTL Fan-out
The output of the driving gate becomes low when its input is high, its DI turns off, QL, DL, are on and QO is saturated.
The input diodes of all load gates are forward biased. Their, QL, DL, and QO are all off. V in
5 V
6 kW
1.75 kW Q o D I L
5 kW
2 kW
out QL

20. Input Low Current - IIL 5 V 1.75 kW 6 kW QL 2 kW V Q D 5 kW out in o I

21. Output Low Current - IOL
IOL = IC,O(Sat) – IRC
IC,O(Sat) = sOLbFIB,O(Sat)
At edge of saturation, s = 1
IC,O(Sat) = bFIB,O(Sat)
IB,O(Sat) = IE,L - IRD V in
5 V
6 kW
1.75 kW Q o D I L
5 kW
2 kW QL
IOL

22. Output Low Current - IOL
If we assume that IB,L is very small, we can assume:
VB,L = VBE,L(FA) + VD,L(ON) + VBE,O(Sat)
If we consider the circle as a super-node, then IE,L = IrRB
Therefore,
5 V
rRB
(r-1)RB QL Q o
Super-node D L
5 kW

23. Example – Modified DTL Fan-out
IB,O = 1.6 m – 160 m = 1.44 mA IC,O = 100 * 1.44 m = 144 mA – Assuming s = 1 and bF = 100 IOL = 144 m – 800 m = mA N = / 1.09 =

24. Power Dissipation ICC(OL) ICC(OL) = IRB + IRC QO is saturated. 5 V rRBin
5 V RC
rRB Q o D I L RD
(1-r) RB QL

25. Power Dissipation ICC(OH) QO is cut-off. 5 V rRB RC (1-r) RB V QL Q Din
5 V RC
rRB Q o D I L RD
(1-r) RB QL

26. Power Dissipation - Example
ICC(OL) = 2.4 mA

27. DTL Summary Pros: Cons: Relatively large fan-out
A large area is needed for the input diodes.
A relatively large power dissipation.
Slow transition time.
Long propagation delay ~60 nS.