1. Design For Testability
No single methodology solves all testing problems.
No single DFT techniqne is effective for all kinds of circuits.
DFT techniqnes:
1. Ad hoc techniqnes.
2. Structured techniqnes:
a. Full scan.
b. Partial scan.
There is definitely no single methodology which solves all VLSI testing problems; there also is no single DFT technique which is effective for all kinds of circuits. DFT techniques can largely be divided into two categories, i.e., ad hoc techniques and structured (systematic) techniques. The latter will be discussed later, which include major internal scan approaches; while the former are the subject of this section, which are basically ad hoc DFT guidelines. Some important guidelines are listed below.

2. Ad Hoc DFT Guidelines
1. Employ test points to enhance controllability & observability (testpoints: control points (CPs) & observation points (OPs)).
Test points include control points (CPs) and observation points (OPs). The former are active test points, while the latter are passive ones. There are test points which are both CPs and OPs.
After partitioning, we still need a mechanism of directly accessing the interface between the modules. Test stimuli and responses of the module under test can be made accessible through test points. Test point insertion can be done as illustrated in the figure, and can be accessed via probe pads and extra or shared (multiplexed) input/output pins.
Before exercising test through test points which are not PIs and POs, we should investigate into additional requirements on the test points raised by the use of test equipments.

3. Ad Hoc DFT Guidelines
2. Partition large circuits into smaller subcircuits to reduce test generation cost (using MUXes and/or scan chains). .
One of the most important step in designing a testable chip is to first partition the chip in an appropriate way such that for each functional module there is an effective (DFT) technique to test it. Partitioning certainly has to be done at every level of the design process, from architecture to circuit, whether testing is considered or not. Conventionally, when testing is not considered, designers partition their objects to ease management, to speed up turn-around time, to increase performance, and to reduce costs. We stress here that the designers should also partition the objects to increase their testability.
Partitioning can be functional (according to functional module boundaries) or physical (based on circuit topology). In general, either way is good for testing in most cases. Partitioning can be done by using multiplexers and/or scan chains. Maintaining signal integrity is a basic guideline on partition for testability, which helps localize faults. After partitioning, modules should be completely testable via their interface.

4. Ad Hoc DFT Guidelines 3. Design circuits to be easily initializable.
4. Disable internal one-shots (monostables) during test
(due to difficulty for tester to remain synchronized
with DUT).
5. Disable internal oscillators and clocks during test.
Design circuits to be easily initializable.
This increases predictability. A power-on reset mechanism is the most effective and widely used approach. A reset pin for all or some modules also is important. Synchronizing or homing sequences for small finite state machines may be used where appropriate (a famous example is the JTAG TAP controller-see the chapter on Boundary Scan).
Disable internal one-shots (monostables) during test.
This is due to the difficulty for the tester to remain synchronized with the DUT. A monostable (one-shot) multivibrator produces a pulse of constant duration in response to the rising or falling transition of the trigger input. It has only in stable state. Its pulse duration is usually controlled externally by a resistor and a capacitor (with current technology, they also can be integrated on chip).
One-shots are used mainly for 1) pulse shaping, 2) switch-on delays, 3) switch-off delays, 4) signal delays. Since it is not controlled by clocks, synchronization and precise duration control are very difficult, which in turn reduces testability by ATE. Counters and dividers are better candidates for delay control.
Disable internal oscillators and clocks during test.
To guarantee tester synchronization, internal oscillator and clock generator circuitry should be isolated during the test of the functional circuitry. Of course the internal oscillators and clocks should also be tested separately.

5. Ad Hoc DFT Guidelines 6. Partition large counters into smaller ones.
7. Avoid the use of redundant logic.
8. Provide logic to break global feedback paths.
Provide logic to break global feedback loops.
Circuits with feedback loops are sequential ones. Effective sequential ATPGs are yet to be developed, while combinational ones are relatively mature now. Breaking the feedback loops turn the sequential testing problem into a combinational one, which greatly reduces the testing effort needed in general. Specifically, test generation becomes feasible, and fault localization becomes much easier. Breaking global feedback loops are especially effective, since otherwise we are facing the problem of testing a large sequential circuit (such as a CPU), which can frequently be shown to be very hard or even impossible.
Scan techniques and/or multiplexers which are used to partition a circuit can also be used to break the feedback loops. The feedback path can be considered as both the CP and the OP.
Partition large counters into smaller ones.
Sequential modules with long cycles such as large counters, dividers, serial comparators, and serial parity checkers require very long test sequences. For example, a 32-bit counter requires 232 clock cycles for a full state coverage, which means a test time of more than one hour only for the counter, if a 10 MHz clock is used. Test points should be used to partition these circuits into smaller ones and test them separately.
Avoid the use of redundant logic.
This has been discussed in the chapters on combinational and sequential ATPG.

6. Ad Hoc DFT Guidelines
9. Keep analog and digital circuits physically apart.
10. Avoid the use of asynchronous logic.
Keep analog and digital circuits physically apart.
Mixed analog and digital circuits in a single chip is gaining attraction as VLSI technologies keep moving forward. Analog circuit testing, however, is very much different from digital circuit testing. In fact, what we mean by testing for analog circuits is really measurement, since analog signals are continuous (as opposed to discrete or logic signals in digital circuits). They require different test equipments and different test methodologies, therefore they should be tested separately.
To avoid interference or noise penetration, designers know that they should physically isolate the analog circuit layout from the digital one which resides on the same chip, with signals communicated via AD converters and/or DA converters. For testing purpose, we require more. These communicating wires between the analog and digital modules should become the test points, i.e., we should be able to test the analog and digital parts independently.
Avoid the use of asynchronous logic.
Asynchronous circuits are sequential ones which are not clocked. Timing is determined by gate and wire delays. They usually are less expensive and faster than their synchronous counterpart, so some experienced designers like to use them. Their design verification and testing, however, are much harder than synchronous circuits. Since no clocking is employed, timing is continuous instead of discrete, which makes tester synchronization virtually impossible, and therefore only functional test by application board can be used. In almost all cases, high fault coverage cannot be guaranteed within a reasonable test time.

7. Ad Hoc DFT Guidelines
11. Avoid diagnostic ambiguity groups such as wired-
OR/wired-AND junctions and highfanout nodes.
12. Consider tester requirements (pin limitation,
tristating, etc.)
Avoid diagnostic ambiguity groups such as wired-OR/wired-AND junctions and high-fanout nodes.
Apart from performance reasons, wired-OR/wired-AND junctions and high-fanout nodes are hard to test (they are part of the reasons why ATPGs are so inefficient), so they should be avoided.
Consider tester requirements.
Tester requirements such as pin limitation, tristating, timing resolution, speed, memory depth, driving capability, analog/mixed-signal support, internal/boundary scan support, etc., should be considered during the design process to avoid delay of the project and unnecessary investment on the equipments.

8. Ad Hoc DFT Guidelines High fault coverage not guaranteed.
Manual test generation still required.
Design iterations also required.
The above guidelines are from experienced practitioners. They are not meant to be complete or universal. In fact, there are drawbacks for these techniques:
high fault coverage cannot be guaranteed;
manual test generation is still required;
design iterations are likely to increase.

9. Syndrome-Testable Design
Savir, IEEE TC-29(6), 1980, & TC-30(8), 1981
Syndrome testing [1, 2] is an exhaustive method, and is only for combinational circuits, so it is not considered as an efficient method. The idea of introducing control inputs to make circuits syndrome testable (to be explained below) however can be applied effectively in many DFT situations other than syndrome testing.
The syndrome of a boolean function f is , where k is the number of 1s (minterms) in f and n is the number of independent input variables.
By the definition, A circuit is said to be syndrome testable iff fault
, To use syndrome testing, the DUT must be syndrome testable Furthermore, since the method is exhaustive (we have to evaluate all 2n input combinations), it is applicable only to circuits with small number of inputs, e.g.,
For large circuits, we can partition them with scan chains and/or multiplexers.
According to the definition, the syndromes of primitive gates can easily be calculated, as shown in the table.
Gate
ANDn
ORn
XORn
NOT S
1/2n
1-1/2n
1/2
1/2

10. Syndrome-Testable Design
Consider a circuit having 2 blocks, f and g, with unshared inputs:
The overall syndrome of a fanout-free circuit can then be derived in a recursive manner. For example, consider a circuit having 2 blocks, f and g, with unshared inputs. Its overall syndrome can be obtained according to the table.
O/p gate OR
AND
XOR
NAND
NOR S
Sf +Sg - SfSg
SfSg
Sf + Sg - 2SfSg
1 - Sf - Sg
1 - Sf - Sg + SfSg

11. Syndrome-Testable Design
Exercise 1 Show that for blocks with shared inputs (circuits having reconvergent fanouts):

12. Syndrome-Testable Design

13. Syndrome-Testable Design
Definition 1
A logic function is unate in a variable xi if it can be represented as an sop or pos expression in which the variable xi appears either only in an uncomplemented form or only in a complemented form.
Theorem 1
A 2-level irredundant circuit realizing a unate function in all its variables is syndrometestable.
Theorem 2
Any 2-level irredundant circuit can be made syndrome-testable by adding control inputs to the AND gates.

14. Syndrome-Testable Design

15. Syndrome-Testable Design
Drawbacks:
Only for combinational logic.
Exhaustive: all patterns applied, and # of 1s
recorded. Only applicable to small circuits (larger
circuits partition).
Modification doubles test set size.

16. Scan -Type Design
To provide controllability and observability of internal state variables for testing.
To turn the sequential test problem into a combinational one.
Four Major Approaches:
1. Shift-register modification [M. Williams & Angell, IEEE TC-22(1), 1973].
2. Scan path [Funatsu et al., DA Symp., 1975, & ITC, 1978].
3. LSSD [Eichelberger & T. Williams, DAC, 1977, & JDAVTC-2(2), 1978].
4. Random access [Ando, COMPCON, 1980].
Although we have not formally presented the scan techniques, their purpose and importance have been discussed in the previous sections, namely,
they are effective for circuit partitioning;
they provide controllability and observability of internal state
variables for testing;
they turn the sequential test problem into a combinational one.
There are four major scan approaches that we will discuss in this section, i.e.,
1. Shift-register modification [3];
2. Scan path [4, 5];
3. LSSD [6, 7]
4. Random access [8].

17. Shift-Register Modification
Invented at Stanford in by M. Williams & Angell.
Later adopted by IBM---heavily used in IBM products
This approach is also called the MUX Scan Approach, in which a MUX is inserted in front of every FF to be placed in the scan chain. It was invented at Stanford in 1973 by M. Williams & Angell, and later adopted by IBM---heavily used in IBM products.
A popular finite state machine (FSM) model for sequential circuits is shown here, in which X is the PI vector, Z the PO vector, Y the excitation (next state) vector, and y the present state vector. The excitation vector is also called the pseudo primary output (PPO) vector, and the present state vector is also called the pseudo primary input (PPI) vector.

18. Shift-Register Modification
To make elements of state vector controllable and observable, we add
1. A TEST mode pin(T).
2. A SCAN-IN pin(SI).
3. A SCAN-OUT pin (SO).
4. A MUX (switch) in front of each FF (M).
When the test mode pin T=0, the circuit is in normal operation mode; when T=1, it is in test mode (or shift-register mode). This is clearly shown in the figure.

19. Shift-Register Modification
Test procedure:
1. Switch to the shift-register mode and check the SR operation by shifting in an alternating sequence of 1s and 0s, e.g., (functional test)
2. Initialize the SR---load the first pattern.
3. Return to the normal mode and apply the test pattern.
4. Switch to the SR mode and shift out the final state while setting the starting state for the next test. Go to 3.
The SI pin may be a redefined input pin (using a MUX ) in test mode.
The SO pin may be a redefined output pin (using a MUX ) in test mode.
The test procedure using this method is shown here.
This approach effectively turns the sequential testing problem into a combinational one, i.e., the DUT becomes the combinational logic which usually can be fully tested by compact ATPG patterns. Unfortunately, there are two types of overheads associated with this technique which the designers care about very much: the hardware overhead (including three extra pins, multiplexers for all FFs, and extra routing area) and performance overhead (including multiplexer delay and FF delay due to extra load).
Since test mode and normal mode are exclusive of each other, in test mode the SI pin may be a redefined input pin, and the SO pin may be a redefined output pin. The redefinition of the pins can be done by a multiplexer controlled by T. This arrangement is good for a pin-limited design, i.e., one whose die size is entirely determined by the pad frame. The actual hardware overhead varies from circuit to circuit, depending on the percentage of area occupied by the FFs and the routing condition.

20. Scan Path
By Kobayashi, 1968, and Funatsu, 1975, at NEC, and adopted by NEC.
Uses raceless D-FFs: each FF consists of 2 latches operating in master-slave fashion, and has 2 clocks to select either SI or DI.
Normal mode: C2 = 1 to block SI; C1 = to load KI.
SR(test) mode: C1 = 1 to block DI; C2 = to load SI.
This approach is also called the Clock Scan Approach, in which the multiplexing function is implemented by two separate ports controlled by two different clocks instead of a MUX. It was invented by Kobayashi et al. in 1968, and reported by Funatsu et al. in 1975, and adopted by NEC. It uses two-port raceless D-FFs: each FF consists of two latches operating in a master-slave fashion, and has two clocks (C1 and C2) to control the scan input (SI) and the normal data input (DI) separately. The logic diagram of the two-port raceless D-FF is shown in the figure.
The test procedure of the Clock Scan Approach is the same as the MUX Scan Approach. The difference is in the scan cell design and control. The MUX has disappeared from the scan cell, and the FF is redesigned to incorporate the multiplexing function into the register cell. The resulting two-port raceless D-FF is controlled in the following way:
Normal mode: C2 = 1 to block SI; C1 = to load DI.
SR (test) mode: C1 = 1 to block DI; C2 = to load SI.
This approach is said to achieve a lower hardware overhead (due to dense layout) and less performance penalty (due to the removal of the MUX in front of the FF) compared to the MUX Scan Approach. The real figures however depend on the circuit style and technology selected, and on the physical implementation.

21. Level-Sensitive Scan Design (LSSD)
By Eichelberger and T. Williams, 1977, 1978
Latch-based design used at IBM.
Race-& hazard-free operation and testing: insensitive to rise time, fall time, delay, etc.
Faster than SR modification; lower hardware complexity.
More complicated design rules.
Uses 2 latches: one for normal operation and one for scan.
A logic circuit is level sensitive iff the steady state response to any allowed input change is independent of the delays within the circuit. Also, the response is independent of the order in which the inputs change.
This approach was introduced by Eichelberger and T. Williams in 1977 and It is a latch-based design used at IBM, which guarantees race- and hazard-free system operation as well as testing, i.e., it is insensitive to component timing variations such as rise time, fall time, and delay. It also is claimed to be faster and have a lower hardware complexity than SR modification. It uses two latches (one for normal operation and one for scan) and three clocks. Furthermore, to enjoy the luxury of race- and hazard-free system operation and test, the designer has to follow a set of complicated design rules (to be discussed later), which kill nine designers out of ten.

22. LSSD Polarity-Hold Latch:
The correct change of the latch output (L) is not dependent on
the rise/fall time of C, but only on C being ,1, for a period of time
data propagation and stabilization time.
LSSD requires that the circuit be LS, so we need LS memory elements as defined above. The figure shows an LS polarity-hold latch. The correct change of the latch output (L) is not dependent on the rise/fall time of C, but only on C being '1' for a period of time greater than or equal to data propagation and stabilization time.

23. LSSD Polarity-Hold Shift-Register Latch (SRL):
Normal mode: A = B =0, C =
SR (test) mode: C =0, AB = to shift SI through L1 and L2.
The figure shows the polarity-hold shift-register latch (SRL) used in LSSD as the scan cell.
The scan cell is controlled in the following way:
Normal mode: A = B =0, C =
SR (test) mode: C = 0, AB = to shift SI through L1 and L2.

24. LSSD Polarity-Hold, hazard-free, and level-sensitive.
To be race-free, clocks C & B as well as A & B must be nonoverlapping.
Avoids performance degradation introduced by the MUX in shift-register modification.
Can replace B with A+B, i.e., NOR(A,C).
The SRL has to be polarity-hold, hazard-free, and level-sensitive. To be race-free, clocks C and B as well as A and B must be nonoverlapping. This design (similar to Scan Path) avoids performance degradation introduced by the MUX in shift-register modification. If pin count is a concern, we can replace B with A + C, i.e., NOR(A, C).

25. Double-Latch LSSD

26. Single-Latch LSSD

27. Single-Latch LSSD With Conventional SRLs

28. SRL Using Two-Port L2*

29. SRL Using Two-Port L2*

30. Single-Latch LSSD With L2* Latches

31. LSSD Design Rules
1. Internal storage elements must be polarity-hold latches.
2. Latches can be controlled by 2 or more nonoverlapping clocks that satisfy:
(1) A latch X may feed the data port of another latch Y
iff the clock that sets the data into Y does not clock X.
(2) A latch X may gate a clock C to produce a gated
clock Cg , which drives another latch Y iff Cg , or any
other clock C1g , produced from Cg , does not clock X.

32. LSSD Design Rules
3. There must exist a set of clock primary inputs from which the clock inputs to all SRLs are controlled either through (1) single-clock distribution tree or (2) logic that is gated by SRLs and/or nonclock primary inputs. In addition, the following conditions must hold:
(1) All clock inputs to SRLs must be OFF when clock PIs
are OFF.
(2) Any SRL clock input must be controlled from one or
more clock PIs.
(3) No clock can be ANDed with either the true or the
complement of another clock.

33. LSSD Design Rules
4. Clock PIs cannot feed the data inputs to latches, either directly or through combinational logic.
5. Every system latch must be part of an SRL; each SRL must be part of some scan chain.
6. A scan state exists under the following conditions:
(1) Each SRL or scan-out PO is a function of only the
preceding SRL or scan-in PI in its scan chain during the
scan operation.
(2) All clocks except the shift clocks are disabled at the SRL
inputs.

34. LSSD Design Rules
(3) Any shift clock to an SRL can be turned ON or OFF by
changing the corresponding clock PI.
A network that satisfies rules 1-4 is level-sensitive.
Race-free operation is guaranteed by rules 2(1) & 4.
Rule 3 allows a tester to turn off system clocks and use the shift clocks to force data into and out of the scan chain.
Rules 5 & 6 are used to support scan.

35. Advantages With LSSD
Correct operation independent of AC characteristics.
Reducing FSM to C/L as far as testing is concerned.
Eliminating hazards & races; simplifying test generation and fault simulation.
The advantages associated with LSSD are:
1. Correct operation independent of AC characteristics guaranteed.
2. FSM is reduced to combinational logic as far as testing is concerned.
3. Hazards and races are eliminated, which simplifies test generation and
fault simulation.

36. Problems With LSSD
Design rules imposed on designers --- no freedom to vary from the overall schemes, and higher design and hardware costs (4-20% more h/w & 4 extra pins).
No asynchronous designs.
Sequential routing of latches can introduce irregular structures.
Faults Changing combinational function to sequential may cause trouble, e.g., bridging and CMOS stuck-open.
Function to be tested has been changed into a quite different combinational one, so specification language won, t be of any help.
Slow test application; normal-speed testing is impossible.
Not good for memory intensive designs.
There however are problems with LSSD (or previously discussed scan approaches):
1. Complex design rules are imposed on designers-no freedom to vary from the
overall schemes, and higher design and hardware costs (4-20% more hard-
ware and 4 extra pins).
2. No asynchronous designs are allowed.
3. Sequential routing of latches can introduce irregular structures.
4. Faults changing combinational function to sequential one may cause trouble,
e.g., bridging and CMOS stuck-open faults.
5. Function to be tested has been changed into a quite different combinational
one, so specification language will not be of any help.
6. Test application becomes a slow process, and normal-speed testing of the
entire test sequence is impossible.
7. It is not good for memory intensive designs.

37. Random Access Uses addressable latches.
Provides random access to FFs via multiplexing---address selection.
Used by Fujitsu, Amdahl, & TI (developed by Fujitsu [Ando, 1980]).
This approach uses addressable latches whose addressing scheme is similar to high-density memory addressing, i.e., an address decoder is needed. It provides random access to FFs via multiplexing-address selection. The approach was developed by Fujitsu [Ando, 1980], and was used by Fujitsu, Amdahl, and TI. Its overall structure is shown in the figure.

38. Random Access Fast; minimal impact on normal path. Advantages:
Fast for testing---random access.
Ability to ,watch, a node in normal operation mode
(impossible with LSSD).
Disadvantages:
Address decode---and thus h/w overhead---is large.
More pins added ( ... parallel address).
No asynchronous circuits.
The difference between this approach and the previous ones is that the state vector can now be accessed in a random sequence. Since neighboring patterns can be arranged so that they differ in only a few bits, and only a few response bits need to be observed, the test application time can be reduced. Also, it has minimal impact on the normal paths, so the performance penalty is minimized. Another advantage of this approach is that it provides the ability to 'watch' a node in normal operation mode, which is impossible with previous scan methods. The major disadvantage of the approach is that it needs an address decoder, thus the hardware overhead (chip area and pin count) is high.

39. A Typical CMOS Scan Cell Design
A typical CMOS scan cell design is shown in the figure.

40. Partial Scan D: Sequential depth (the distance along the longest path)
L: Maximum length of any cycle
The length of a test sequence for a sequential circuit is propotional to D . 2L .

41. Partial Scan BASIC IDEA METHOD 1 (Trischler et al, ITC-80)
Select a subset of flip-flops for scan
Lower overhead (area and speed)
Relaxed design rules
METHOD 1 (Trischler et al, ITC-80)
Use testability measure for flip-flop selection
Use sequential ATPG
METHOD 2 (Agrawal et al, D&T, April 1988)
Use functional vectors for initial fault coverage
Use comb. ATPG to select flip-flops for scan
Overhead about 50% of full-scan
METHOD 3 (Cheng and Agrawal, FTCS-19)
Select scan flip-flops to simplify sequential ATPG
Overhead about 25% of full scan

42. Partial Scan (Cheng and Agrawal)
SELECT MINIMAL SET OF FLIP-FLOPS TO ELIMINATE SOME OR ALL CYCLES
SELF-LOOPS (CYCLES OF UNIT LENGTH) ARE NOT BROKEN TO KEEP THE SCAN OVERHEAD LOW
THE NUMBER OF SELF-LOOPS IN REAL DESIGN CAN BE QUITE LARGE

43. Partial Scan (Cheng and Agrawal)

44. Partial Scan (Cheng and Agrawal)

45. Partial Scan (Cheng and Agrawal)
SEPARATE SCAN CLOCK IS USED
SCAN FLIP-FLOPS ARE REMOVED AND THEIR INPUT AND OUTPUT SIGNALS ARE ADDED TO THE PO/PI LISTS
A SEQUENTIAL CIRCUIT TEST GENERATOR IS USED FOR TEST GENERATION
THE VECTOR SEQUENCES ARE THEN CONVERTED INTO SCAN SEQUENCES:
EACH VECTOR IS PRECEDED BY A SCAN-IN SEQUENCE TO SET THE STATES OF SCANNED FLIP-FLOPS
A SCAN-OUT SEQUENCE IS ADDED AT THE END OF EACH VECTOR SEQUENCE

46. Partial Scan (Cheng and Agrawal)

47. Partical Scan (Gupta, Gupta, and Breuer)

48. Partical Scan (Gupta, Gupta, and Breuer)

49. Partical Scan (Gupta, Gupta, and Breuer)

50. Partical Scan (Gupta, Gupta, and Breuer)

51. Partical Scan (Gupta, Gupta, and Breuer)