1. ASIC Design Methodology
EL 653
ASIC Design Methodology
Extracted from “Advanced ASIC Chip Synthesis using Synopsys”, Himanshu Bhatnagar,
2001

2. STA: Static timing analysis
CT: Clock tree
DC: Synopsys Design Compiler

3. Typical Design Flow Architectural and electrical specification
RTL coding and simulation test bench preparation
DFT (design for test) memory BIST (built-in self test) insertion, for design containing memory elements
Exhaustive dynamic simulation of the design, in order to verify the functionality of the design
Design environment settings (technology library and other environment attributes)

4. Typical Design Flow
Constraining and synthesizing the design with scan insertion
Block level static timing analysis
Formal verification of the design (RTL against synthesized netlist)
Pre-layout static timing analysis on the full design

5. Typical design Flow
Forward annotation of timing constraints to the layout tool
Initial floorplanning with timing driven placement of cells, clock tree insertion and global routing
Transfer of clock tree to the original design (netlist)
Formal verification between the synthesized netlist and clock tree inserted netlist

6. Typical Design Flow
Extraction of estimated timing delays from the layout after the global routing step
Back annotation of estimated timing data from the global routed design
Static timing analysis using the estimated delays extracted after performing global route
Detailed routing of the design

7. Typical Design Flow
Extraction of real timing delays from the detailed routed design
Back annotation of the real extracted data from the detailed routed design
Post-layout static timing analysis
Functional gate level simulation of the design with post - layout timing
Tape out after LVS (layout-versus-schematic) and DRC (design rule checking) verification

8. Specifications
Chip design starts with the conception of an idea dictated by the market
The ideas are translated to architectural and electrical specifications
Architectural specification defines the functionality of the chip as well as the partition into several blocks
Electrical specification defines the relationship between the blocks in terms of timing information

9. RTL Coding
After the specifications are made, design continues with implementation
In the past implementation was done manually drawing schematics (components of a cell library)
Manual design was time consuming and impractical for design reuse
HDL are used today for implementation
Verilog and VHDL are mostly used today

10. RTL Coding
Three levels of abstraction my be used to represent the design: behavioral, RTL, and structural
Behavioral is used primarily for translating the architectural specification to a code that can be simulated
Behavioral is used to explore the authenticity and feasibility of the chosen implementation
RTL describes and infers the structural components and their connections
RTL describes the functionality of the design and is synthesizable to produce the structural netlist

11. Dynamic Simulation
Simulating RTL code is performed to check the functionality of the design
The design is surrounded by a test bench ready for simulation
Test benches are written in behavioral HDL (Verilog or VHDL)
Purpose of test bench is to provide necessary stimuli to the design
Coverage of the design is dependant on the number of tests performed and the quality of the test bench

12. Dynamic Simulation RTL simulation doesn’t consider component timing
To minimize the differences between RTL and gate level simulation, delays are added into the RTL source code
Test Bench
Top Level A B
Resultant Outputs
Input Stimuli C D

13. Constraints and Synthesis
In the past, HDLs were used for logic verification, Designers manually translated HDL into schematics and draw the interconnections
Synthesis tools renders the manual tasks obsoletes
Synthesis reduces the RTL to a gate level netlist
Synthesizing a design is an iterative process starting with the timing constraints definition
Timing constraints define the relationship of each signal with the clock input for a particular block

14. Constraints and Synthesis
Synthesis also needs a file specifying the environment (e.g. technology libraries)
Synthesis produces a gate level netlist from the RTL code using a cell library, timing constraints, and environment variables
RTL Code
Cell library
Environment & timing constraints
Synthesis
tool
Gate level netlist

15. Design for Test
Most designs incorporate design-for-test (DTF) logic to test functionality after the chip is fabricated
DFT
Memory BIST (built-in-self-test): synthesizable RTL based upon controller logic and incorporated in the design before synthesis
Scan insertion: maps the RTL directly to scan-flops, before linking them in a scan-chain
Boundary scan (JTAG): used for test the board connection without unplugging the chip from the board

16. Formal Verification
Performs a validation of a design using mathematical methods
Checks for logic functions of a design by comparing it against the reference design
Formal methods verifies the design by proving that the two descriptions are logically equivalent
Validates RTL against RTL, gate level against RTL, and gate level against gate level

17. Static Timing Analysis
Allows the user to exhaustively analyze all critical paths of the design
Provides information about capacitive loading (fanout)
It is an iterative process