1. Lecture 2 Interrupts

2. I/O devices Usually includes some non-digital component.
Typical digital interface to CPU:
status
reg
CPU
mechanism
data
reg
Data reg - holds values that are treated as data by the device, such as the data read or written by a disc.
Status reg – provides information about the device’s operation, such as whether the current transaction has completed.

3. Application: 8251 UART
Universal asynchronous receiver transmitter (UART) : provides serial communication.
8251 functions are integrated into standard PC interface chip.
Allows many communication parameters to be programmed.

4. Serial communication Characters are transmitted separately: no char
bit 0
bit 1
bit n-1
...
start
stop
time
One character

5. Serial communication parameters
Baud (bit) rate (=1/period of one bit)
Number of bits per character (5-8)
parity/no parity (whether parity to be included)
Even/odd parity (if parity included, its value)
Length of stop bit (1, 2 bits).

6. 8251 CPU interface status (8 bit) 8251 CPU xmit/ rcv data serial port

7. Interrupt I/O Busy/wait is very inefficient.
CPU can’t do other work while testing device.
Hard to do simultaneous I/O.
Interrupts allow a device to change the flow of control in the CPU – allow parallelism.
Causes subroutine call to handle device.

8. Interrupt interface intr request status reg CPU intr ack mechanism IRPC
data/address
data
reg

9. Interrupt behavior Based on subroutine call mechanism.
Interrupt forces next instruction to be a subroutine call to a predetermined location.
Return address is saved to resume executing foreground program.

10. Interrupt physical interface
CPU and device are connected by CPU bus.
CPU and device handshake:
device asserts interrupt request;
CPU asserts interrupt acknowledge when it can handle the interrupt.

11. Debugging interrupt code
What if you forget to change registers?
Foreground program can exhibit mysterious bugs.
Bugs will be hard to repeat---depend on interrupt timing.
Interrupt never occurs in the middle of instruction execution, but before it or after it.

12. Priorities and vectors
Two mechanisms allow us to make interrupts more specific:
Priorities determine what interrupt gets CPU first.
Vectors determine what code is called for each type of interrupt.
Mechanisms are orthogonal: most CPUs provide both.

13. Prioritized interrupts
device 1
device 2
device n
interrupt
acknowledge
L1 L2 .. Ln
CPU
If all devices ask interrupt simultaneously,
only the highest priority receives it

14. Interrupt prioritization
Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete.
Non-maskable interrupt (NMI): highest-priority, never masked.
Often used for power-down.

15. Example: Prioritized I/O
:interrupts
:foreground :A :B :C B C A
A,B

16. Interrupt vectors
Allow different devices to be handled by different code.
Interrupt vector table:
Interrupt
vector
table head
handler 0
handler 1
handler 2
handler 3
© 2000 Morgan Kaufman

17. Interrupt vector acquisition
Activity on the bus
:CPU
:device
Receive interrupt
request
Receive
ack
receive
vector

18. Generic interrupt mechanism
continue
execution
intr?
Assume priority selection is handled before this point. N Y
intr priority > current priority? N
ignore Y
ack Y
bus error Y N
timeout?
vector? Y
call table[vector]

19. Interrupt sequence CPU acknowledges request. Device sends vector.
CPU calls handler.
Software processes request.
CPU restores state to foreground program.

20. Sources of interrupt overhead
Handler execution time.
Interrupt mechanism overhead.
Register save/restore.
Pipeline-related penalties (branch penalty)
Cache-related penalties.

21. Interrupts on MSP-430

22. Maskable interrupts
Caused by peripherals with interrupt capability including watchdog.
Each interrupt source can be enabled/disabled by the correspondent bit in the status register.

23. Non-Maskable Interrupt
There is no need to mask the interrupt.
The interrupt is reseted automatically and then set again.

26. Interrupt vector table

27. Watchdog timer Watchdog timer is periodically reset by system timer.
If watchdog is not reset, it generates an interrupt to reset the host.
host CPU
interrupt
watchdog
timer
reset

28. Preprocessor directives
In C and C++, the language supports a simple macro preprocessor. Source lines that should be handled by the preprocessor, such as #define and #include are referred to as preprocessor directives.
Another C construct, the #pragma directive, is used to instruct the compiler to use pragmatic or implementation-dependent features