1. 3D CMOS monolithic 3-bit resolution pixel sensor with fast digital pipelined readout Olav Torheim, Yunan Fu, Christine Hu-Guo, Yann Hu, Marc Winter on behalf of IPHC (Strasbourg)
Outline
3DIT improves MAPS performances
A 12 µm pitch pixel CMOS MAPS for the ILC vertex detector using 3DIT
3D rolling shutter CMOS MAPS with fast digital pipelined readout
Analog tier: sensor, preamplifier and pixel-level ADC
Digital tier : SRAMs and data sparsification circuitry
Conclusions

2. Using 3DIT to improve MAPS performances
3DIT are expected to be particularly beneficial for MAPS :
Combine different fabrication processes
 Split charge collection and signal processing functionalities
 Use best suited technology for each tier :
Tier-1: charge collection system  Thin epitaxial charge collection layer X0 
Tier-2: analogue signal processing Low Ileak, process, N metal layers shields from digital.
Tier-3: digital signal processing & data transmission
Resorb most limitations specific to 2D MAPS
Dead surface 
Power consumption
Readout speed …
2009: run in Chartered/Tezzaron technology
3D consortium: coordinated by Fermilab
Digital
Analog
Sensor
~ 50 µm
22/06/ VLSI Workshop in Paris

3. A 12 µm pitch CMOS MAPS in 3DIT for the ILC vertex detector
Delayed R.O. architecture for the ILC Vertex Detector (designed & submitted)
Trial 3D architecture based on small pixel pitch, motivated by :
Single point resolution < 3 μm with binary output
Probability of > 1 hit per train per pixel << 10 %
12 μm pitch :
sp ~ 2.5 μm
Probability of > 1 hit/train/pixel < 5 %
3D 2-tier process
Tier-1: A: sensing diode & amplifier, B: shaper & discriminator
Tier-2: time stamp (5 bits) + overflow bit & delayed readout
 Architecture prepares for 3-Tier perspectives : 12 µm
Tier-1: CMOS process adapted to charge collection
Tier-2: CMOS process adapted to analogue & mixed signal processing
Tier-3: digital process (<< 100 nm ?)
~1 ms
~200 ms
Acquisition
Readout 
sp : ~ 2.5 μm
Tint : ~ 31 µs
Pow : ~ 3.47 W/cm2
(instantaneous power)
Detection diode
or Q injection
Amplifier
Amp.+Shaper
Discriminator
Hit identification
12 µm
24 µm
5 bits (7) time stamp
2nd hit flag
Readout
Tier 1
Tier 2 A B +
& Amp
ASD
TS & R.O.

4. 3D Rolling Shutter MAPS with fast pipelined digital readout
3D MAPS with fast pipelined digital readout aiming to improve spatial resolution and time resolution and to minimize power consumption
(R&D in progress)
Subdivide sensitive area in ”small” matrices running individually in rolling shutter mode
Adapt the number of rows to required frame readout time
 few µs r.o. time may be reached
Design in ~ 25 µm²:
Tier 1: Sensor & preamplifier + 3-bit pixel-level ADC (LSB ~RMS noise,15~20 e-)
Tier 2: SRAMs + Fast pipeline readout circuitry with data sparsification
sp < 2.5 μm Tint. ~ 7 µs
Pow ~ 0.73W/cm2
(compromise of
time res. and power) 
~ 25 µm
Detection diode+Amplifier
+Pixel-level ADC
Delay+SRAMs +
Sparsification

5. 3D Rolling Shutter Mode Digital Pixel Sensor Circuitry
Block diagram of the 3D integrated Rolling Shutter Binary Pixel (RSBPix) architecture with in-pixel amplification, double sampling, digitization and in-pixel digital circuitry.
Feedback
Analog Tier #
Digital Tier #
Vclp SF
Clamp
soff < 15 mV
Vdd
Vref CS
Preamp
Track
Discrimination n+
MOSCAP
Auto-zeroed
N-well
MiMCAP
Comparator
P-epi
Chip-level analog
ramp generator
P-sub
Track
Auto-zeroed
Chip-level
Counter
SRAM
Vref
S ~ 50 MHz
Negative feedback  Stabilizes the operating point of the amplifier and robust against process mismatches
In-Pixel offset-compensated Multi-Stage Amplifier  High gain, low offset voltage
Auto-zeroed comparator  Low power, low offset voltage
Digital front-end  Fast pipeline digital readout, data sparsification
Digital Front-end
(data sparsification)
Digital output / X.Y Address

6. Token-compliant rolling shutter mode
Sub-array 1
Sub-array n
Token
Row buffers
Phase1
Phase2
( upper half )
( lower half )
Token-compliant rolling shutter mode  the tokens must be injected into the upper half while hits are injected into the lower half, and vice versa:
Time resolution = TPhase1 + TPhase2
Parallel data sparsification  Time resolution   Tint ~ 7 µs (adjustable)
“M” rows in each sub-array  M = Tint / (T A-to-D + TRESET)
Row buffers  Store the information of the hits in each row

7. Details of the Digital Front-end
VDD
Logic A
3-bit
data
Reset
Token_CLK
Logic B
Enable
000
111 1
Cell 0
Cell 1
Cell (M-1)
Cell M
Token_in
011 A B
NAND
NOR D Q
Token_in
Token_CLK
Reset
3-bit data
Enable
Logic A A
Token_in D Q
Token_CLK B
Reset
3-bit data
Enable
Token_in
Logic B
A token passes through a chain of intertwined NAND and NOR digital pixel cells
 To minimize delay time of token passing
“Enable” signal  Select signal for placing pixel address and 4-bit ADC value at shared row bus
Row buffers (Hits counter + shift registers) successively store hit information placed at row bus.

8. Row buffers
Cell 0
Cell 1 ….
Cell510
Hits counter
Buffer 1
Cell 2
Cell511
Token
Buffer N-2
(Cell 511)
Buffer N-1
(Cell 2)
Buffer N
(Cell 1)
3 Hits
(Cell 0)
2 Hits
(Cell 510)
1 Hit
Row0
Row1
RowM .…
For every token clock cycle, the content on the line data bus is stored into the leftmost buffers, with the content of all the buffers being shifted from one buffer to the next, A hits counter increments the number of valid hits as long as the token injected into the row has not been returned.
Number of buffers must be adopted to hit density of experiment:
Low value of the background ( 3 hits/ cm2 / BX) , cluster multiplicity 6 “N” Buffers = 18
High value of the background (15 hits/ cm2 / BX), cluster multiplicity 6  “N” Buffers = 30

9. Pipeline readout mode Sub-array 1
Phase2
Phase1
Token
Rolling shutter
Sub-array 1
Row buffers
( upper half )
( lower half )
Row M
Row 0
Row 1
Row 2
Mux
FSM
FIFO
3-bit digital data
X / Y address
write
read
Rolling
shutter
Pipelined readout of Row buffers  The row buffers in upper half are operated in pipelined scan mode while new hits are injected into the buffers of lower half, and vice versa:
Finite State Machine (FSM)  Reads content of each line before advancing the pipeline.
Due to pipelined operation, no upper limit on hits per line (like in MIMOSA26), only upper limit on hits per frame (dependent on FSM operating frequency).

10. Binary discriminated pixels / distributed hit pattern encoding
Patterns of hits in each line coded as states
Similar to MIMOSA26 but...
Algorithm moved from periphery and distributed into individual pixels.
 Higher time resolution.
 Covers higher hit density.

11. Distributed hit pattern encoding
State encoding logic must be minimized in order to fit into each pixel cell:
State encoding implemented as priority encoder
Simplified logic for nonredundant state identification

12. Conclusion and perspectives
A 12 µm pitch pixel 3D 2-tier CMOS MAPS with delayed and full serial readout architecture has been designed and being fabricated.
Sensor, front-end electronics and 5-bit TDC (Tint=31µs).
Full serial read-out speed : ~100 MHz.
But in order to further improve the single point resolution, time resolution (< 10 us) and save power consumption:
A new architecture of 3D rolling shutter CMOS MAPS with fast pipelined digital readout is proposed:
Tier 1 : Sensor & preamplifier + 3-bit pixel-level ADC (LSB ~RMS noise,15~20 e-)
Tier 2: SRAMs + Fast pipeline readout circuitry with data sparsification