Elia Conti on behalf of the RD53 Collaboration

Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS pixel upgrades
Elia Conti on behalf of the RD53 Collaboration 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA

Radiation qualification The RD53A demonstrator
OUTLINE Introduction Radiation qualification The RD53A demonstrator Floorplan and design flow Power Analog front-ends Digital matrix Digital chip bottom Analog chip bottom RD53A verification Conclusion

Introduction (I) Next generation of silicon pixel detectors for phase-2 upgrade of ATLAS and CMS experiments at HL-LHC (~ ) sets unprecedented design requirements High granularity  small pixels (50x50 µm2 / 25x100 µm2) Large chips (~2x2 cm2, ~109 transistors) High occupancy (pileup ~200)  3 GHz/cm2 hit rate Radiation tolerance for innermost layers: 2x1016 neq/cm2, 1 Grad TID RD53 Collaboration: focused R&D developing pixel chips for ATLAS/CMS upgrades (baseline technology: 65 nm) Extensive radiation testing to determine how best to obtain sufficient radiation hardness Tools and methodology to efficiently design large complex mixed signal chips dedicated simulation and verification framework Developed and tested many test structures, building blocks and small pixel arrays shared rad-hard IP library (analog front-ends, calibration circuit, bandgap, DAC, ADC, PLL, serializer, cable driver, serial I/O, serial power regulator, on-chip monitoring) radiation test structures (transistor arrays, analog circuits, digital libraries) two small scale (64x64) prototypes: FE65-P2 (see presentation by Timon Heim), CHIPIX65 (see presentation by Luca Pacher) Design and characterization of full scale demonstrator pixel chip: RD53A 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

RD53A size: 20 x 11.8 mm2  400 columns x 192 rows, 50 x 50 µm2 pixels
Introduction (II) RD53A is intended to demonstrate in large format IC the suitability of the chosen 65nm CMOS technology for HL-LHC upgrades of ATLAS and CMS radiation tolerance stable low threshold operation high hit and trigger rate capabilities RD53A size: 20 x 11.8 mm2  400 columns x 192 rows, x 50 µm2 pixels RD53A is not intended to be a ﬁnal production chip for use by the experiments contains design variations for testing purposes wafer scale production will enable prototyping of bump bonding assembly with realistic sensors in new technology  performance measurement forms the basis for production designs of ATLAS and CMS: architecture designed to be easily scalable to a full scale chip Submitted: end of August 2017 (shared engineering run with CMS MPA/SSA chips for cost sharing) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Extensive irradiation campaign in past 3 years
Preparatory work – Radiation qualification (I) Extensive irradiation campaign in past 3 years transistor arrays analog circuits digital test chip Significant radiation damage above 100 Mrad analog: transconductance, Vth shift digital: speed degradation Short and narrow channel effects (RISCE, RINCE) strongly depend on temperature during irradiation and bias conditions of devices less damage when irradiating at low temperature (-20 °C) worst case bias : VGS = VDS = 1.2 V (diode connected) some recovery observed at low and room temperature annealing but high temperature annealing with bias introduces high Vth shift Investigations at single transistor level on sensitivity to various parameters (NMOS vs PMOS, W/L, temperature, bias, during irradiation / during annealing…) RISCE is dominant for the NMOS devices High temperature annealing (100 °C for 7 days) For the RD53A, this temperature effect can be avoided by keeping the system : In cold environment : -20°C for 5 years Unbiased at room temp for few months 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Digital libraries: DRAD chip [Jara Casas et al., JINST, 2017]
Preparatory work – Radiation qualification (II) Realistic to stand 500 Mrad with conservative design approach (inner barrel layer can be replaced after 5 yrs) Conservative transistor simulation models for behavior after 200 and 500 Mrad dose (worst case bias, irradiation at room temperature) for circuit simulations and optimizations Analog circuits appropriately designed (large transistors) and then simulated with 500 Mrad corner model Digital libraries: DRAD chip [Jara Casas et al., JINST, 2017] study effect of radiation on digital standard cells in 65nm test efficiency and validity of digital simulations with irradiation corner model Simulation results agree with irradiation tests but the model overestimates TID damage level NOR gates should be avoided due to strong degradation Large devices  better time margins Test results used to decide which timing corner to use for RD53A design DRAD: joint effort between RD53, MPA and LP-GBT What to test: speed degradation and power consumption of a subset of the digital library from the foundry and of modified libraries with larger transistor (which should reduce performance degradation) Motivation Radiation damage is severe in short and narrow channel. Most of the standard cells in digital libraries use minimum length transistor (L = 60 nm) and small width (W ~200 nm) What will effective performance degradation be of digital circuits at +100 Mrad? Will special/modified libraries be needed for high rad and/or high speed? substrate contacts 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

RD53A specifications [CERN-RD53-PUB-15-001]
The RD53A demonstrator RD53A specifications [CERN-RD53-PUB ] Technology 65 nm CMOS Pixel size 50 x 50 um2 Pixels 192 x 400 = (50% of production chip) Detector capacitance < 100fF (200fF for edge pixels) Detector leakage < 10nA (20nA for edge pixels) Detection threshold < 600e- In-time threshold < 1200e- Noise hits < 10-6 Hit rate < 3 GHz/cm2 (75 kHz avg. pixel hit rate) Trigger rate Max 1 MHz Trigger latency 12.5 us Hit loss at max hit rate (in-pixel pile-up) ≤ 1% Charge resolution ≥ 4 bits ToT (Time over Threshold) Readout data rate Gbits/s = max 5.12 Gbits/s Radiation tolerance 500Mrad, 1 x Mev eq. n/cm2 at -15 oC SEU affecting whole chip < 0.05/hr/chip at 1.5GHz/cm2 particle flux Power consumption at max hit/trigger rate < 1W/cm2 including SLDO losses Pixel analog/digital current 4 uA / 4 uA Temperature range -40oC ÷ 40oC 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Analog Chip Bottom (ACB)
RD53A floorplan and organization (I) 120 µm Top pad row (debug) Analog BIAS Digital lines Analog BIAS Digital lines Digital lines Analog BIAS Sensitive area 192 rows x 400 columns 9.6 mm Bias Bias MacroCOL Bias MacroCOL Bias MacroCOL Bias 70 m Analog Chip Bottom (ACB) Digital Chip Bottom (DCB) ~ 1.5 mm ADC Calibr. Bias DACs CDR/PLL POR Sensors Ring osc. The sensitive area of the chip is placed at the top of the chip and is arranged as a matrix of 192 x 400 pixels of 50 µm × 50 µm. At the top is a row of test pads for debugging purposes The peripheral circuitry is placed at the bottom of the chip and contains all global analog and digital circuitry needed to bias, conﬁgure, monitor and readout the chip. The wire bonding pads are organized as a single row at the bottom chip edge In the chip periphery, all the analog building blocks are grouped in a macroblock called Analog Chip Bottom (ACB), which is fully assembled and characterized in an analog environment All the building blocks have been previously prototyped, tested and characterized in radiation environment at least up to 500 Mrad TID. The ACB block is surrounded by a synthesized block, called Digital Chip Bottom (DCB), which implements the Input, Output and Conﬁguration digital logic ShLDO_An ShLDO_Dig ShLDO_An ShLDO_Dig Driver/Rec ShLDO_An ShLDO_Dig ShLDO_An ShLDO_Dig ~ 270 µm Padframe RD53A metal stack: 9 metal layers + 28K AP layer RD53A uses standard Vt 9-track library (tcbn65lp) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

RD53A floorplan and organization (II)
50x50 μm2 pixel floorplan 50% Analog Front End (AFE), 50% digital cells Pixel array built up of 8x8 pixel cores  16 analog “islands” (quads) embedded in a flat digital synthesized “sea” A pixel core can be simulated at transistor level with analog simulator All cores (for each FE flavour) are identical  hierarchical verifications AFE Digital logic 35 15 PIXEL ANALOG QUAD PIXEL CORE 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

(RTL/Innovus/Verilog)
RD53A design flow: Top level integration PIXEL ARRAY Analog front-end (Virtuoso/ADE-XL) PIXEL CORE (8x8) (RTL/Innovus/Verilog) (DRC/LVS) LEF/LIB OA Analog Chip Bottom (Virtuoso/ADE-XL) PADFRAME (Virtuoso/ADE-XL) LEF/LIB LEF/LIB LEF/LIB Digital Chip Bottom (RTL/Verilog) RD53A Top Level (RTL/Innovus/Verilog) RTL gds VCD stimuli to an. blocks .v, .vams Calibre DRC/LVS RD53A Simulation VEPIX53 (System Verilog/UVM) BDAQ53 (Python) (see Marco Vogt’s presentation) Verilog AMS (Wreal) HSIM gds Tapeout 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

(see presentation by Stella Orfanelli)
Power RD53A designed to operate with serial powering  constant current to power chips/modules in series 2 internal voltage rails: analog (VDDA) and digital (VDDD) Based on ShuntLDO regulator:Low Drop-Out linear voltage regulator + shunt regulator 2 ShuntLDOs (analog, digital internal rails) and 4 active pads associated with each The extreme rate requirements for the PROC necessitate the use of a modern high density low power CMOS technology with low supply voltage (1.2 V), resulting in a pixel chip that must be supplied with significant current levels (2.2 A per chip). The use of a classical passive parallel powering system is excluded for such high currents. The use of local DC-DC power conversion has also been excluded because of the extremely hostile radiation environment and very tight constraints on space and material budget. A serial power distribution system has been found to be the only viable scheme to supply the Inner Tracker with the required power, within an acceptable material budget and with acceptable power cable losses. The pixel chip, implemented in a modern 65 nm CMOS technology, requires significant current levels of about 2 A per chip to cope with the very large number of pixels and the high hit and trigger rates. The power distribution system must be low mass to minimize interactions of particles with the material. High radiation and magnetic field levels combined with extremely tight space constraints prevents the use of a more classical DC-DC power conversion within the pixel volume. The regulator can be configured as a pure Low Drop-Out linear voltage regulator for usage in a conventional voltage based supply scheme. In addition, the regulator provides dedicated shunt circuitry which can be enabled for application in a current based serially powered supply scheme. The ShuLDO control circuit ensures that the external supply pad sinks a constant input current independent of the internal circuit consumption, and generates a regulated output voltage (V_rail) to the chip interior The ShuLDO control circuit is common to all the power pads feeding the same rail. Any excess current not needed by the chip internal circuits is shunted to ground, with the sum of chip core and shunt currents remaining constant. (see presentation by Stella Orfanelli) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Synchronous FE Linear FE Differential FE
Pixel Array – Analog front-ends (I) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Linear FE Differential FE 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (I) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Linear FE Differential FE Single stage Charge Sensitive Ampliﬁer AC coupled to synchronous comparator Baseline “auto-zeroing” scheme  no threshold trimming needed Latch can be turned into local oscillator up to 800 MHz for fast ToT counting 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (I) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Linear FE Differential FE Linear pulse ampliﬁcation stage with current comparator and ToT counter 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (I) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Linear FE Differential FE Continuous reset integrator first stage + DC-coupled pre-comparator stage with differential threshold circuit 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Digital n-well guard ring closed: analog quad isolated from “outside”
Pixel Array – Analog front-ends (II) Post-layout simulations (*except Diff.: schematic level sim): CD=50 fF, T=27 °C, Qth=600 e- In-time overdrive relative to Qin=30 ke- Time walk  Qin=1200 e- (relative to a Qin=30 ke-) ToT  Qin = 6 ke- 1 5.1 uA including latch Analog front-ends main features Sync. Lin. Diff.* spec Charge sensitivity [mV/ke-] 43 25 103 - ENC rms [e-] 67 83 53 <<126 Threshold dispersion σ(Qth) rms [e-] 93 32 20 √(ENC2 + σ(Qth)2) [e-] 115 89 54 ≤126 In-time overdrive [e-] ≤50 ≤100 ≤ 600 Current consumption [µA/pixel] 3.31 4.3 3.5 ≤ 4 Time over threshold [ns] 121 99 118 < 133 Analog deep n-well nMOS connected to analog ground GNDA Digital deep n-well nMOS connected to digital ground GNDD 35um PRBoundary Digital N-well guard ring (biased by VDDD) Analog N-well guard ring (shorted to VDDA) global p-substrate (VSUB) Digital n-well guard ring closed: analog quad isolated from “outside” 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel array logic organization
Pixel Array – Digital matrix (I) Pixel array logic organization Basic layout unit: 8x8 digital Pixel Core  synthesized as one digital circuit Pixel Core contains multiple Pixel Regions (PR) and some additional arbitration and clock logic Each Pixel Core receives all input signal from the previous core (closer to Digital Chip Bottom) and regenerates the signals for next core Timing critical clock and calibration injection signals are internally delayed within the core relative to the regenerated ones to have a uniform timing (within 1-2 ns) 192x400 pixels 8x8 pix 1x4 pixel region 4x4 pixel region OR 8x8 Pixel Core Digital Chip Bottom The digital core handles all processing of the binary outputs, including masking, digital injection, ToT counting, storage of ToT values, latency timing, triggering and readout. The timing critical clock and injection edge signals are internally delayed within the core relative to the regenerated ones so that when all the cores are integrated there is uniform timing (within 2 ns) of those signals within all cores. To achieve this uniformity there are multiple core delay values used in RD53A, with the largest (smallest) delay used in the top (bottom) third of the matrix. Other than this delay value, all cores of the same flavor are identical. 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Centralized Buffering Architecture (CBA)
Pixel Array – Digital matrix (II) Pixel Regions contain trigger latency buffering (most efficient architectural solution in order to handle very high hit rate) Architecture exploration from initial statistical study (2013) to behavioral parameterized pixel array model: two different buffering architectures ( ), eventually implemented into small scale prototypes Centralized Buffering Architecture (CBA) 4x4 pixel region implemented into CHIPIX65 Storing hit information locally in array from multiple hits from the same cluster together translates into significant savings in required storage resources Architecture exploration was focused on investigating optimal sharing strategy of digital logic Distributed Buffering Architecture (DBA) 2x2  1x4 pixel region based on ATLAS FE-I4 implemented into FE65_P2 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Comparative study DBA-CBA:
Pixel Array – Digital matrix (III) VEPIX53: simulation and verification environment (UVM) supporting design from initial architectural modeling to final verification generation of different kinds of input stimuli (internally generated or from Monte Carlo) automated verification features Pixel array architecture performance metrics: hit loss and latency buffer occupancy Comparative study DBA-CBA: at behavioral level at RTL from small scale prototypes Comparable performance found between CBA and DBA architectures in terms of buffer overflow hit loss Result of the study motivated further optimizations implemented into RD53A addressing design limitations  all differences solved 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Digital Chip Bottom Pixel Matrix
Digital Chip Bottom (DCB) (I) Serial input stream (custom protocol) CDR/PLL Channel Sync Command Decoder Global Config JTAG Serializ. Aurora 64b/66b Data Builder Digital Chip Bottom Analog Chip Bottom Pixel Matrix Data_in Data_out CMD_clk (160 MHz) BX_clk (40 MHz) RX_Data[15:0] Decoded commands Pixel Data Register data To_Serializer [19:0] SER_out SER_clk (1.28 GHz) 1/2/4 CML outputs @ 1.28 Gbps Aurora 64/66 (Xilinx) Fine delay clock (640 MHz) Readout proceeds with column-parallel token chain one trigger at a time 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Mean time between errors
Digital Chip Bottom (DCB) (II) Configuration: 9-bit address, 16-bit data Global configuration: 9-bit address, 16-bit data Pixel configuration: up to 8-bit data per pixel, R/W done on pixel pairs SEU tolerance strategy SEU tolerant dual interlocked (DICE) latches with interleaved layout designed and irradiated: 9x more tolerant than single latch  not sufficient Triple Modular Redundancy (TMR) consumes area and not compatible for pixel configuration  used for global configuration Solution for pixel configuration: simple DFF with trickle configuration (frequent data refresh cycles) To be refined, extended and have SEU simulations for final chips Mean time between errors Area/bit (without ctrl logic) Pixel config (1.28 Mbit/chip) Global config (1 kbit/chip) Single latch 55 ms 71 s 5 um2 DICE 0.5 s 639 s 11.6 um2 TMR 209 s 74 h 700 um2 Memory in the data path is not protected, because the amount of corruption expected during the time that hit data spends in chip memory (less than 20 µs) is much less than the speciﬁed 1% hit loss. With a single bit upset cross section of 5×10−14 cm2 and an estimated rate of particles above upset threshold of 500 MHz/cm2, even taking the extreme case that every single upset corrupts an entire 64-bit Aurora frame, the calculated fraction of lost hits in 20 µs is 3 × 10−8. Control paths are protected with triple redundancy of circuits such as counters, and/or deglitching of controls signals. 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Analog Chip Bottom (ACB)
Multi-purpose macroblock containing all analog IPs, assembled in analog environment (Virtuoso) and simulated with analog and mixed-signal simulator Provides 4 µA current reference to current DACs, regulated in order to compensate for process variations Monitors different quantities (temperature, total dose, currents/voltages) in different parts of the chip, digitized by 12-bit ADC Provides global analog front-end bias and calibration circuit voltage levels All IPs previously thoroughly tested, also from the standpoint of radiation tolerance before integration in RD53A chip Macrocol_Bias_Sync Macrocol_Bias_Lin Macrocol_Bias_Diff DACs Diff Lin Sync Ring osc. PLL CML CDR/PLL Mon-Cal-Iref Temp. sens (ShLDO_DIG) (ShLDO_AN) (4th Temp. sensor on top of array) It covers the full area between pixel array and PADFRAME: 20 mm x 1.5 mm Connections with Pixel Array and PADFRAME by simple abutment The empty space between blocks is filled by Digital Chip Bottom std. cells Analog lines shielded when crossing digital lines 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Also support directed test pattern generation
RD53A Verification (I) VEPIX53 UVM verification components (UVC) allowing for reusability and automated verification functions Also support directed test pattern generation Interface verification components (UVCs): Hit (sensor pixel hit data) Command (custom input protocol for control and trigger) Aurora, HitOr (monitor pixel chip output) Module UVCs: Pixel array UVC (reference models, scoreboard, lost hits classifier) Channel Sync and Command Decoder UVC (monitor, checker) Planned: configuration register model (automatic configuration register verification), SEU injection 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Verification approach:
RD53A Verification (II) Verification approach: Constrained-random tests  functional coverage collection Based on generation of constrained-random inputs Automated pixel array verification Directed tests  specific test cases aimed to verify single functions and unlikely perturbations Custom command sequences Extreme hits/triggers No extensive tests So far tests checked manually (eManager logs and Simvision waveforms for debug) Generation of stimuli for analog simulations Example of test regression run at each design iteration (RTL and gate-level, 3 timing corners) Pros Architecture exploration before the actual design has been very useful for understanding how to organize and dimension buffering logic It was possible to assess the improvement in performance at different steps for meeting specifications Constrained-random verification allows us to detect hard to find bugs especially those related to data path which show only when simulating at operating conditions Cons Significant time spent on architecture study  less familiarity with actual chip verification Few people working on verification (2 main engineers at first, others coming and going) Digital designers underestimating verification building and integrating complex testbench takes lot of time most of designers were reluctant to participate and preferred sticking to their own block-based Verilog testbench with directed test patterns insertion of custom command sequences as a compromise for meeting project deadline Block / Function Test type Global configuration readback Directed Hit or data path Constrained-random Triggered data path Calibration injection hits Pixel configuration readback 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Preparation for chip testing already ongoing
Conclusion The goal of the RD53A chip is to demonstrate feasibility of 65 nm technology with respect to the challenging requirements set by the future experiment upgrades at the HL_LHC RD53A puts into practice guidelines elaborated by RD53 over the years (radiation tolerance, architecture exploration, floorplan, design flow, serial powering, verification) and used IP library developed, prototyped and tested  different analog front-end flavors and digital pixel array architectures coexisting on the same chip RD53A submitted at end of August on shared engineering run, expecting delivery ~November Preparation for chip testing already ongoing RD53 in agreement with upgrade management of experiments is formally proposing to make final chips for ATLAS and CMS select front end variant, increase pixel matrix size, additional functionality according to experiment specs further optimization (power, architecture, SEU immunity) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

THANK YOU FOR YOUR ATTENTION
RD53A design team Flavio Loddo (Bari) Tomasz Hemperek (Bonn) Roberto Beccherle (INFN PI) Elia Conti (CERN) Francesco Crescioli (Paris) Francesco De Canio (INFN BG-PV) Leyre Flores (Glasgow) Luigi Gaioni (INFN BG-PV) Dario Gnani (LBNL) Hans Krueger (Bonn) Sara Marconi (CERN / INFN PG) Mohsine Menouni (CPPM) Sandeep Miryala (FNAL) Ennio Monteil (INFN TO) Luca Pacher (INFN TO) Andrea Paternò (INFN TO) THANK YOU FOR YOUR ATTENTION The RD53 Collaboration Bonn CERN Marseille CPPM FNAL LBNL Paris LPNHE New Mexico INFN (Bari, Milano, Padova, Bergamo-Pavia, Pisa, Perugia, Torino) NIKHEF Prague IP-FNSPE-CTU RAL-STCF Seville

BACKUP

Corners for RD53A Only for digital TypRo1 TypRo2 TypRo3 TypOp1 TypOp2
LV Op1 LVOp2 LV Ro1 LV Ro2 FF LT FF HT SS HT SS LT 200 Mrad 500 Mrad Model TT FS SF FF SS 200Mrad 500Mrad VDD 1.2 1.08 1.32 0.9 T 27 -20 -40 40 80 Only for digital 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_1) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Single stage with SAR-like ToT counter using synchronous comparator Linear FE Single stage with current comparator and ToT counter Differential FE Continuous reset integrator first stage + DC-coupled pre-comparator stage Single stage Charge Sensitive Ampliﬁer with Krummenacher feedback AC coupled to synchronous discriminator (offset compensated Differential Ampliﬁer (DA) + positive feedback latch) Baseline “auto-zeroing” scheme  no threshold trimming needed Latch can be turned into local oscillator up to 800 MHz using asynchronous logic feedback loop  Fast ToT counting 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_2) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Single stage with SAR-like ToT counter using synchronous comparator Linear FE Single stage with current comparator and ToT counter Differential FE Continuous reset integrator first stage + DC-coupled pre-comparator stage Linear pulse ampliﬁcation stage with current comparator and ToT counter Single amplification stage for minimum power dissipation Krummenacher feedback to comply with expected large increase in detector leakage current High speed, low power current comparator Selectable gain 30000 e- maximum input charge, ~450 mV preamplifier output dynamic range 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_3) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Single stage with SAR-like ToT counter using synchronous comparator Linear FE Single stage with current comparator and ToT counter Differential FE Continuous reset integrator first stage + DC-coupled pre-comparator stage Preampliﬁer: continuous reset and adjustable gain (two possible values of feedback capacitance), can operate at very low currents DC-coupled pre-comparator stage: additional gain and differential threshold circuit Global threshold adjustable through two distributed voltages, trimmed in each pixel using one 4-bit resistor ladder in each pre- comparator branch. Continuous time comparator stage with output connected to digital pixel region through logic gates Optimized for low-threshold operation (~500e- ) Current consumption: 4 µA/pixel at 50 fF detector load and 10 nA leakage current 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_4) 3 different analog front-end designs for performance comparisons with same layout area Easily interchangeable on the pixel array Common calibration injection circuit for direct performance comparison 128 columns (16 core columns) 136 columns (17 core columns) Synchronous FE Linear FE Differential FE Local generation of analog test pulse from 2 defined DC voltages (CAL_HI, CAL_ME) distributed to all pixels and a 3rd level (local gnd) Two operation modes allowing to generate 2 consecutive signals of same polarity or to inject different charges in neighboring pixels at same time Control signals S0 and S1 generated in digital domain and can be phase shifted with ﬁne delay (global for the whole chip) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Fast ToT counting with local oscillator
Pixel Array – Analog front-ends (bak_5) Fast ToT counting with local oscillator 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_6)
2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Pixel Array – Analog front-ends (bak_7)
The AFE prototype in FE65_P2 shows significant degradation of its threshold tuning capabilities 0 Mrad 350 Mrad 150 Mrad 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Comparative study DBA-CBA:
Pixel Array architecture study (I) Pixel array architecture performance metrics: hit loss and latency buffer occupancy Comparative study DBA-CBA: at behavioral level at RTL from small scale prototypes DBA to be preferred at behavioral level Comparable performance found between CBA and DBA architectures in terms of buffer overflow hit loss Result of the study motivated further optimizations implemented into RD53A Y AXIS LABELS MISSING Metrics CBA (CHIPIX65) DBA (FE65_P2) Hit loss (%) analog dead time 3.19 0.72 buffer overflow 15 loc.: 0.59 16 loc.: 0.24 8 loc.: 0.74 9 loc.: 0.27 Total hit loss (%) 15 loc.: 3.79 16 loc.: 3.44 8 loc.: 1.46 9 loc.: 0.99 ToT loss (%) 0.10 – 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Implemented DBA architecture
Digital matrix (I) Implemented DBA architecture Shared hit time buffer (latency counters) Independent hit charge buffer in each PUC 8 memory locations 1x4 elongated shape more convenient for buffer occupancy 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Implemented CBA architecture
Digital matrix (II) Implemented CBA architecture Pixels have a latch-based single-row buffer Staging buffer delays hit map for Sync time Clock Cycles (2 rows deep) TOT Compression maps 16 TOTs into 8 slots 16 rows deep timestamp buffer Integrated with Sync analog front-end (Fast ToT) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Digital Chip Bottom (DCB) (bak_1) Serial input stream (custom protocol) CDR/PLL Channel Sync Command Decoder Global Config JTAG Serializ. Aurora 64b/66b Data Builder Digital Chip Bottom Analog Chip Bottom Pixel Matrix Data_in Data_out CMD_clk (160 MHz) BX_clk (40 MHz) RX_Data[15:0] Decoded commands Pixel Data Register data To_Serializer [19:0] SER_out SER_clk (1.28 GHz) 1/2/4 CML outputs @ 1.28 Gbps Aurora 64/66 (Xilinx) Fine delay clock (140 MHz) Different reset procedures for different parts of the chip Data path logic reset with ECR command Active low Power-On Reset (POR) generator powered from digital power internal rail (no brown- out detection) Asynchronous reset for Global Config register, synchronized with CMD_CLK for all other blocks 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Custom serial input protocol
Digital Chip Bottom (DCB) (bak_2) Serial input stream (custom protocol) Custom serial input protocol Clock and commands encoded on a single link DC-balanced with short run length for AC coupling and reliable tx Built-in framing and error detection Continuous stream of 16-bit frames (each frame exactly DC balanced) unique sync frame (data frame alignment for protocol initialization) trigger (15 different patterns) command data command frame = 2 identical command symbols allowing for error correction 7 command types: BCR, ECR, Cal, GlobalPulse, WrReg, RdReg, Null data frame = 2 data symbols encoding 5 bits each  32 data symbols 3 phases: Initialization (Channel Synchronizer lock), Data Transmission and Decoding ChipID associated to commands with data frames: command executed only by the chip with matching geographical address (3 wirebond pads) CDR/PLL Channel Sync Command Decoder Global Config JTAG Serializ. Aurora 64b/66b Data Builder Digital Chip Bottom Analog Chip Bottom Pixel Matrix Data_in Data_out CMD_clk (160 MHz) BX_clk (40 MHz) RX_Data[15:0] Decoded commands Pixel Data Register data To_Serializer [19:0] SER_out SER_clk (1.28 GHz) 1/2/4 CML outputs @ 1.28 Gbps Aurora 64/66 (Xilinx) Fine delay clock (140 MHz) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Output protocol: Aurora 64b66b
Digital Chip Bottom (DCB) (bak_3) Output protocol: Aurora 64b66b All data, messages, and conﬁguration readback serialized with the Aurora protocol and transmitted on 1 to 4 parallel lanes (1.28 Gbps each, programmable) Multilane Aurora protocol using strict alignment: all lanes send same type of Aurora frame (66-bits long) Output stream: ND data frames + 1 register/service frame (ND:1 ratio programmable) Serial input stream (custom protocol) CDR/PLL Channel Sync Command Decoder Global Config JTAG Serializ. Aurora 64b/66b Data Builder Digital Chip Bottom Analog Chip Bottom Pixel Matrix Data_in Data_out CMD_clk (160 MHz) BX_clk (40 MHz) RX_Data[15:0] Decoded commands Pixel Data Register data To_Serializer [19:0] SER_out SER_clk (1.28 GHz) 1/2/4 CML outputs @ 1.28 Gbps Aurora 64/66 (Xilinx) Fine delay clock (140 MHz) Readout proceeds with column-parallel token chain one trigger at a time 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Digital Chip Bottom (DCB) (bak_4) Serial input stream (custom protocol) CDR/PLL Channel Sync Command Decoder Global Config JTAG Serializ. Aurora 64b/66b Data Builder Digital Chip Bottom Analog Chip Bottom Pixel Matrix Data_in Data_out CMD_clk (160 MHz) BX_clk (40 MHz) RX_Data[15:0] Decoded commands Pixel Data Register data To_Serializer [19:0] SER_out SER_clk (1.28 GHz) JTAG module disabled by default (via wire bonding) but if forced externally allows to: Bypass Command Decoder (replace Command Decoder outputs) Fully scan Configuration Register (minimal Scan Chain interface) Spy critical registers (Boundary Scan) 1/2/4 CML outputs @ 1.28 Gbps Aurora 64/66 (Xilinx) Fine delay clock (140 MHz) We need to have a working chip even in case of malfunctioning blocks  we must be able to completely bypass critical blocks CMD_CLK and SER_CLK can be externally bypassed 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

(see Sandeep Miryala’s presentation)
SEU: TMR placement (see Sandeep Miryala’s presentation) 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Analog front-end bias 2-stage structure: Advantages: 2x384
Analog Chip Bottom (ACB) (bak_1) Analog front-end bias 2-stage structure: Global V/I provided by 10-bit current steering DACs in ACB After current scaling biases are distributed to MacroColumnBias cells where final bias is distributed in parallel to 384 pixels (768) of two adjacent columns Advantages: Improved reliability (failure in a pixel involving bias lines affects only 2 columns) Limited effect of leakage current increase with radiation Drawback: increase of mismatch among pixels, (but 1st current mirroring is done with large transistors) All DACs currents can be read back from Monitoring block 2x384 Macrocol Bias 1 Macrocol Bias 2 Macrocol Bias 200 Ref. current generator 4 uA To DACs Mirror 1 Mirror n Iref Mirror Monitoring ADC BGR CDAC 1 CDAC n Global bias in ACB 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

RD53A test preparation RD53A test working group preparing testing
Chips will come in November Test systems being prepared: PC plug-in Hardware: Commercial PCI-E FPGA card Custom FMC adapter card Standalone custom card: Ethernet Single chip card with standardized interface: Command/clock line and Readout link(s) on standard display port cable Power prepared for serial powering Multi-chip hybrids: In the pipeline for later tests Firmware, Software Based on previous experience with FEI4 test systems Pixel sensors being produced in both ATLAS and CMS. Bump-bonding being prepared RD53A dummy wafers and sensors for initial trials 300mm wafer handling in HEP community and BB companies Community getting equipped with 300mm wafer probers Radiation testing Many systems will be used in ATLAS/CMS pixel community 2017 Topical Workshop on Electronics for Particle Physics – Sept , Santa Cruz, CA – Elia Conti (CERN)

Elia Conti on behalf of the RD53 Collaboration

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Elia Conti on behalf of the RD53 Collaboration

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