1. Getting Started with Micriμm’s μC/OS-III Kernel

2. Renesas Technology & Solution Portfolio
In the session 110C, Renesas Next Generation Microcontroller and Microprocessor Technology Roadmap, Ritesh Tyagi introduces this high level image of where the Renesas Products fit. The big picture.
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 NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide
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The wealth of technology you see here is a direct result of the fact that Renesas Electronics Corporation was formed on April 1, 2010 as a joint venture between Renesas Technology and NEC Electronics — Renesas Technology having been launched seven years ago by Hitachi, Ltd. and Mitsubishi Electric Corporation. There are four major areas where Renesas offers distinct technology advantage.
--The Microcontrollers and Microprocessors are the back bone of the new company. Renesas is the undisputed leader in this area with 31% of W/W market share.
--We do have a rich portfolio of Analog and power devices. Renesas has the #1 market share in low voltage MOSFET solutions.
--We have a rich portfolio of ASIC solution with an advanced 90nm, 65nm, 40nm and 28nm processes. The key solutions are for the Smart Grid, Integrated Power Management and Networking
--ASSP: Industry leader for USB 2.0 and USB 3.0. Solutions for the cell phone market
-- Memory: #1 in the Networking Memory market
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3. Agenda Introduction Lab 1 Foreground/Background Systems
Kernel-Based Applications
Initiating Multitasking
Lab 2
Scheduling and Context Switches
Lab 3
Additional Kernel Services
Lab 4
Conclusion

4. Introduction

5. Class Objectives Understand what services a real-time kernel provides
Learn how to make use of kernel services
Learn how kernels are implemented
Gain experience with an actual kernel

6. Labs Based on µC/OS-III
Real-time kernel from Micriµm
Concepts underlying the labs are not µC/OS-III-specific
Step-by-step instructions are provided for each lab

7. A µC/OS-III-Based Application
Application Code
Micriµm’s Modules
(Portable Code)
Micriµm’s Modules
(Hardware-Specific Code)
Hardware

8. A µC/OS-III-Based Application (Cont.)
Application Code
µC/OS-III
µC/CPU
µC/LIB
µC/OS-III
µC/CPU
BSP
Hardware

9. Directory Structure
Workspace files

10. e2 Studio IDE supporting Renesas MCUs Based on Eclipse
A variety of debugging features

11. Lab 1

12. Lab 1 Summary The kernel is built alongside application code
A kernel-based application looks much like any other C program
Application code interacts with the kernel through API functions

13. Foreground/Background Systems

14. A Foreground/Background Example
int main (void) { Perform initializations; while (1) { ADC_Read(); SPI_Read(); USB_Packet(); LCD_Update(); Audio_Decode(); File_Write(); }
void USB_ISR (void) { Clear interrupt; Read packet; }

15. Foreground/Background Benefits
No upfront cost
Minimal training required
Developers don’t need to learn a kernel’s API
No need to set aside memory resources to accommodate a kernel
There is a small amount of overhead associated with a kernel

16. Foreground/Background Drawbacks
Difficult to ensure that each operation will meet its deadline
All code in the background essentially has the same importance, or priority
while (1) {
ADC_Read();
SPI_Read();
USB_Packet();
Service other devices; }
void ADC_Read (void) {
Initialize ADC;
while (conv_rdy == 0) { ; }
Process converted value;
Potential to delay entire application

17. Foreground/Background Drawbacks (Cont.)
High-priority code must be placed in the foreground (in an ISR)
Lengthy ISRs can negatively impact system responsiveness
while (1) {
ADC_Read();
SPI_Read();
USB_Packet();
LCD_Update();
Audio_Decode();
File_Write(); }
void USB_ISR (void) {
Clear interrupt;
Read packet; }
If a USB packet is received immediately after this function returns, the response time will be lengthy.

18. Foreground/Background Drawbacks (Cont.)
Problems with multiple developers
Developers’ efforts must be closely coordinated
Difficult expansion, even with one developer
Changes to one portion of the application may negatively impact the remainder of the code

19. Kernel-Based Applications

20. A Kernel-Based Example
Tasks
ISRs
void AppTaskADC (void *p_arg) { while (1) { ADC_Read(); Sleep for 1 ms; } void AppTaskUSB (void *p_arg) Wait for signal from ISR; USB_Packet();
void AppISRUSB (void) { Clear interrupt; Signal USB Task; }

21. Kernel Basics Application is divided into tasks
Kernel shares CPU amongst tasks
Developer may assign importance, or priority, to each task

22. Template Task static void AppTaskExample (void *p_arg) {
Perform initializations;
while (1) {
Work toward task’s goals; }

23. Initiating Multitasking

24. Initializing and Starting the Kernel
Application code must initialize the kernel
µC/OS-III is typically initialized in main()
Initialization accomplished through kernel API functions

25. OSInit() Must be invoked before any kernel services are used
Initializes data structures
Creates internal tasks
Number of tasks depends on configuration

26. µC/OS-III Internal Tasks
Always present
Idle Task
Automatically given lowest
priority
Tick Task
Synchronized with a periodic
interrupt
Allows µC/OS-III to provide
time delays
Optional
Statistics Task
Monitors resource usage
ISR Handler Task
Facilitates deferred interrupt scheme
Timer Task
Manages software timers

27. Creating a Task
void OSTaskCreate (OS_TCB *p_tcb, CPU_CHAR *p_name, OS_TASK_PTR p_task, void *p_arg, OS_PRIO prio, CPU_STK *p_stk_base, CPU_STK *p_stk_limit, OS_STK_SIZE stk_size, OS_MSG_QTY q_size, OS_TICK time_quanta, void *p_ext, OS_OPT opt, OS_ERR *p_err);
The task itself
The task’s priority
A pointer to the task’s stack

28. A Task Control Block (TCB)
Contains information on the task’s status
StkPtr
ExtPtr
StkLimitPtr
NextPtr
fields
PrevPtr

29. Stacks Each task has a stack Context is stored on stacks
Stack growth conventions vary
across platforms
Higher memory addresses
PSW (0x )
PC (p_task)
R15 (0x )
R14 (0x )
R13 (0x )
R12 (0x )
R11 (0x )
R10 (0x )
R9 (0x )
R8 (0x )
R7 (0x )
R6 (0x )
R5 (0x )
R4 (0x )
R3 (0x )
R2 (0x )
p_stk
R1 (p_arg)
Lower memory addresses

30. OSStart() Runs highest priority task Initializes CPU registers
Should be the last function called from main()

31. Lab 2

32. Lab 2 Summary
Application code creates tasks by calling kernel API functions
Each task has its own stack
A priority must be assigned to each task

33. Scheduling and Context Switches

34. Two Types of Multitasking
Scheduling differs from kernel to kernel
There are two common approaches to scheduling multiple tasks
Cooperative scheduling
Preemptive scheduling

35. Cooperative Scheduling
Interrupt signals the availability of Task A’s data
ISR
Task A
Task A cannot run until Task B completes
Task B
Time

36. Preemptive Scheduling
Interrupt signals the availability of the high-priority task’s data
ISR
The high-priority task is scheduled by the kernel
High-Priority Task
Low-Priority Task
Time

37. Round-Robin Scheduling
Task A
Task B
Task C
Time Quantum
Time

38. Scheduling in µC/OS-III
µC/OS-III is preemptive
Finds highest-priority, ready task
Scheduling can be optimized
Assembly language, tables
Round-robin scheduling is performed only when enabled

39. OSTCBCurPtr->StkPtr
Context Switch
Switch from Task A to Task B
Load new stack pointer
Pop registers from stack
Update kernel variables
Save stack pointer
Push registers onto stack
OSPrioCur
OSTCBCurPtr->StkPtr
OSTCBCurPtr
PSW
R0 (SP)
PSW PC PC R1 R1 R1 R2 R2 R2 R3 R3 R3 R4 R4 R4 R5 R5 R5 R6 R6 R6
PSW R7 R7 R7 PC R8 R8 R8 R9 R9 R9
R10
R10
R10
R11
R11
R11
R12
R12
R12
R13
R13
R13
R14
R14
R14
R15
R15
R15
Task A’s stack
Task B’s stack

40. Interrupts
In a preemptive kernel, interrupt handlers are capable of triggering context switches
ExampleISR:
Save CPU registers;
OSIntEnter();
AppISR();
OSIntExit();
Restore CPU registers;
Return from interrupt;
void AppISR (void) {
/* Clear interrupt */
/* Signal task */ }
Determine whether a context switch is needed

41. The Tick Interrupt
Most kernels keep track of time via a periodic interrupt, often called a “tick”
A kernel can use its tick interrupt to implement a number of useful features:
Time delays
Software timers
Timeouts for blocking API functions

42. Time Delays
void OSTimeDly (OS_TICK dly, OS_OPT opt, OS_ERR *p_err); void OSTimeDlyHMSM (CPU_INT16U hours, CPU_INT16U minutes, CPU_INT16U seconds, CPU_INT32U milli,

43. Lab 3

44. Lab 3 Summary
Most µC/OS-III ISRs are written at least partially in assembly language
ISRs must perform a few kernel-specific operations
An interrupt can be set up with a fairly small amount of code

45. Additional Kernel Services

46. Beyond Task Management
A kernel does more than just switch between tasks
Synchronization
Inter-task communication
Resource protection

47. Synchronization Can be thought of as signaling
Tasks can be signaled by ISRs or other tasks
While one tasks waits for a signal, the kernel runs other tasks

48. Semaphores A means of synchronization Based on a counter
Counter value indicates whether or not an event has occurred
Two basic operations
Pend: wait for event
Post: signal occurrence of event

49. Semaphore API
void OSSemCreate (OS_SEM *p_sem, CPU_CHAR *p_name, OS_SEM_CTR cnt, OS_ERR *p_err); OS_SEM_CTR OSSemPend (OS_SEM *p_sem, OS_TICK timeout, OS_OPT opt, CPU_TS *p_ts, OS_SEM_CTR OSSemPost (OS_SEM *p_sem,

50. Semaphore Example Statistics Task Display Task OS_SEM AppSemDisp;
/* Initialization Code */
OSSemCreate((OS_SEM *)&AppSemDisp,
(CPU_CHAR *)”Disp Sem”,
(OS_SEM_CTR)0,
(OS_ERR *)&err);
void AppTaskStat (void *p_arg) {
Perform initializations;
while (1) {
Read signals;
Calculate statistics;
OSSemPost((OS_SEM *)&AppSemDisp,
(OS_OPT )OS_OPT_POST_1,
(OS_ERR *)&err);
Delay for 5 ms; }
Statistics Task
Display Task
void AppTaskDisp (void *p_arg) {
while (1) {
OSSemPend((OS_SEM *)&AppSemDisp,
(OS_TICK )100,
(OS_OPT )OS_OPT_PEND_BLOCKING,
(CPU_TS *)&ts,
(OS_ERR *)&err);
Update display; }

51. Task Semaphores An alternative to standard semaphores in µC/OS-III
Lower overhead
Type
SemCtr
NamePtr
TCB
SemPendTime
OS_SEM
PendList
SemPendTimeMax
Ctr TS

52. Event Flags Another means of synchronization
Each event represented by a bit
Pend and post operations
Pend for multiple events

53. Event Flag API
void OSFlagCreate (OS_FLAG_GRP *p_grp, CPU_CHAR *p_name, OS_FLAGS flags, OS_ERR *p_err); OS_FLAGS OSFlagPend (OS_FLAG_GRP *p_grp, OS_TICK timeout, OS_OPT opt, CPU_TS *p_ts, OS_FLAGS OSFlagPost (OS_FLAG_GRP *p_grp,

54. Shared Resources
Peripheral devices, buffer pools, or simple global variables
Accessed by more than one task or by at least one task and one ISR
Can cause race conditions

55. Shared Resource Example
void AppTaskUART (void *p_arg) { Perform initializations; while (1) { Write message to UART; Delay for 1s; }
void AppTaskFS (void *p_arg) { Perform initializations; while (1) { Read file; Write status to UART; }

56. Protecting Shared Resources
Disabling and enabling interrupts
Locking and unlocking the scheduler
Semaphores
Mutexes

57. Mutexes Implemented much like semaphores
Manipulated through pend and post functions
Offer protection against priority inversion

58. Mutex API
void OSMutexCreate (OS_MUTEX *p_mutex, CPU_CHAR *p_name, OS_ERR *p_err); void OSMutexPend (OS_MUTEX *p_mutex, OS_TICK timeout, OS_OPT opt, CPU_TS *p_ts, void OSMutexPost (OS_MUTEX *p_mutex,

59. Mutex Example Pressure Task Error Task OS_MUTEX AppMutexSD;
/* Initialization Code */
OSMutexCreate((OS_MUTEX *)&AppMutexSD,
(CPU_CHAR *)”SDCard Mutex”,
(OS_ERR *)&err);
void AppTaskError (void *p_arg) {
while (1) {
Check for errors;
OSMutexPend((OS_MUTEX *)&AppMutexSD,
(OS_TICK )50,
(OS_OPT )OS_OPT_PEND_BLOCKING,
(CPU_TS *)&ts,
(OS_ERR *)&err);
Write errors to SD card;
OSMutexPost((OS_MUTEX *)&AppMutexSD,
(OS_OPT )OS_OPT_POST_NONE, }
void AppTaskPressure (void *p_arg) {
while (1) {
Read pressure;
OSMutexPend((OS_MUTEX *)&AppMutexSD,
(OS_TICK )50,
(OS_OPT )OS_OPT_PEND_BLOCKING,
(CPU_TS *)&ts,
(OS_ERR *)&err);
Write pressure to SD card;
OSMutexPost((OS_MUTEX *)&AppMutexSD,
(OS_OPT )OS_OPT_POST_NONE, }
Pressure Task
Error Task

60. Inter-Task Communication
Sending and receiving messages
Tasks can send or receive
ISRs can send
Messages stored in a queue managed by the kernel
While one task waits for a message, other tasks run

61. Message Queue API
void OSQCreate (OS_Q *p_q, CPU_CHAR *p_name, OS_MSG_QTY max_qty, OS_ERR *p_err); void *OSQPend (OS_Q *p_q, OS_TICK timeout, OS_OPT opt, OS_MSG_SIZE *p_msg_size, CPU_TS *p_ts, void OSQPost (OS_Q *p_q, void *p_void, OS_MSG_SIZE msg_size,

62. Message Queue Example ADC Task ISR ADC OS_Q AppQADC;
/* Initialization Code */
OSQCreate((OS_Q *)&AppQADC,
(CPU_CHAR *)”ADC Queue”,
(OS_MSG_QTY)20,
(OS_ERR *)&err);
ADC Task
ISR
void AppISRADC (void) {
Read new value;
Clear ADC interrupt;
OSQPost((OS_Q *)&AppQADC,
(void *)adc_val,
(OS_MSG_SIZE)msg_size,
(OS_OPT )OS_OPT_POST_FIFO,
(OS_ERR *)&err); }
void AppTaskADC (void *p_arg) {
while (1) {
adc_val = (CPU_INT32U)OSQPend((OS_Q *)&AppQADC,
(OS_TICK )0,
(OS_OPT )OS_OPT_PEND_BLOCKING,
(OS_MSG_SIZE *)&msg_size,
(CPU_TS *)&ts,
(OS_ERR *)&err);
Process value; }
ADC
Note that it is possible to use queues for resource protection: a single task manages a particular I/O device and receives requests to manipulate that device from other tasks via a queue.

63. Task Message Queue Message queue included in TCB
Less overhead than standard message queue
Can be used whenever only one task will be receiving messages

64. Additional Services Multi-pend Dynamic memory allocation Timers
Pend on multiple queues and semaphores
Dynamic memory allocation
Timers
One-shot and periodic software timers with callbacks

65. Lab 4

66. Lab 4 Summary
In general, it is desirable to keep interrupt handlers as short as possible
Using semaphores, interrupt handlers can signal tasks
The two primary semaphore operations are pend and post

67. Conclusion

68. Summary Today we discussed…
The differences between foreground/background systems and kernel-based applications
How a kernel is initialized
The contents of a task
How a kernel schedules tasks

69. Summary (Cont.) Today we discussed…
What happens during a context switch
The structure of ISRs in kernel-based applications
Synchronization, mutual exclusion, and inter-task communication services

70. Questions?
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